MOTOROLA MCM72FB8ML8R 256k x 72 bit burst ram multichip module Datasheet

MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
Advance Information
256K x 72 Bit BurstRAM
Multichip Module
The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC and other high performance microprocessors. It is organized as
256K words of 72 bits each. This device integrates input registers, an output register (MCM72PB8ML only), a 2–bit address counter, and high speed SRAM onto
a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally (burst sequence operates in linear or
interleaved mode dependent upon the state of LBO) and controlled by the burst
address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The eight bytes are designated as “a” through “h”. SBa controls DQa,
SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx
are asserted with SW. All bytes are written if either SGW is asserted or if all SBx
and SW are asserted.
The module can be configured as either a pipelined or flow–through SRAM.
For read cycles, pipelined SRAMs output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (K). Flow–through SRAMs allow output to simply flow freely from
the memory array.
The multichip module operates from a 3.3 V core power supply and all outputs
operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are
JEDEC standard JESD8–5 compatible.
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Option for Pipeline or Flow–Through (Speeds Guaranteed When Module is
Purchased by Appropriate Part Number)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• JEDEC BGA Pin Assignment
MCM72FB8ML
MCM72PB8ML
MULTICHIP MODULE
PBGA
CASE 1103B–01
PIN A1
INDICATION
(corner without
fiducial)
TOP VIEW
PIN A1
BOTTOM VIEW
INDICATION
(corner with (Drawings Not to Scale)
fiducial)
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
7/30/97

Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM72FB8ML MCM72PB8ML
1
256K X 72 FOUR–CHIP MODULE BLOCK DIAGRAM
SA2 – SA17
SA0
SA1
ADSP
ADSC
ADV
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT
18
MCM69P/F819DC*
SA2 – SA17
SA0
LW
SA1
DQ0 – DQ8
ADSP
ADSC
UW
ADV
DQ9 – DQ17
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT
MCM69P/F819DC*
SA2 – SA17
SA0
LW
SA1
DQ0 – DQ8
ADSP
ADSC
UW
ADV
DQ9 – DQ17
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT
MCM69P/F819DC*
SA2 – SA17
SA0
LW
SA1
DQ0 – DQ8
ADSP
ADSC
UW
ADV
DQ9 – DQ17
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT
MCM69P/F819DC*
SA2 – SA17
SA0
LW
SA1
DQ0 – DQ8
ADSP
ADSC
UW
ADV
DQ9 – DQ17
K
G
SE1
SE2
SE3
LBO
SW
SGW
FT
SBa
SBb
SBc
SBd
SBe
SBf
SBg
SBh
9
9
9
9
9
9
9
9
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
* Motorola TrueDie devices.
MCM72FB8ML MCM72PB8ML
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
A
B
C
D
5
6
7
8
9
10
11
12
13
14
15
DQe
DQe
SA
SA
SA
SE1
SA
SA
SA
DQd
DQd
DQe
DQe
SA
SA
SA
G
SA
SA
SA
DQd
DQd
DQe
DQe
SE2 VDDQ VDDQ SGW VDDQ VDDQ SE3
DQd
DQd
DQe
DQe VDDQ VDD
VSS
VDD VDDQ DQd
DQd
DQe
DQf VDDQ VDD
VSS ADSC VSS
VDD
VDDQ DQc
DQd
DQf
DQf VDDQ VDD
VSS
ADSP
VSS
VDD
VDDQ DQc
DQc
DQf
DQf VDDQ VDD
VSS
VSS
VSS
VDD VDDQ DQc
DQc
DQf
DQf VDDQ VSS
VSS
VSS
VSS
VSS VDDQ
DQc
DQc
DQf
DQf
SBe
VSS
VSS
VSS
VSS
VSS
SBd
DQc
DQc
SBf
SBg
NC
VSS
VSS
VSS
VSS
VSS
NC
SBb
SBc
DQg
DQg
SBh
VSS
VSS
VSS
VSS
VSS
SBa
DQb
DQb
DQg
DQg
VDDQ VSS
VSS
VSS
VSS
VSS
VDDQ DQb
DQb
DQg
DQg
VDDQ VDD
VSS
VSS
VSS
VDD
VDDQ DQb
DQb
DQg
DQg
VDDQ VDD
VSS
NC
VSS
VDD
VDDQ DQb
DQb
DQg
DQh
VDDQ VDD
VSS
K
VSS
VDD
VDDQ DQa
DQb
DQh
DQh
VDDQ VDD
VSS
SW
VSS
VDD
VDDQ DQa
DQa
DQh
DQh
LBO
VDDQ VDDQ SA1 VDDQ
VDDQ FT
DQa
DQa
DQh
DQh
NC
SA
SA
SA0
SA
SA
NC
DQa
DQa
DQh
DQh
NC
NC
NC
NC
NC
NC
NC
DQa
DQa
ADV
VSS
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
TOP VIEW
256K X 72 JEDEC FOUR–CHIP MODULE
209 BUMP PBGA
Not to Scale
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
3
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
E10
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate
READ, WRITE, or chip deselect cycle.
F10
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate
READ, WRITE, or chip deselect cycle (exception — chip deselect
does not occur when ADSP is asserted and SE1 is high).
D10
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
DQx
I/O
U13
FT
Input
Flow–Through Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through mode.
High — pipeline mode.
B10
G
Input
Asynchronous Output Enable.
R10
K
Input
Clock: This signal registers the address, data in, and all control
signals except G, LBO, and FT.
U7
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
U10, V10
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs
are registered and must meet setup and hold times.
A7, A8, A9, A11, A12, A13, B7, B8, B9,
B11, B12, B13, V8, V9, V11, V12
SA2 – SA17
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
L13, K14, K15, J13, J7, K5, K6, L7
(a) (b) (c) (d) (e) (f) (g) (h)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d, e, f, g, h). SGW overrides SBx.
A10
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high–blocks ADSP or deselects chip when ADSC is
asserted.
C7
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
C13
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
C10
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of
the status of the SBx and SW signals. If only byte write signals SBx
are being used, tie this pin high.
T10
SW
Input
Synchronous Write: This signal writes only those bytes that have
been selected using the byte write SBx pins. If only byte write
signals SBx are being used, tie this pin low.
D8, D12, E8, E12, F8, F12, G8,
G12, N8, N12, P8, P12, R8, R12, T8, T12
VDD
Supply
Core Power Supply.
C8, C9, C11, C12, D7, D13, E7,
E13, F7, F13, G7, G13, H7, H13,
M7, M13, N7, N13, P7, P13, R7,
R13, T7, T13, U8, U9, U11, U12
VDDQ
Supply
I/O Power Supply.
(a) R14, T14, T15, U14, U15, V14, V15,
W14, W15
(b) L14, L15, M14, M15, N14, N15, P14,
P15, R15
(c) E14, F14, F15, G14, G15, H14, H15,
J14, J15
(d) A14, A15, B14, B15, C14, C15, D14,
D15, E15
(e) A5, A6, B5, B6, C5, C6, D5, D6, E5
(f) E6, F5, F6, G5, G6, H5, H6, J5, J6
(g) L5, L6, M5, M6, N5, N6, P5, P6, R5
(h) R6, T5, T6, U5, U6, V5, V6, W5, W6
MCM72FB8ML MCM72PB8ML
4
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d, e, f, g, h).
MOTOROLA FAST SRAM
PIN DESCRIPTIONS (continued)
Pin Locations
Symbol
Type
D9, D11, E9, E11, F9, F11, G9 – G11,
H8 – H12, J8 – J12, K8 – K12, L8 – L12,
M8 – M12, N9 – N11, P9, P11, R9, R11,
T9, T11
VSS
Supply
Description
K7, K13, P10, V7, V13, W7 – W13
NC
—
Ground.
No Connection: There is no connection to the chip.
TRUTH TABLE (See Notes 1 through 5)
Address
Used
SE1
SE2
SE3
ADSP
Deselect
None
1
X
X
Deselect
None
0
X
1
Deselect
None
0
0
Deselect
None
X
X
Next Cycle
Deselect
ADSC
ADV
G3
DQx
Write 2, 4
X
0
X
X
High–Z
X
0
X
X
X
High–Z
X
X
0
X
X
X
High–Z
X
1
1
0
X
X
High–Z
X
None
X
0
X
1
0
X
X
High–Z
X
Begin Read
External
0
1
0
0
X
X
X
High–Z
X5
Begin Read
External
0
1
0
1
0
X
X
High–Z
READ5
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
5
WRITE TRUTH TABLE
SGW
SW
SBa
SBb
SBc
SBd
SBe
SBf
SBg
SBh
Read
Cycle Type
H
H
X
X
X
X
X
X
X
X
Read
H
L
L
H
H
H
H
H
H
H
Write Byte a
H
L
L
H
H
H
H
H
H
H
Write Byte b
H
L
H
L
H
H
H
H
H
H
Write Byte c
H
L
H
H
L
H
H
H
H
H
Write Byte d
H
L
H
H
H
L
H
H
H
H
Write Byte e
H
L
H
H
H
H
L
H
H
H
Write Byte f
H
L
H
H
H
H
H
L
H
H
Write Byte g
H
L
H
H
H
H
H
H
L
H
Write Byte h
H
L
H
H
H
H
H
H
H
L
Write All Bytes
H
L
L
L
L
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
X
X
X
X
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Power Supply Voltage
I/O Supply Voltage
Symbol
Value
Unit
VDD
VSS – 0.5 to + 4.6
V
Notes
VDDQ
VSS – 0.5 to VDD
V
2
Vin, Vout
VSS – 0.5 to
VDD + 0.5
V
2
Input Voltage (Three–State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
± 20
mA
Package Power Dissipation
PD
6.4
W
Ambient Temperature
TA
0 to 70
°C
Die Temperature
TJ
110
°C
Tbias
– 10 to 85
°C
Tstg
– 55 to 125
°C
Input Voltage Relative to VSS for
Any Pin Except VDD
Temperature Under Bias
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
3
3
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Symbol
Max
Unit
Notes
RθJA
19
13
°C/W
1, 2
Junction to Board (Bottom)
RθJB
10
°C/W
3
Junction to Case (Top)
RθJC
0.3
°C/W
4
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
MCM72FB8ML MCM72PB8ML
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
I/O Supply Voltage
VDDQ
2.375
2.5
2.9
V
Input Low Voltage
VIL
– 0.3
—
0.7
V
Input High Voltage
VIH
1.7
—
VDD + 0.3
V
Input High Voltage I/O Pins
VIH2
1.7
—
VDDQ + 0.3
V
Supply Voltage
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter
Supply Voltage
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.465
V
I/O Supply Voltage
VDDQ
3.135
3.3
VDD
V
Input Low Voltage
VIL
– 0.5
—
0.8
V
Input High Voltage
VIH
2
—
VDD + 0.5
V
Input High Voltage I/O Pins
VIH2
2
—
VDDQ + 0.5
V
VIH
VSS
VSS – 1.0 V
20% tKHKH (MIN)
Figure 1. Undershoot Voltage
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
7
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(I)
—
—
±1
µA
Output Leakage Current (0 V ≤ Vin ≤ VDDQ)
Ilkg(O)
—
—
±1
µA
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max)
Includes Supply Current from Both VDD and VDDQ
IDDA
—
—
1700
mA
1, 2, 3
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels)
ISB2
—
—
TBD
mA
4. 5
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
—
—
TBD
mA
4, 6
Clock Running (Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max, All Inputs Toggling at
CMOS Levels)
ISB4
—
—
TBD
mA
4. 5
Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB5
—
—
TBD
mA
4, 6
Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V
VOL1
—
—
0.7
V
Output High Voltage (IOH = – 2 mA) VDDQ = 2.5 V
VOH1
1.7
—
—
V
Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V
VOL2
—
—
0.4
V
Output High Voltage (IOH = – 4 mA) VDDQ = 3.3 V
VOH2
2.4
—
—
V
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) then high (MSB).
3. Data states are all zero.
4. Device is deselected as defined by the Truth Table.
5. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
6. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
—
16
pF
Input/Output Capacitance
CI/O
—
—
5
pF
MCM72FB8ML MCM72PB8ML
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time (See Figure 3) . . . . . . . . . 1.0 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
Pipeline
MCM72PB8ML3.5
166 MHz
P
Parameter
Pipeline
MCM72PB8ML4
133 MHz
Flow–Through
MCM72FB8ML7.5
117 MHz
Flow–Through
MCM72FB8ML8
100 MHz
S b l
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
U i
Unit
Cycle Time
tKHKH
6
—
7.5
—
8.5
—
10
—
ns
Clock High Pulse Width
tKHKL
2.4
—
3
—
3.4
—
4
—
ns
3
Clock Low Pulse Width
tKLKH
2.4
—
3
—
3.4
—
4
—
ns
3
Clock Access Time
tKHQV
—
3.5
—
4
—
7.5
—
8
ns
Output Enable to Output
Valid
tGLQV
—
3.5
—
3.8
—
3.5
—
3.5
ns
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
0
—
ns
4, 5
Clock High to Output
Change
tKHQX2
1.5
—
1.5
—
2
—
2
—
ns
4
Output Enable to Output
Active
tGLQX
0
—
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
tGHQZ
—
3.5
—
3.8
—
3.5
—
3.5
ns
4, 5
Clock High to Q High–Z
4, 5
tKHQZ
1.5
6
1.5
7.5
2
3.5
2
3.5
ns
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
1.5
—
1.5
—
2
—
2
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
ns
N
Notes
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
1.25 V
Figure 2. AC Test Load
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
9
OUTPUT LOAD
OUTPUT
BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT
2.0
INPUT
WAVEFORM
2.0
0.5
0.5
2.0
OUTPUT
WAVEFORM
2.0
0.5
tr
0.5
tf
NOTES:
1. Input waveform has a slew rate of 1 V/ns.
2. Rise time tr is measured from 0.5 to 2.0 V unloaded.
3. Fall time tf is measured from 2.0 to 0.5 V unloaded.
Figure 3. Unloaded Rise and Fall Time Characterization
MCM72FB8ML MCM72PB8ML
10
MOTOROLA FAST SRAM
PULL–UP
VOLTAGE (V)
I (mA) MIN
I (mA) MAX
– 0.5
– 38
– 105
0
– 38
– 105
– 38
– 105
– 26
– 83
1.5
– 20
– 70
2.3
0
– 30
2.7
0
– 10
2.9
0
0
2.3
2.1
VOLTAGE (V)
0.8
1.25
2.9
2.5
1.25
0.8
0
0
– 38
CURRENT (mA)
– 105
– 100
– 50
CURRENT (mA)
– 150
(a) Pull–Up for 2.5 V I/O Supply
3.6
3.135
2.8
PULL–UP
I (mA) MIN
I (mA) MAX
– 0.5
– 50
– 150
0
– 50
– 150
1.4
– 50
– 150
1.65
– 46
– 130
2.0
– 35
– 101
3.135
0
– 25
3.6
0
0
VOLTAGE (V)
VOLTAGE (V)
1.65
1.4
0
0
(b) Pull–Up for 3.3 V I/O Supply
VDD
PULL–DOWN
I (mA) MIN
I (mA) MAX
– 0.5
0
0
0
0
0
0.4
10
20
0.8
20
40
1.25
31
63
1.6
40
80
2.8
40
80
3.2
40
80
3.4
40
80
1.6
VOLTAGE (V)
VOLTAGE (V)
1.25
0.3
0
0
40
CURRENT (mA)
80
(c) Pull–Down
Figure 4. Typical Output Buffer Characteristics
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
11
MCM72FB8ML MCM72PB8ML
12
MOTOROLA FAST SRAM
Q(n)
B
SINGLE READ
tKHQX1
A
Q(A)
Q(B)
tKHQX2
t KHQV
tKHKL
NOTE: E low = SE2 high and SE3 low.
W low = SGW low and/or SW and SBx low.
DESELECTED
tKHQZ
DQx
G
W
E
SE1
ADV
ADSC
ADSP
SA
K
tKHKH
Q(B+2)
BURST READ
Q(B+1)
tGHQZ
Q(B+3)
BURST WRAPS AROUND
tKLKH
Q(B)
ADSP, SA
SE2, SE3
IGNORED
D(C)
C
MCM72PB8ML PIPELINE READ/WRITE CYCLES
D(C+2)
BURST WRITE
D(C+1)
D(C+3)
tGLQX
D
SINGLE READ
Q(D)
t KHQV
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
13
Q(n)
A
SINGLE READ
tKHQX1
Q(A)
tKHQV
B
tKHKL
NOTE: E low = SE2 high and SE3 low.
W low = SGW low and/or SW and SBx low.
DESELECTED
tKHQZ
DQx
G
W
E
SE1
ADV
ADSC
ADSP
SA
K
tKHKH
tKHQX2
Q(B)
Q(B+2)
BURST READ
Q(B+1)
tGHQZ
Q(B+3)
BURST WRAPS AROUND
tKLKH
Q(B)
ADSP, SA
SE2, SE3
IGNORED
D(C)
C
D(C+2)
BURST WRITE
D(C+1)
MCM72FB8ML FLOW–THROUGH READ/WRITE CYCLES
D(C+3)
SINGLE READ
tGLQX
tGLQV
D
Q(D)
APPLICATION INFORMATION
STOP CLOCK OPERATION
In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP and ADSC, and stops the clock after the last
write data is latched, or the last read data is driven out.
When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.
To achieve the lowest power operation for all three stop
clock modes, stop read, stop write, and stop deselect:
1. Force the clock to a low state.
2. Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input
will not start an unplanned on activity).
3. Force the address inputs to a low state.
MCM72PB8ML PIPELINE STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
Q(A1)
DQx
ADSP
(INITIATES
BURST READ)
CLOCK STOP
(CONTINUE
BURST READ)
Q(A1 + 1)
Q(A2)
WAKE UP ADSP
(INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).
Best results are obtained if VIL < 0.2 V.
MCM72FB8ML MCM72PB8ML
14
MOTOROLA FAST SRAM
MCM72FB8ML FLOW–THROUGH STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
Q(A1)
DQx
ADSP
(INITIATES
BURST READ)
CLOCK STOP
(CONTINUE
BURST READ)
Q(A1 + 1)
Q(A2)
WAKE UP ADSP
(INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).
Best results are obtained if VIL < 0.2 V.
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
15
STOP CLOCK WITH WRITE TIMING
K
ADSC
ADDRESS
A1
A2
WRITE
ADV
DATA IN
D(A1)
D(A1 + 1)
VIH OR VIL FIXED (SEE NOTE)
D(A2)
HIGH–Z
DQx
ADSC
(INITIATES
BURST WRITE)
CLOCK STOP
(CONTINUE
BURST WRITE)
WAKE UP ADSC
(INITIATES BURST WRITE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
MCM72FB8ML MCM72PB8ML
16
MOTOROLA FAST SRAM
STOP CLOCK WITH DESELECT OPERATION TIMING
K
ADSC
SE1
DATA IN
VIH OR VIL FIXED (SEE NOTE 1)
HIGH–Z
DQx
DATA
CONTINUE
BURST READ
DATA
CLOCK STOP
(DESELECTED)
WAKE UP
(DESELECTED)
NOTES:
1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
2. For best possible power savings, the data–in should be driven low.
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
17
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous interface can make use of the MCM72FB8ML or MCM72PB8ML.
The burst counter feature of the BurstRAM can be disabled,
and the SRAM can be configured to act upon a continuous
stream of addresses. See Figures 5 and 6.
CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)
Non–Burst
Sync Non–Burst,
Pipelined SRAM
ADSP
ADSC
ADV
SE1
LBO
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
D(E)
D(F)
D(G)
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
READS
D(H)
WRITES
Figure 5. Configured as Non–Burst Synchronous Flow–Through SRAM
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
READS
D(G)
D(H)
WRITES
Figure 6. Configured as Non–Burst Synchronous Pipelined SRAM
MCM72FB8ML MCM72PB8ML
18
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
72FB8
72PB8
XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed for MCM72FB8 (7.5 = 7.5 ns, 8 = 8 ns)
Speed for MCM72PB8 (3.5= 3.5 ns, 4 = 4 ns)
Package (ML = Multichip Module on Laminate)
Full Part Numbers — MCM72FB8ML7.5
MCM72FB8ML7.5R
MCM72FB8ML8
MCM72FB8ML8R
MCM72PB8ML3.5
MCM72PB8ML3.5R
MCM72PB8ML4
MCM72PB8ML4R
PACKAGE DIMENSIONS
MULTICHIP MODULE
PBGA
CASE 1103B–01
2X
0.2
D
A1
CORNER
C
A
0.2 C
209X
0.35 C
4X
(E3)
E
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DIMENSIONS D2, D3, E2, AND E3 ARE FOR
INFORMATION ONLY.
(E2)
2X
0.2
(D2)
(D3)
209X
B
TOP VIEW
b
0.30
M
A B C
0.15
M
A
5 6 7 8 9 10 11 12 13 14 15
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
D1
e
A2
DIM
A
A1
A2
b
D
D1
D2
D3
e
E
E1
E2
E3
MILLIMETERS
MIN
MAX
2.00
2.90
0.50
0.70
0.80
1.20
0.60
0.90
25.00 BSC
22.86 BSC
7.14 REF
14.05 REF
1.27 BSC
25.00 BSC
12.70 BSC
7.14 REF
14.05 REF
A
A1
SIDE VIEW
E1
BOTTOM VIEW
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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How to reach us:
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MCM72FB8ML MCM72PB8ML
20
MOTOROLAMCM72FB8ML/D
FAST SRAM
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