Freescale MCZ33285EFR2 Dual high-side tmos driver Datasheet

Freescale Semiconductor
Advance Information
Document Number: MC33285
Rev. 5.0, 2/2007
Dual High-Side TMOS Driver
33285
A single input controls the 33285 in driving two external high-side NChannel TMOS power FETs controlling incandescent or inductive
loads. Pulse Width Modulated (PWM) input control to 1.0 kHz is
possible. The 33285 contains a common internal charge pump used to
enhance the Gate voltage of both FETs.
An external charge capacitor provides access to the charge pump
output. Both external FETs are protected against inductive load
transients by separate internal source-to-gate dynamic clamps. The
power FETs are protected by the 33285 with short-circuit delay time of
800 µs. The device is designed to withstand reverse polarity battery
and load dump transients, encountered in automotive applications.
HIGH-SIDE TMOS DRIVER
Features
• PWM Capability
• Power TMOS Number One (OUT1) Short-Circuit Detection and
Short-Circuit Protection
• Voltage Range 7.0 V ≤ 40 V
• Extended Temperature Range from -40°C ≤ 125°C
• Load Dump Protected
• Overvoltage Detection and Activation of OUT2 During
Overvoltage
• Single Input Control for Both Output Stages
• Capacitor Value of 100 nF Connected to Pin CP
• Analog Input Control Measurement Detection
• OUT1 LOAD Leakage Measurement Detection
• Pb-Free Packaging Designated by Suffix Code EF
VCC
33285
VCC
D SUFFIX
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
ORDERING INFORMATION
Device
MC33285D/R2
MCZ33285EF/R2
VPWR
DRN
CP
OUT2
Input Control
IN
GND
OUT1
SRC
Motor
Figure 1. 33285 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Temperature
Range (TA)
Package
-40°C to 125°C
8 SOICN
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGN
Oscillator
+
DRN
Charge
Pump
Bandgap
Rthr
Divider
S
-
CP
and
R
VREF
Kl.30
CCP
VCC
tLDDET
ION2
ION1
Load Dump
Detection
OUT2
IN
tOUT2ECT
THRIN2
+
OUT2 Activation
Time
VOUT2-VDRN> VTH2
R Q
S
IOUTN2
-
THRIN1
OUT1
VOUT1-VSRC> VTH1
+
IOUTN1
GND
RQ
S
OC Detection
M
+
-
SRC
SCPC
tOCDET
Start tOCDET
Figure 2. 33285 Simplified Internal Block and Typical Applications Diagram
33285
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
SRC
11
88
IN
OUT1
22
77
GND
DRN
33
66
VCC
OUT2
44
5
5
CP
Figure 3. 33285 Pin Connections
Table 1. 33285 Pin Definitions
Pin Number
Pin Name
Formal Name
Definition
1
SRC
Source
2
OUT1
Output 1
3
DRN
Drain
4
OUT2
Output 2
5
CP
Charge Pump
6
VCC
Voltage Power Supply
Battery supply voltage
7
GND
Ground
This is the ground pin.
8
IN
Input
OUT2 external FET Source connection
This pin is output number 1
OUT1 and OUT2 external FET Drain connection
This pin is output number 2
External capacitor connection for internal the Charge Pump
Voltage level sensitive input for OUT1 and OUT2
33285
Analog Integrated Circuit Device Data
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3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VOUT
VVCC + 20
V
VCP
50
V
Input Voltage VI at DRN
VDRN
-2.0 to 40
V
Input Voltage VI at SRC
VSRC
-5.0 to 40
V
Input Voltage at Pin VCC
VCC
-2.0 to 40
V
Input Voltage at Pin IN. Condition: -2.0 V < VVCC < 40 V
VIN
-2.0 to VVCC
V
VVCC
7.0 to VI
V
TSTG
-40 to150
°C
TA
-40 to 125
°C
TPPRT
Note 2
°C
ELECTRICAL RATINGS
Maximum Voltage at Pins OUT1 and OUT2
Maximum Voltage at Pin CP
Operational Voltage VVCC at Pin VCC
THERMAL RATINGS
Storage Temperature
Operating Ambient Temperature
Peak Package Reflow Temperature During Reflow (1), (2)
Notes
1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33285
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Analog Integrated Circuit Device Data
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tOUT2ACT
300
460
620
ms
VDRN - VSRC
1.12
—
1.44
V
Leakage Current
ILCDET
15
30
50
mA
Leakage Current Detection Time
tLCDET
130
200
270
µA
IDRN
—
—
1.5
mA
ILEAK-DRN
-5.0
—
5.0
µA
VON
—
—
VCC + 15
V
IOUTOFF
66
110
154
µA
Supply Voltage Range
VCC
7.0
—
40
V
Quiescent Supply Current at VCC = 20 V
ICC
—
—
10
mA
Input Low Voltage OUT1
VIL
—
—
0.7
V
Input High Voltage OUT1
VIH
1.7
—
—
V
VHYS
0.4
—
—
V
IIN
7.5
15
16.5
µA
Open Input Voltage
VIOP
—
—
0.7
V
Input Low Voltage OUT2
VIL2
—
—
3.0
V
Input High Voltage OUT2
VIH2
3.9
—
—
V
OVERVOLTAGE AND OVER CURRENT
Load Dump Activation Time
Error Voltage Threshold
SRC PIN 1
DRN PIN 3
Operating Current (7.0 V < VDRN < 20 V)
Leakage Current (0 V < VDRN < 20 V, VVCC < 4.0 V)
OUT1, PIN 2, AND OUT2 PIN 4
Output ON Voltage. Charge Pump ON
Turn OFF Current, VOUT > 0.5 V
VCC PIN 6
IN PIN 8
Input Hysteresis OUT1 and OUT2
Input Pull Down Current, 0.7 V < VIN < 6.0 V
33285
Analog Integrated Circuit Device Data
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5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Load Dump Detection Time
tLDDET
250
400
550
µs
Over Current Detection Time
tOCDET
520
800
1080
µs
tON
—
—
—
—
OVER VOLTAGE AND OVER CURRENT
OUT1 PIN 2, AND OUT2 PIN 4
Turn ON Time, OUT1: 8.0 nF, 10 µA; OUT2:16 nF, 10 µA
-7.0 V < VCC < 10 V, VOUT > VCC + 7.0
-10 V < VCC < 20 V, VOUT > VCC + 11
ms
1.5
1.5
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The power FETs are turned ON by charging their gate
capacities with a current flowing out of pins OUT1 and OUT2.
During PWM, the values of table below are guaranteed. They
IN
are measured with 8.0 nF on OUT1 and 16 nF on OUT2. Test
condition VIN: ramp 0 V ≤ 2.5 V or 2.5 V ≤ 5.0 V.
5.0 V
IN
2.5 V
THRIN2
THRIN1
VCCP
VOUT1
VOUT2
VOUT2
VVCC + 7.0
20 ms
5.0 V
2.5 V
IN
IN
2.5 V
VOUT2MAX
0V
VOUT1MAX
VOUT2
VOUT1
0V
0V
0
tON1 tON2
tON3
0
tON1
tON3
tON2
VOLTAGE VVCC
MINIMUM VOUT1, OUT2
AFTER TON1 = 100 µSEC
MINIMUM VOUT1,OUT2
AFTER TON2 = 1.0 µSEC
MINIMUM VOUT1,OUT2
AFTER TON3 = 1.5 µSEC
7.0 V < VVCC < 10 V
10 V < VVCC < 20 V
20 V < VVCC < 40 V
VVCC - 0.7 V
VVCC - 0.7 V
VVCC - 0.7 V
VVCC + 5.95 V
VVCC + 9.35 V
VVCC + 7.0 V
VVCC + 11 V
Figure 4. Turn On Behavior
Turn Off Characteristics
The output voltages at OUT1 and OUT2 are limited by
The power FETs on OUT1 and OUT2 are turned OFF by
controlling the current sources ION1, ION2 to avoid current
discharging the gate capacity with the constant discharge
flowing through the external or the internal zener diode.
current IOUTOFF.
When voltage power supply plus threshold voltage
• Discharge current IOUTxOFF is IOUTxOFF = 110 µA
(VCC + VTH) is reached, the current sources are turned OFF.
condition: VOUT x > 0.5 V ( VIN < VTHRxIN )
• Threshold VTH1 for OUT1 output voltage control is
7.0 V < VTH1 < VZ
• Test conditions for switching OFF the power FETs:
• Threshold VTH2 for OUT2 output voltage control is
1. IN open
7.0 V < VTH2 < 15 V
2. Stages disabled via pin IN
3. Stage OUT1 disabled by an over current error
33285
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTRODUCTION
The 33285 contains only one charge pump for two
outputs.The outputs, OUT1 and OUT2, are switched ON and
OFF by the input (IN) .There are three ways to control the
outputs:
OUT1 can be switched alone
OUT1 and OUT2 can be switched together
OUT2 can be switched when OUT1 is already on
In the last case, the voltage drop on OUT1 when charging
OUT2 is limited.
The external capacitor (CCP) connected to the CHARGE
PUMP (CP) pin is used to store the charge continuously
delivered by the charge pump. The voltage on this pin is
limited to a maximum value VCPMAX. Both outputs are
sourced with a constant current from CCP to switch them ON.
Additionally, the gates of the power FETs are precharged
from voltage power supply (VCC) to prevent CCP from being
discharged by a voltage on OUT1 or OUT2, is still lower than
VVCC. The values of the output voltages are limited to
VOUT1MAX and VOUT2MAX.
The power FET on OUT1 is protected against an
exceeded gate-source voltage by an internal zener diode.
Channel One protects the N-Channel power FET on OUT1
undercurrent and short-circuit conditions. The drain-source
voltage of the FET on OUT1 is checked if Channel One is
switched ON. The internal error voltage threshold determines
the maximum drain-source voltage allowing the power FET to
stay in the ON state. If the measured drain-source voltage
exceeds the internal error voltage threshold, the output of the
short-circuit protection comparator (SCPC) is enabled. If the
output of the SCPC is active longer than tOCDET, output
OUT1 is switched OFF.
After switching OFF the power FET on OUT1 by an shortcircuit condition, the power FET can only be turned ON again
by the input IN.
When switching OFF the power FETs their gate capacities
are discharged by a constant current, IOUTOFF.
If the input IN is disconnected, the 33285 outputs, OUT1
and OUT2, are in the OFF state.
If overvoltage occurs on the DRAIN (DRN) pin for a time
period longer than tLDDET, OUT2 is switched ON for the time
tOUT2ACT. In an overvoltage condition OUT1 is OFF if IN is
below VIH.
INTERNAL ZENER DIODE
An on-chip zener diode is placed between OUT1 and The
SOURCE (SRC). Design guarantees VZ > VTH1. Zener
clamping voltage between OUT1 and SRC is VTH1 < VZ <
20 V
PWM CAPABILITY
The CPIC2 is PWM capable on OUT2. The loss of charge
ON CCP when switching ON OUT2 is refreshed until the Start
on the next PWM cycle to a value sufficient to guarantee the
specified turn ON behavior.
The PWM capability is measured with a test circuit and
load conditions:
• PWM cycle is period T = 20 ms ; OUT2 is switched ON
from 10 to 90 percent of T
• Test condition VIN ramps 2.5 V ≤ 5.0 V according to PWM
cycle defined above
CROSS TALK BETWEEN OUT1 AND OUT2
If output OUT2 is switched ON while OUT1 is already ON,
the voltage drop occurring on OUT1 is limited.
Voltage drop on OUT1:
• 10 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V
• 7.0 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V
Each time OUT1 is switched ON, a current ILCDET is
sourced out of the SRC pin for the time tLCDET to check if
there is an external leakage current on that node in the
application. The high-side switch on OUT1 is turned ON only
if the test is successful.
33285
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
D SUFFIX
EF SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42564B
ISSUE U
33285
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
4.0
9/2006
•
•
•
Implemented Revision History page
Converted to Freescale format
Added part number MCZ33285EF (Pb-FREE) to Ordering Information
5.0
2/2007
•
•
Added Peak Package Reflow Temperature During Reflow (1), (2) to Maximum Ratings
Added notes (1) and (2)
33285
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
33285
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
REVISION HISTORY
33285
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33285
Rev. 5.0
2/2007
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