MD1811 High Speed Quad MOSFET Driver Features General Description ► ► ► ► ► ► ► ► ► ► ► The Supertex MD1811 is a high speed, quad MOSFET driver designed to drive high voltage P and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1811 can operate from a 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. 6ns rise and fall time 2 A peak output source/sink current 1.2V to 5V input CMOS compatible 5V to 12V total supply voltage Smart Logic threshold Low jitter design Quad matched channels Drives two P- and two N-channel MOSFETs Outputs can swing below ground Low inductance quad flat no-lead package High-performance thermally-enhanced The output stage of the MD1811 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and –5 volts, and the output L and H levels may be varied anywhere over the range of –5 to +5 volts. The output stage is capable of peak currents of up to ±2 amps, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Applications ► ► ► ► ► ► Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver Clock driver/buffer High speed level translator Typical Application Circuit +100V +10V +10V 1 F 0.22 F ENAB +PLS1 #1 3.3V CMOS Logic Inputs -PLS1 +PLS2 OE 0.47 F VDD 10nF To Piezoelectric Transducer #1 OUTA INA 10nF -100V OUTB INB 1 F Supertex TC6320 OUTC INC +100V 1 F #2 -PLS2 VH OUTD IND GND VSS VL Supertex MD1811 10nF To Piezoelectric Transducer #2 10nF -100V Supertex TC6320 1 F MD1811 Ordering Information Package Options DEVICE 16-Lead QFN 4x4mm body, 1.0mm height (max), 0.65mm pitch MD1811 MD1811K6-G θJA 45°C/W (1oz. 4-layer 3x4inch PCB) -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Product Marking Parameter Value VDD-VSS, Logic supply voltage -0.5V to +13.5V VH, Output high supply voltage VL-0.5V to VDD+0.5V VL, Output low supply voltage VSS-0.5V to VH+0.5V VSS, Low side supply voltage Logic Input levels 1811 YWLL -7V to +0.5V 16-Lead QFN Package VSS-0.5V to VSS+7V Maximum junction temperature Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = “Green” Packaging +125°C Storage temperature -65°C to 150°C Soldering temperature 235°C Package power dissipation 2.2W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. DC Electrical Characteristics (V H Sym. = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C) Parameter Min. Typ. Max. Units Logic supply voltage 4.5 - 13 V -- VSS Low side supply voltage -5.5 - 0 V -- VH Output high supply voltage VSS+2 - VDD V -- VL Output low supply voltage VSS - VDD-2 V -- 0.8 VDD-VSS IDDQ VDD quiescent current - IHQ VH quiescent current - IDD VDD average current - IH VH average current VIH mA 10 µA 8.0 - mA - 26 - mA Input logic voltage high VOE-0.3 - 5.0 V VIL Input logic voltage low 0 - 0.3 V IIH Input logic current high - - 1.0 µA IIL Input logic current low - - 1.0 µA VIH OE Input logic voltage high 1.2 - 5 V VIL OE Input logic voltage low 0 - 0.3 V RIN Input logic impedance to GND 12 20 30 KΩ CIN Logic input capacitance - 5.0 10 pF 2 Conditions No input transitions, OE = 1 One channel on at 5.0Mhz, No load For logic inputs INA, INB, INC, and IND For logic input OE -- MD1811 Outputs (V H = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C) Sym. Parameter Min. Typ. Max. Units Conditions RSINK Output sink resistance - - 12.5 Ω ISINK = 50mA RSOURCE Output source resistance - - 12.5 Ω ISOURCE = 50mA ISINK Peak output sink current - 2.0 - A -- Peak output source current - 2.0 - A -- ISOURCE AC Electrical Characteristics (V H Sym Min Typ Max Units Input or OE rise & fall time - - 10 ns tPLH Propagation delay when output is from low to high - 7.0 - ns tPHL Propagation delay when output is from high to low - 7.0 - ns tPOE Propagation delay OE to output - 9.0 - ns tr Output rise time - 6.0 - ns tf Output fall time - 6.0 - ns l tr - tf l Rise and fall time matching - 1.0 - ns l tPLHtPHL l Propagation low to high and high to low matching - 1.0 - ns ∆tdm Propagation delay matching - ±2.0 - ns tirf Parameter = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C) Conditions Logic input edge speed requirement CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns for each channel Device to device delay match Logic Truth Table Logic Inputs Output OE INA INB OUTA OUTB H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL OE INC IND OUTC OUTD H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL 3 MD1811 VTH vs VOE Timing Diagram and VTH / VOE Curve VTH VOE/2 1.8V IN 2.0 50% 5 0% 1.5 0V t PLH tPHL 12V 90 % 1.0 0.6V 9 0% OUT 0.5 0V 10% 10% 0 tr tf 0 1.0 2.0 3.0 4.0 5.0 VOE Application Information For proper operation of the MD1811, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND to VLL, where VLL is 1.2 to 5.0 volts. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1811 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS, and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. of up to 1.0µF may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor 4 MD1811 Simplified Block Diagram VH VDD MD1811 OE OUTA INA OUTB INB OUTC INC OUTD IND VSS GND Detailed Block Diagram VL V DD OE Level Shifter INA Level Shifter VH OUTA VSS VL VH VDD INB OUTB Level Shifter VSS VL VH VDD INC OUTC Level Shifter V SS VL VH VDD IND Level Shifter OUTD SUB VSS GND 5 VL MD1811 Pin Description Pin # Function 1 INB 5 INC 6 IND 15 INA 2 VL 4 Description Logic input. Input logic high will cause the output to swing to VH. Input logic low will cause the output to swing to VL. Keep all logic inputs low until IC powered up. Supply voltage for N-channel output stage. 3 GND 7 VSS Low side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies and powered-up first. 8 OUTD Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTD will swing to VL turning off the external N-channel MOSFET. 9 OUTC Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTC will swing to VH turning off the external P-channel MOSFET. 12 OUTB Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. 13 OUTA Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. 10 Logic input ground reference. VH Supply voltage for P-channel output stage. 14 VDD High side supply voltage. 16 OE Output enable logic input. When OE is high, (VOE+VGND)/2 sets the threshold transition between logic level high and low. When OE is low, all outputs are at high impedance. Keep OE low until IC powered up. 11 Substrate The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally. 6 MD1811 16-Lead QFN Package Outline (K6) 4x4mm body, 1.00mm height (max), 0.65mm pitch Note 1 (Index Area D/2 x E/2) D2 D 16 16 1 1 e Note 1 (Index Area D/2 x E/2) E E2 b View B Top View Bottom View Note 3 θ L A A3 Seating Plane L1 Note 2 A1 View B Side View Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 0.25 3.85 2.40 3.85 2.40 0.30 4.00 - 4.00 - 0.35 4.15 2.80 4.15 2.80 JEDEC Registration MO-220, Variation VGGC-3, Issue K, June 2006. Drawings not to scale. Doc.# DSFP - MD1811 NR40907 7 e 0.65 BSC L L1 θ 0.30 - 0O 0.40 - - 0.50 0.15 14O