Supertex inc. MD1812 Initial Release High Speed Quad MOSFET Driver Features General Description ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ The Supertex MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.2 to 5.0 volt amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages. 6ns rise and fall time 2A peak output source/sink current 1.2V to 5V input CMOS compatible ±5V to ±12V supply voltage operation Smart Logic threshold Low jitter design Quad matched channels Drives two N and two P-channel MOSFETs Outputs can swing below ground Built-in level translator for negative gate bias User-defined damping for return-to-zero application Low inductance quad flat no-lead package Thermally-enhanced package As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of –5V to +5V. The output stage is capable of peak currents of up to ±2 amps, depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A builtin level shifter provides P-MOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses. Applications ♦ ♦ ♦ ♦ ♦ ♦ Ultrasound PN code transmitter Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation High speed level translator High voltage bipolar pulser Typical Application Circuit +100V +10V +10V 1 F 0.22 F 0.47 F 11 14 3.3V CMOS Logic Inputs 15 INA 1 INB VH VDD 16 OE OUTA 13 OUTB 12 INC 6 IND 10nF OUTG 10 LT 5 10nF 2K GND 3 VL VSS 7 2 OUTC 9 OUTD 8 VNEG 4 -100V Supertex TC6320 1 F 10nF -10V 0.47 F Supertex MD1812 Supertex TC2320 NR031706 Supertex inc. · 1235 Bordeaux Drive, Sunnyvale, CA 94089 · Tel: (408) 222-8888 · FAX: (408) 222-4895 · www.supertex.com 1 MD1812 Package Option Device 16-lead 4x4x0.9 QFN MD1812 MD1812K6-G -G indicates package is RoHS compliant (‘Green’) 16-Lead QFN (K6) Pin Configuration 16-Lead QFN (K6) Package 13 16 1 12 MD1812 4 9 5 8 Top View Pin Description Pin # Function Description 1 INB Logic input. Controls OUTB when OE is high.. 2 VL Supply voltage for N-channel output stage. 3 GND Device ground. 4 VNEG Supply voltage the auxiliary gate drive. 5 INC Logic input. Controls OUTC when OE is high. 6 IND Logic input. Controls OUTD when OE is high. 7 VSS Supply voltage for low-side analog, level shifter, and gate drive circuit. 8 OUTD Output driver. 9 OUTC Output driver. 10 OUTG Auxiliary output driver. 11 VH 12 OUTB Output driver. 13 OUTA Output driver. 14 VDD Supply voltage for high-side analog, level shifter, and gate drive circuit. 15 INA Logic input. Controls OUTA when OE is high. 16 OE Output enable logic input. Supply voltage for P-channel output stage Note: Thermal pad and pin #4, VNEG must be connected externally. NR031706 2 MD1812 Absolute Maximum Ratings Parameter Value VDD-VSS, Logic Supply Voltage -0.5V to +13.5V VH, Output High Supply Voltage VL-0.5V to VDD+0.5V VL, Output Low Supply Voltage VSS-0.5V to VH+0.5V Vss, Low Side Supply Voltage -7V to +0.5V VNEG-VSS, Negative Supply Voltage VSS-13.5V to VSS+0.5V Logic Input Levels VSS-0.5V to VSS+7V Maximum Junction Temperature +125°C Storage Temperature -65°C to 150°C Soldering Temperature 235°C Package Power Dissipation 2.2W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. DC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC) Symbol Parameter Min Typ Max Units Conditions VDD - VSS Logic supply voltage 4.5 - 13 V --- VSS Low side supply voltage -5.5 - 0 V --- VH Output high supply voltage VSS+2 - VDD V --- VL Output low supply voltage VSS - VDD-2 V --- VNEG Negative supply voltage -13 - VSS-2 V May connect to VSS if OUTG not used IDDQ VDD quiescent current - 1.5 - mA IHQ VH quiescent current - - 10 µA INEGQ VNEG quiescent current - - 10 µA IDD VDD average current - 7.0 - mA IH VH average current - 22 - mA INEG VNEG average current - 1.5 - mA VIH Input logic voltage high VOE-0.3 - 5 V VIL Input logic voltage low 0 - 0.3 V IIH Input logic current high - - 1.0 µA IIL Input logic current low - - 1.0 µA VIH OE Input logic voltage high 1.2 - 5 V VIL OE Input logic voltage low 0 - 0.3 V RIN Input logic impedance to GND 12 20 30 KΩ CIN Logic input capacitance - 5 10 pF No input transitions, OE = 1 One channel on at 5.0Mhz, No load For logic inputs INA, INB, INC, and IND For logic input OE --- NR031706 3 MD1812 Outputs (VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC) Symbol Parameter Min Typ Max Units Conditions RSINK Output sink resistance - - 12.5 Ω ISINK = 50mA RSOURCE Output source resistance - - 12.5 Ω ISOURCE = 50mA ISINK Peak output sink current - 2.0 - A --- ISOURCE Peak output source current - 2.0 - A --- AC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VNEG = -12V, VOE = 3.3V, TJ = 25OC) Symbol Parameter tirf Input or OE rise & fall time Min Typ Max Units - - 10 ns - 7 - ns - 7 - ns tPHL Propagation delay when output is from low to high Propagation delay when output is from high to low tPOE Propagation delay OE to output - 9 - ns tPCG Propagation delay INC to OUTG - 28 - ns tr Output rise time - 6 - ns tf Output fall time - 6 - ns Rise and fall time matching - 1.0 - ns Propagation low to high and high to low matching - 1.0 - ns Propagation delay matching - ±2.0 - ns tPLH l tr - tf l l tPLH-tPHL l ∆tdm Conditions Logic input edge speed requirement CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns for each channel Device to device delay match Logic Truth Table Logic Inputs Output OE INA INB OUTA OUTB H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL OE INC IND OUTC OUTG OUTD H L L VH VSS VH H L H VH VSS VL H H L VL VNEG VH H H H VL VNEG VL L X X VH VSS VL NR031706 4 MD1812 Application Information The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0µF may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area, and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will reduce the output voltage slew rate at the terminals of a capacitive load. For proper operation of the MD1812, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB, INC, IND and OE pins should be connected to a logic source with a swing of GND to VCC, where VCC is 1.2 to 5.0 volts. When input logic(s) is high, output(s) will swing to VL, and when input(s) logic is low, output(s) will swing to VH. All inputs must be kept low until the device is powered up. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1812 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane, with short leads and decoupling components to prevent resonance in the power leads. The OE pin sets the threshold level of logic for inputs (VOE + VGND) / 2. When OE is low, OUTA and OUTC are at VH. OUTB and OUTD are at VL. Auxiliary output OUTG, is at VSS, regardless of the inputs INA or INB. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V, even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. Best timing performance is obtained for OUTC when the voltage of (VSSVNEG) = (VH-VL). Output drivers, OUTA and OUTC, drive the gate of an external Pchannel MOSFET, while output drivers OUTB and OUTD drive the gate of an external N-channel MOSFET, and they all swing from VH to VL. The auxiliary output drive, OUTG, swings from VSS to VNEG, and drives the gate of an external P-channel MOSFET via a 2KΩ series resistor. NR031706 5 MD1812 16-Lead QFN Package Outline (K6) Datum A or B -A - D D/2 4 INDEX AREA (D/2 xE/2) l1 -B- 4 E/2 1 e E Chamfer/Radius aaa C 2x Terminal Tip N-1 N 4 5 Symbol aaa C 2x A ccc C 0.08 C SEATING PLANE -C- A3 A1 SIDE VIEW D2 e -B- E2 E2/2 NXl D2/2 1 N N-1 NXb -A- INDEX AREA (D/2 xE/2) 4 SEE DETAIL B Height Dimensions Min TOP VIEW NX e/2 bbb C ddd N om D B SC 4.0 E B SC 4.0 e 0.65 Max D2 2.0 2.15 2.25 E2 2.0 2.15 2.25 b 0.25 0.30 0.35 l 0.45 0.55 0.65 A 0.80 0.90 1.0 A1 0.00 0.02 0.05 A3 --- 0.20 ref --- L1 0.03 --- 0.15 Issue A Tolerance of Form & Position aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 Issue A C A B Bottom ID Dimensions BTM VIEW AA BB CC DD .344 .344 .181 .181 Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5m - 1994. 2. All dimensions are in millimeters, all angles are in degrees (O). 3. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95, SPP-002. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1identifier may be either a mold or marked feature. 4. Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to or greater than 0.33mm. 5. Dimension B applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension B should not be measured in that radius area. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com. ©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895 Doc.# DSFP - MD1812 NR031706 www.supertex.com 6