OKI MD56V62800A

Pr
E2G1054-18-62
el
im
y
4-Bank ¥ 2,097,152-Word ¥ 8-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MD56V62800A is a 4-bank ¥ 2,097,152-word ¥ 8-bit synchronous dynamic RAM, fabricated
in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and
outputs are LVTTL compatible.
FEATURES
•
•
•
•
•
•
•
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
4-bank ¥ 2,097,152-word ¥ 8-bit configuration
3.3 V power supply, ±0.3 V tolerance
Input
: LVTTL compatible
Output : LVTTL compatible
Refresh : 4096 cycles/64 ms
Programmable data transfer mode
– CAS latency (1, 2, 3)
– Burst length (1, 2, 4, 8, full page)
– Data scramble (sequential, interleave)
• Burst read single bit write capability
• CBR auto-refresh, Self-refresh capability
• Package:
54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62800A-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
Max.
Frequency
Access Time (Max.)
tAC2
tAC3
MD56V62800A-8
125 MHz
10 ns
6 ns
MD56V62800A-10
100 MHz
9 ns
9 ns
ar
This version:
Jun. 1998
MD56V62800A
in
¡ Semiconductor
MD56V62800A
¡ Semiconductor
1/28
¡ Semiconductor
MD56V62800A
PIN CONFIGURATION (TOP VIEW)
VCC
DQ1
VCCQ
NC
DQ2
VSSQ
NC
DQ3
VCCQ
NC
DQ4
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
A13/BA0
A12/BA1
A10
A0
A1
A2
A3
VCC
1
54 VSS
2
53 DQ8
3
52 VSSQ
4
51 NC
5
50 DQ7
6
49 VCCQ
7
48 NC
8
47 DQ6
9
46 VSSQ
10
45 NC
11
44 DQ5
12
43 VCCQ
13
42 NC
14
41 VSS
15
40 NC
16
39 DQM
17
38 CLK
18
37 CKE
19
36 NC
20
35 A11
21
34 A9
22
33 A8
23
32 A7
24
31 A6
25
30 A5
26
29 A4
27
28 VSS
54-Pin Plastic TSOP (II)
(K Type)
Pin Name
CLK
Note:
Function
Pin Name
Function
System Clock
DQM
Data Input/Output Mask
CS
Chip Select
DQi
Data Input/Output
CKE
Clock Enable
VCC
Power Supply (3.3 V)
A0 - A11
Address
VSS
Ground (0 V)
A12, A13
Bank Select Address
VCCQ
Data Output Power Supply (3.3 V)
RAS
Row Address Strobe
VSSQ
Data Output Ground (0 V)
CAS
Column Address Strobe
NC
No Connection
WE
Write Enable
The same power supply voltage must be provided to every VCC pin and VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
2/28
¡ Semiconductor
MD56V62800A
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA11
Column address: CA0 – CA8
A12, A13
(BA1, BA0)
Bank Access pins. These pins are dedicated to select one of 4 banks.
RAS
CAS
Functionality depends on the combination. For details, see the function truth table.
WE
DQM
Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal.
DQi
Data inputs/outputs are multiplexed on the same pin.
3/28
¡ Semiconductor
MD56V62800A
BLOCK DIAGRAM
CKE
CS
RAS
CAS
WE
DQM
A0 A13
CLOCK
BUFFER
Row
Address
Latches
& Refresh
Counter
Command
Decoding
Logic
Command
Buffers
Address
Buffers
Row Decoders
Control
Logic
Mode
Register
Word Drivers
Column
Address
Latches
& Counter
Latency
& Burst
controller
Column Decoders
Sense Amplifiers
CLK
Memory
Cells
BANK A
BANK B
BANK C
BANK D
Input
Buffers
Input
Data
Register
Output
Buffers
Output
Data
Register
DQ1 - DQ8
4/28
¡ Semiconductor
MD56V62800A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced to VSS)
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
–0.5 to VCC + 0.5
V
VCC Supply Voltage
VCC, VCCQ
–0.5 to 4.6
V
Storage Temperature
Tstg
–55 to 150
°C
Power Dissipation
PD*
1
W
Short Circuit Current
IOS
50
mA
Operating Temperature
Topr
0 to 70
°C
*: Ta = 25°C
Recommended Operating Conditions
(Voltages referenced to VSS = 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC, VCCQ
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VCC + 2.0
V
Input Low Voltage
VIL
VCC – 2.0
—
0.8
V
Capacitance
(VCC = 3.3 V, Vbias = 1.4 V, Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (CLK)
Input Capacitance (CKE, CS,
RAS, CAS, WE, DQM, A0 - A13)
Input/Output Capacitance
(DQ1 - DQ8)
Symbol
Min.
Max.
Unit
CCLK
2.5
4
pF
CIN
2.5
5
pF
COUT
4
6.5
pF
5/28
¡ Semiconductor
MD56V62800A
DC Characteristics
Condition
Parameter
Symbol
Version
-8
Unit Note
-10
Min. Max.
2.4
—
V
Bank
CKE
Others
Output High Voltage VOH
—
—
IOH = –2 mA
Min.
2.4
Max.
—
Output Low Voltage
VOL
—
—
IOL = 2 mA
—
0.4
—
Input Leakage Current
ILI
—
—
—
–5
5
Output Leakage Current
ILO
—
—
—
–5
5
CKE ≥ VIH
tCC = min
tRC = min
No Burst
—
tCC = min
tRC = min
tRRD = min
No Burst
ICC1
Average Power
Supply Current
(Operating)
One Bank
Active
ICC1D Both Banks
Active
CKE ≥ VIH
Both Banks
Precharge
CKE ≥ VIH
tCC = min
Average Power
ICC3S Both Banks
Active
Supply Current
(Clock Suspension)
CKE £ VIL
tCC = min
Power Supply
Current (Stand by)
ICC2
–5
5
mA
–5
5
mA
125
—
115
mA 1, 2
—
175
—
165
mA 1, 2
—
30
—
30
mA
3
—
6
—
6
mA
2
—
60
—
50
mA
3
CKE ≥ VIH,
CS ≥ VIH
tCC = min
ICC4
Both Banks
Active
CKE ≥ VIH
tCC = min
—
165
—
155
mA 1, 2
ICC5
One Bank
Active
CKE ≥ VIH
tCC = min
tRC = min
—
185
—
185
mA
—
2
—
2
mA
—
2
—
2
mA
ICC3
Power Supply
Current (Burst)
Power Supply
Current
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
Notes:
V
One Bank
Active
Average Power
Supply Current
(Active Stand by)
Average Power
Supply Current
(Power down)
0.4
ICC6
ICC7
Both Banks
Precharge
CKE £ 0.2 V
Both Banks
Precharge
CKE £ VIL
2
tCC = min
tCC = min
1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
6/28
¡ Semiconductor
MD56V62800A
Mode Set Address Keys
CAS Latency
Write Burst Length
Burst Type
Burst Length
Write Burst Length
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT = 0
BT = 1
0
Burst Write
0
0
0
Reserved
0
Sequential
0
0
0
1
1
1
Single Bit Write
0
0
1
1
1
Interleave
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
1
0
1
Reserved
1
0
1
Reserved Reserved
1
1
0
Reserved
1
1
0
Reserved Reserved
1
1
1
Reserved
1
1
1
Full Page Reserved
A9
Notes:
1. A7, A8, A10, A11, A12 and A13 should stay "L" during mode set cycle.
2. When A9 = 1, a burst length for write operation is always 1 regardless of the burst
lengths set by A0, A1 and A2.
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the VCC voltage has reached the specified level, pause for 200 ms or more with
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
7/28
¡ Semiconductor
MD56V62800A
AC Characteristics
Parameter
Note 1, 2
Symbol
CL = 3
MD56V62800A-8
MD56V62800A-10
Unit Note
Min.
Max.
Min.
Max.
8
—
10
—
ns
12
—
15
—
ns
CL = 1
24
—
30
—
ns
CL = 3
Access Time from CL = 2
Clock
CL = 1
—
6
—
9
ns
3, 4
tAC
—
10
—
9
ns
3, 4
—
22
—
27
ns
3, 4
Clock "H" Pulse Time
tCH
3
—
3
—
ns
Clock "L" Pulse Time
tCL
3
—
3
—
ns
Input Setup Time
tSI
2
—
3
—
ns
Input Hold Time
tHI
1
—
1
—
ns
Output Low Impedance
Time from Clock
tOLZ
3
—
3
—
ns
Output High Impedance
Time from Clock
tOHZ
—
8
—
8
ns
Output Hold from Clock
tOH
3
—
3
—
ns
RAS Cycle Time
tRC
80
—
90
—
ns
RAS Precharge Time
tRP
30
—
30
—
ns
RAS Active Time
tRAS
50
100,000
60
100,000
ns
RAS to CAS Delay Time
tRCD
20
—
30
—
ns
Write Recovery Time
tWR
8
—
10
—
ns
RAS to RAS Bank Active
Delay Time
tRRD
16
—
20
—
ns
Refresh Time
tREF
—
64
—
64
ms
Power-down Exit Set-up Time
tPDE
tSI + 1 CLK
—
tSI + 1 CLK
—
ns
—
3
—
Clock Cycles Time CL = 2
tCC
3
3
ns
Input Level Transition Time
tT
CAS to CAS Delay Time (Min.)
lCCD
1
1
Cycle
Clock Disable Time from CKE
lCKE
1
1
Cycle
Data Output High Impedance
Time from DQM
lDOZ
2
2
Cycle
Data Input Mask Time from
DQM
lDOD
0
0
Cycle
Data Input Time from Write
Command
lDWD
0
0
Cycle
CL = 3
Data Output High
Impedance Time from CL = 2
Precharge Command CL = 1
3
3
Cycle
lROH
2
2
Cycle
1
1
Cycle
Active Command Input Time from Mode
Register Set Command Input (Min.)
lMRD
3
3
Cycle
Write Command Input Time
from Output
lOWD
2
2
Cycle
8/28
¡ Semiconductor
MD56V62800A
Notes : 1. AC measurements assume that tT = 1 ns.
2. The reference level for timing of input signals is 1.4 V.
3. Output load.
1.4 V
Z = 50 W
50 W
Output
50 pF
4. The access time is defined at 1.4 V.
5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and
VIL.
9/28
,
,
,,
,
¡ Semiconductor
MD56V62800A
TIMING WAVEFORM
Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRC
CKE
CS
tRP
RAS
tRCD
CAS
ADDR
Ra
Ca0
Rb
Cb0
A13
A12
A10
Ra
Rb
tOH
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
tOHZ
tAC
Db2
Db3
tWR
WE
DQM
Row Active
Read Command
Row Active
Write Command
Precharge Command
Precharge Command
10/28
¡ Semiconductor
MD56V62800A
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
,
,,
,,
tCC
tCL
High
CKE
CS
tSI
tHI
RAS
lCCD
tHI
tSI
CAS
tSI
ADDR
tSI
tSI
Ra
Ca
Cb
tHI
Cc
tHI
A13
A12
A10
Ra
tAC
DQ
Qa
tHI
Db
tOLZ
Qc
tSI
tOH
tOHZ
lOWD
tHI
WE
tSI
DQM
Row Active
Write Command
Read Command
Precharge Command
Read Command
11/28
¡ Semiconductor
*Notes:
MD56V62800A
1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM are
invalid.
2. When issuing an active, read or write command, the bank is selected by A12 and A13.
A12
A13
Active, read or write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A10
A12
A13
0
0
0
After the end of burst, bank A holds the idle status.
Operation
1
0
0
After the end of burst, bank A is precharged automatically.
0
0
1
After the end of burst, bank B holds the idle status.
1
0
1
After the end of burst, bank B is precharged automatically.
0
1
0
After the end of burst, bank C holds the idle status.
1
1
0
After the end of burst, bank C is precharged automatically.
0
1
1
After the end of burst, bank D holds the idle status.
1
1
1
After the end of burst, bank D is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A10, A12 and A13
inputs.
A10
A12
A13
0
0
0
Bank A is precharged.
0
0
1
Bank B is precharged.
Operation
0
1
0
Bank C is precharged.
0
1
1
Bank D is precharged.
1
X
X
All banks are precharged.
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM entry.
12/28
¡ Semiconductor
MD56V62800A
,,
,
,
,,
,
,
,
,
,
,,
Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
Bank A Active
RAS
CAS
lCCD
ADDR
Ca0
Cb0
Cc0
Cd0
A13
A12
A10
DQ
Qa0
Qa1
Qb0 Qb1
Dc0
Dc1
lOWD
Dd0
tWR *Note2
WE
*Note1
DQM
Read Command
Read Command
Write Command
Write Command
Precharge Command
*Notes:
1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command
to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
13/28
,
,,,,
,,
¡ Semiconductor
MD56V62800A
Read & Write Cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
tRRD
CAS
ADDR
RAa
RDb CAa
RAa
RDb
CDb
A13
A12
A10
WE
CAS Latency = 2
DQ
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
A-Bank Precharge Start
DQM
CAS Latency = 3
DQ
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
A-Bank Precharge Start
tWR
DQM
Row Active
(A-Bank)
A Bank Read with
Auto Precharge
Row Active
(D-Bank)
D Bank Write with
Auto Precharge
D Bank Precharge
Start Point
14/28
,
,
,
,
,
,
,
¡ Semiconductor
MD56V62800A
Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4
0
CLK
CKE
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
High
tRC
RAS
CAS
ADDR
A13
A12
A10
DQ
WE
DQM
tRRD
RAa
CAa
RAa
RCb
CCb
RCb
Read Command
(A-Bank)
CAc
RAc
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
RAc
QCb0 QCb1 QCb2 QCb3
Read Command
(C-Bank)
Row Active
(C-Bank)
Precharge Command
(A-Bank)
QAc0 QAc1 QAc2 QAc3
Read Command
(A-Bank)
Precharge Command
(C-Bank)
Row Active
(A-Bank)
15/28
¡ Semiconductor
MD56V62800A
Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4
,
,,,,
,
,,,
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
A13
A12
A10
RAa
DQ
RBb
RAc
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write Command
(A-Bank)
Precharge
Command
(A-Bank)
Write Command
(B-Bank)
Write Command
(A-Bank)
Row Active
(A-Bank)
Precharge Command
(A-Bank)
Precharge Command
(B-Bank)
16/28
,,,,
,
,
¡ Semiconductor
MD56V62800A
Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
*Note1
CS
RAS
CAS
ADDR
RAa
CAa
RCb
CCb
CAc
CCd
CAe
A13
A12
A10
RAa
RCa
DQ
QAa0 QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3 QAc0 QAc1 QCd0 QCd1 QAe0 QAe1
lROH
WE
DQM
Row Active
(A-Bank)
Row Active
(C-Bank)
Read Command
(A-Bank)
*Note:
Read Command
(C-Bank)
Read Command
(C-Bank)
Read Command
(A-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
1. CS is ignored when RAS, CAS and WE are high at the same cycle.
17/28
,
,,
,
,
,
,,
,,
¡ Semiconductor
MD56V62800A
Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
ADDR
RBa
CBa
RDb
CDb
CBc
CDd
A13
A12
A10
RBa
DQ
RDb
DBa0 DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1 DDd0
WE
DQM
Row Active
(B-Bank)
Row Active
(D-Bank)
Write Command
(B-Bank)
Write Command
(D-Bank)
Write Command
(D-Bank)
Write Command
(B-Bank)
Precharge Command
(All Banks)
18/28
¡ Semiconductor
MD56V62800A
,
,
,
,
,
Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RCb
CCb
RAc
CAc
A13
A12
A10
RAa
RCb
DQ
QAa0 QAa1 QAa2 QAa3
RAc
DCb0 DCb1 DCb2 DCb3
QAc0 QAc1 QAc2 QAc3
WE
DQM
Row Active
(A-Bank)
Row Active
(C-Bank)
Read Command
(A-Bank)
Precharge Command
(A-Bank)
Write Command
(C-Bank)
Read Command
(A-Bank)
Row Active
(A-Bank)
19/28
¡ Semiconductor
MD56V62800A
Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
CS
RAS
CAS
ADDR
A13
A12
A10
DQ
WE
DQM
,,,
,,,
,
High
CAa0
CDb0
QAa0 QAa1 QAa2 QAa3
Read Command
(A-Bank)
CAc0
DDb0 DDb1 DDb2 DDb3
Write Command
(D-Bank)
QAc0 QAc1 QAc2 QAc3
Read Command
(A-Bank)
20/28
¡ Semiconductor
MD56V62800A
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
CKE
CS
RAS
CAS
ADDR
A13
A12
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
¨
,
,
,
,
,
,
,
,
,
,
,
Ra
¨
CLK
*Note1
*Note1
Ca
Cb
Cc
Ra
*Note2
DQ
Qa0
Qa1
Qa2
Qb0
Qb1
tOHZ
WE
DQM
Row Active
Read
Command
*Notes:
CLOCK
Suspension
Read DQM
Read
Command
Dc0
tOHZ
Read DQM
Dc2
*Note3
Write
DQM
Write
Command
CLOCK
Suspension
Write
DQM
1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When DQM is asserted, the read data after two clock cycles is masked.
3. When DQM is asserted, the write data in the same clock cycle is masked.
21/28
¡ Semiconductor
MD56V62800A
Read Interruption by Precharge Command @ Burst Length = 8
,
,
,
,,,
,,
,
,,
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
ADDR
Ra
Ca
A13
A12
A10
Ra
WE
CAS Latency = 2
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
IROH
DQM
CAS Latency = 3
DQ
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
IROH
DQM
Row Active
Read Command
Precharge Command
22/28
,
,
,
,
,
¡ Semiconductor
MD56V62800A
Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tSI
*Note1
tPDE *Note2
tSI
tSI
CKE
CS
RAS
CAS
Ra
ADDR
Ca
A13
A12
Ra
A10
DQ
Qa0
Qa1
Qa2
WE
DQM
Row Active
Power-down
Entry
*Notes:
Power-down
Exit
Clock
Suspention
Entry
Clock
Suspention
Exit
Read
Command
Precharge
Command
1. When all banks are in precharge state, and if CKE is set low, then the MD56V62800A enters power-down
mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, CKE has to be set high for tPDE (tSI + 1 CLK) or more.
23/28
,
,,,,
,,
,
¡ Semiconductor
MD56V62800A
Self Refresh Cycle
0
CLK
1
2
tRC
CKE
tSI
CS
RAS
CAS
ADDR
A13
A12
A10
DQ
WE
DQM
Ra
BS
BS
Ra
Hi - Z
Self
Refresh
Entry
Hi - Z
Self
Refresh
Exit
Row
Active
24/28
¡ Semiconductor
MD56V62800A
Auto Refresh Cycle
Mode Register Set Cycle
0
CLK
CKE
CS
1
2
3
4
5
6
0
1
2
3
CAS
ADDR
DQ
WE
DQM
5
6
7
8
9
10
11
12
,,
,,,
,
High
High
tRC
lMRD
RAS
4
key
Ra
Hi - Z
MRS
New Command
Hi - Z
Auto Refresh
Auto Refresh
25/28
¡ Semiconductor
MD56V62800A
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current State1 CS RAS CAS WE BA
Idle
Row Active
Read
Write
Action
ADDR
X
NOP
X
X
NOP
BA
X
ILLEGAL 2
CA
ILLEGAL 2
BA
RA
Row Active
BA
A10
NOP 4
H
X
X
L
L
OP Code
H
X
X
X
X
L
H
H
H
L
H
H
L
L
H
L
X
BA
L
L
H
H
L
L
H
L
L
L
L
L
L
L
Auto-Refresh or Self-Refresh 5
Mode Register Write
H
X
X
X
X
X
NOP
L
H
H
X
X
X
NOP
L
H
L
H
BA
CA, A10
Read
L
H
L
L
BA
CA, A10
Write
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
Precharge
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Row Active after Burst ends)
L
H
H
H
X
X
NOP (Continue Row Active after Burst ends)
L
H
H
L
BA
X
Term Burst
L
H
L
H
BA
CA, A10
Term Burst, start new Burst Read
L
H
L
L
BA
CA, A10
Term Burst, start new Burst Write
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
Term Burst, execute Row Precharge
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP (Continue Row Active after Burst ends)
L
H
H
H
X
X
NOP (Continue Row Active after Burst ends)
L
H
H
L
BA
X
Term Burst
L
H
L
H
BA
CA, A10
Term Burst, start new Burst Read
L
H
L
L
BA
CA, A10
Term Burst, start new Burst Write
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
Term Burst, execute Row Precharge
L
L
L
X
X
X
ILLEGAL
Read with
H
X
X
X
X
X
NOP (Continue Burst to End and enter Row Precharge)
Auto Precharge
L
H
H
H
X
X
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
L
BA
X
ILLEGAL 2
L
H
L
H
BA
CA, A10
ILLEGAL 2
L
H
L
L
X
X
L
L
H
X
BA
RA, A10
L
L
L
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL 2
Write with
H
X
X
X
X
X
NOP (Continue Burst to End and enter Row Precharge)
Auto Precharge
L
H
H
H
X
X
NOP (Continue Burst to End and enter Row Precharge)
L
H
H
L
BA
X
ILLEGAL 2
L
H
L
H
BA
CA, A10
ILLEGAL 2
L
H
L
L
X
X
L
L
H
X
BA
RA, A10
L
L
L
X
X
X
ILLEGAL
ILLEGAL 2
ILLEGAL
26/28
¡ Semiconductor
MD56V62800A
FUNCTION TRUTH TABLE (Table 1) (2/2)
Current State1 CS RAS CAS WE BA
Precharge
Write Recovery
Row Active
Refresh
Action
ADDR
H
X
X
X
X
X
NOP --> Idle after tRP
L
H
H
H
X
X
NOP --> Idle after tRP
L
H
H
L
BA
X
ILLEGAL 2
L
H
L
X
BA
CA
ILLEGAL 2
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
NOP 4
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
BA
X
ILLEGAL 2
L
H
L
X
BA
CA
ILLEGAL 2
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
ILLEGAL 2
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Row Active after tRCD
L
H
H
H
X
X
NOP --> Row Active after tRCD
L
H
H
L
BA
X
ILLEGAL 2
L
H
L
X
BA
CA
ILLEGAL 2
L
L
H
H
BA
RA
ILLEGAL 2
L
L
H
L
BA
A10
ILLEGAL 2
L
L
L
X
X
X
ILLEGAL
H
X
X
X
X
X
NOP --> Idle after tRC
L
H
H
X
X
X
NOP --> Idle after tRC
L
H
L
X
X
X
ILLEGAL
L
L
H
X
X
X
ILLEGAL
L
L
L
X
X
X
ILLEGAL
Mode Register
H
X
X
X
X
X
NOP
Access
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
L
H
L
X
X
X
ILLEGAL
L
L
X
X
X
X
ILLEGAL
ABBREVIATIONS
RA = Row Address
CA = Column Address
Notes:
BA = Bank Address
AP = Auto Precharge
NOP = No OPeration command
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. Satisfy the timing of lCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
27/28
¡ Semiconductor
MD56V62800A
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State (n) CKEn-1
Self Refresh
Power Down
CKEn
CS RAS CAS WE
H
X
X
X
X
L
H
H
X
L
H
L
H
L
H
L
H
H
L
H
L
H
L
L
H
L
L
X
L
L
X
X
X
ADDR
Action
X
X
INVALID
X
X
X
Exit Self Refresh --> ABI
H
H
X
Exit Self Refresh --> ABI
L
X
ILLEGAL
X
X
ILLEGAL
X
X
ILLEGAL
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Power Down --> ABI
L
H
L
H
H
H
X
Exit Power Down --> ABI
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL 6
L
L
X
X
X
X
X
NOP (Continue power down mode)
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
L
X
ILLEGAL
H
L
L
L
L
H
X
Enter Self Refresh
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
Any State Other
H
H
X
X
X
X
X
Refer to Operations in Table 1
than Listed Above
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Enable Clock of Next Cycle
L
L
X
X
X
X
X
Continue Clock Suspension
All Banks Idle
6
(ABI)
Note:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
28/28