OKI MD5764802 18mb (2m x 9) & 64mb (8m x 8) concurrent rdram Datasheet

E2G1059-39-21
This version: Feb. 1999
MSM5718C50/MD5764802
Previous version: Nov. 1998
¡ Semiconductor
MSM5718C50/MD5764802
¡ Semiconductor
18Mb (2M ¥ 9) & 64Mb (8M ¥ 8) Concurrent RDRAM
DESCRIPTION
The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed
CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited
lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL)
technology permits 600 MHz transfer rates while using conventional system and board design
methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers
as high speed caches, and by using random access mode (page mode) to facilitate large block
transfers. Concurrent (simultaneous) bank operations permit high effective bandwidth using
interleaved transactions.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range
of applications including PC and consumer main memory, graphics, video, and any other
application where high-performance at low cost is required.
FEATURES
• Compatible with Base RDRAMs
• 600 MB/s peak transfer rate per RDRAM
• Rambus Signaling Level (RSL) interface
• Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers
• 480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM
• 13 active signals require just 32 total pins on the controller interface (including power)
• 3.3 V operation
• Additional/multiple Rambus Channels each provide an additional 600 MB/s bandwidth
• Two or four 2KByte sense amplifiers may be operated as caches for low latency access
• Random access mode enables any burst order at full bandwidth within a page
• Graphics features include write-per-bit and mask-per-bit operations
• Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)
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¡ Semiconductor
MSM5718C50/MD5764802
PART NUMBERS
The 18- and 64-Megabit RDRAMs are available in horizontal surface mount plastic package (SHP),
with 533 and 600 MHz clock rate. The part numbers for the various options are shown in Table 1.
Table 1 Part Numbers by Option
Options
533 MHz
600 MHz
18-Megabit SHP
MSM5718C50-53GS-K
MSM5718C50-60GS-K
64-Megabit SHP
MD5764802-53MC
MD5764802-60MC
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¡ Semiconductor
MSM5718C50/MD5764802
RDRAM PACKAGES AND PINOUTS
RDRAMs are available in horizontal surface mount plastic package (SHP).
The package has 32 signal pins and four mechanical pins that provide support for the device. The
mechanical pins are located on the opposite side from the signal leads in the SHP.
VDD
GND
DQ8
GND
DQ7
NC (18M) ; VREF (64M)
ADDRESS
VDD
DQ6
GND
DQ5
VDDA
RXCLK
GNDA
TXCLK
VDD
DQ4
GND
COMMAND
SIN
VREF
SOUT
DQ3
GND
DQ2
(NC)
DQ1
GND
DQ0
(NC)
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Fig. 1 SHP Pin Numbering
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¡ Semiconductor
MSM5718C50/MD5764802
Table 2 Pin Descriptions
Signal
DQ8..DQ0
(BUSDATA [8:0])
I/O
I/O
Description
Signal lines for REQ, DIN, and DOUT packets. The REQ packet contains the
address field, command field, and other control fields. These are RSL
signals.a
CLK
(RXCLK)
I
Receive clock. All input packets are aligned to this clock. This is an RSL
signal.a
CLK
(TXCLK)
I
Transmit clock. DOUT packets are aligned with this clock. This is an RSL
signal.a
VREF
I
Logic threshold reference voltage for RSL signals.
COMMAND
(BUSCTRL)
I
Signal line for REQ, RSTRB, RTERM, WSTRB, WTERM, RESET, and CKE
packets. This is an RSL signal.a
ADDRESS
(BUSENABLE)
I
Signal line for COL packets with column addresses. This is an RSL signal.a
VDD, VDDA
—
+3.3 V power supply. VDDA is a separate analog supply for clock generation
in the RDRAM.
GND, GNDA
—
Circuit ground. GNDA is a separate analog ground for clock generation in
the RDRAM.
SIN
I
Initialization daisy chain input. CMOS levels.
SOUT
O
Initialization daisy chain output. CMOS levels.
a. RSL stands for Rambus Signaling Levels, a low-voltage-swing, active-low signaling technology.
Mechanical
Support Pins
Pin 1
Mechanical
Support Pins
Pin 32
Fig. 2 SHP Package
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MSM5718C50/MD5764802
GENERAL DESCRIPTION
Figure 3 is a block diagram of an RDRAM. At the bottom is a standard DRAM core organized as two
or four independent banks, with each bank organized as 512 or 1024 rows, and with each row
consisting of 2KBytes of memory cells. One row of a bank may be “activated” at any time (ACTV
command) and placed in the 2KByte “page” for the bank. Column accesses (READ and WRITE
commands) may be made to this active page.
The smallest block of memory that may be accessed with READ and WRITE commands is an octbyte
(eight bytes). Bitmask and bytemask options are available with the WRITE command to allow finer
write granularity. There are six control registers that are accessed at initialization time to configure
the RDRAM for a particular application.
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¡ Semiconductor
MSM5718C50/MD5764802
SIN
SOUT RXCLK ADDRESS COMMAND
(BUSENABLE) (BUSCTRL)
1
1
1
DQ8, DQ7,...DQ0
(BUSDATA[8:0])
1 1
TXCLK
9
1
Initialize/Powerdown
1
1 1
9
9
1:8 Demux
8:1 Mux
DIN
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DOUT
DEVICETYPE Register
REQ
RSTRB, RTERM
DEVICEID Register
WSTRB, WTERM
MODE Register
88 CKE, RESET
REFROW Register
RASINTERVAL Register
DEVICEMFGR Register
64/72
d64/72:
64b for 64M
72b for 18M
64/72 ¥ 256 Page
64/72 ¥ 256
64/72
64/72d
64/72 ¥ 256 Page
64/72d
64/72 ¥ 256a Page
c
64/72 ¥ 256 ¥ 1024
Bank 2c
64/72d
64/72 ¥ 256a Page
64/72 ¥ 256a
64/72 ¥ 256
64/72 ¥ 256a ¥ 512b
Bank 1
64/72 ¥ 256 ¥ 1024
Bank 3c
64/72d
MASK Register
Control Logic
64/72d
1
a
64/72 ¥ 256a
64/72 ¥ 256a ¥ 512b
Bank 0
256 octbytes per row for 18M
b
512 rows per bank for 18M
4 banks per RDRAM for 64M
64/72 ¥ 256a ¥ 512b
Bank 1
a
64/72 ¥ 256a ¥ 512b
Bank 0
256 octbytes per row for 64M
1024 rows per bank for 64M
b
Fig. 3 18/64-Mbit Concurrent RDRAM Block Diagram
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MSM5718C50/MD5764802
BASIC OPERATION
Figure 4 (a) shows an example of a read transaction. A transaction begins in interval T0 with the
transfer of a REQ packet. The REQ packet contains the command (ACTV/READ), a device, bank,
and row address (BNK/ROW) of the page to be activated, and the column address (COLa) of the first
octbyte to be read from the page.
The selected bank performs the activation of the selected row during T1 and T2 (the tRCD interval).
Next, the selected bank reads the selected octbyte during T3 and T4 (the tCAC interval). A second
command RSTRB (read strobe) is transferred during T3 and causes the first octbyte (DOUTa) to be
transferred during T5.
T0
T1
T2
T3
T4
T5
COL b
COL c
COL d
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
ACTV
/READ
REQ
Packet
BNK/ROW
/COL a
RSTRB
RTERM
Next
REQ
DOUT a DOUT b DOUT c DOUT d
Bank Operation
tRCD
tCAC
(a) BANK ACTIVATE AND RANDOM READ CYCLES WITHIN A PAGE
T0
T1
T2
T3
T4
COL b
COL c
COL d
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
ACTV
/WRITE
REQ
Packet
BNK/ROW
/COL a
WSTRB
WTERM
Next
REQ
DIN a
DIN b
DIN c
DIN d
tRCD
(b) BANK ACTIVATE AND RANDOM WRITE CYCLES WITHIN A PAGE
Fig. 4 Read and Write Transaction Examples
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¡ Semiconductor
MSM5718C50/MD5764802
In this example, three additional octbytes are read from the activated page. These column addresses
(COLb, COLc, and COLd) are transferred in T3, T4, and T5, respectively. The data octbytes (DOUTb,
DOUTc, and DOUTd) are transferred in T6, T7, and T8, The end of the data octbytes is signaled by
a third command RTERM (read terminate) in T6. The next REQ packet may be sent in T9, or in any
interval thereafter.
Figure 4 (b) shows an example of a write transaction. The transaction begins in interval T0 with the
transfer of a REQ packet. The REQ packet contains, the command (ACTV/WRITE), a device, bank,
and row address (BNK/ROW) of the page to be activated, and the column address (COLa) of the first
octbyte to be written to the page.
The selected bank performs the activation of the selected row during T1 and T2 (the tRCD interval).
A second command WSTRB (write strobe) is transferred during T2 and causes the first octbyte
(DINa) to be transferred during T3.
In this example, three additional octbytes are written to the activated page. These column addresses
(COLb, COLc, and COLd) are transferred in T2, T3, and T4 respectively. The data octbytes (DINb,
DINc, and DINd) are transferred in T4, T5, and T6. The end of the data octbytes is signaled by a third
command WTERM (write termination) in T6. The next REQ packet may be sent in T7, or in any
interval thereafter.
INTERLEAVED TRANSACTIONS
The previous examples showed noninterleaved transactions - the next REQ packet was transferred
after the last data octbyte of the current transaction. In an interleaved transaction, the next REQ packet
is transferred before the first data octbyte of the current transaction. This permits the row and column
access intervals of the next transaction to overlap the data transfer of the current transaction.
Figure 5 shows an example of interleaved read transactions. The first transaction proceeds exactly
as the noninterleaved example of Figure 4 (a) (all packets of the first transaction are labeled with “1”).
However, in T5 the REQ packet for the second transaction is transferred (all packets of the second
transaction are labeled with “2”). The tRCD2 and tCAC2 intervals overlap the transfer of DOUT1 data
octbytes and thus increase the effective bandwidth of the RDRAM since there are no unused
intervals.
A transaction consists of an address transfer phase and a data transfer phase. The REQ packet
performs address transfer, and the remaining packets perform data transfer (DOUT, COL, RSTRB,
and RTERM in the case of a read transaction). The time interval between the address and data transfer
phases of the current transaction may be adjusted to match the data length of the previous transaction
(as long as the row and column access times for the current transaction are observed). Thus, there are
no limits on the types of memory transaction which may be interleaved; any mixing of transaction
length and command type is permitted.
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¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
COL c0 COL d0
COL b1 COL c1 COL d1
COL b2 COL c2
ACTV
RTERM1
RSTRB1 ACTV
RTERM2
RSTRB2 ACTV
/READ
/READ
/READ
REQ
REQ
REQ
Packet 1
Packet 2
Packet 3
BNK/ROW DOUT a0 DOUT b0 DOUT c0 DOUT d0 BNK/ROW DOUT a1 DOUT b1 DOUT c1 DOUT d1 BNK/ROW
/COL a1
/COL a2
/COL a3
tRCD1
tCAC1
Data Transport 0 Overlaps Row/Column Access 1
tRCD2
tCAC2
Data Transport 1 Overlaps Row/Column Access 2
Fig. 5 Interleaved Read Transaction Example
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¡ Semiconductor
MSM5718C50/MD5764802
REQ PACKET (ADDRESS TRANSFER)
An REQ packet initiates a transaction by transferring the address and command information to the
RDRAM. Figure 6 shows the format of the REQ packet. Note that each RDRAM wire carries eight
bits of information in each tPACKET. This is the time required to transfer an octbyte of data and is the
natural granularity with which to illustrate timing relationships. The clock that is actually used by
the RDRAM has a period of tCYCLE, with information transferred on each clock edge. tPACKET is four
times tCYCLE.
In the REQ packet, the bits which are gray are reserved, and should be driven with a zero. In
particular, the bits in tCYCLE t6 and t7 are needed for bus-turn-around during read transactions.
A35..A3: The address field A35..A3 consumes the greatest number of bits. These are allocated to
device, bank, row, and column addressing according to Table 3:
Table 3 A35..A3 Address Fields
Field
18M
64M
COL
A10..A3
A10..A3
ROW
A19..A11
A20..A11
BNK
A20
A22, A21
DEV
A35..A21
A35..A23
OP5..OP0: The command field OP5..OP0 specifies the type of transaction that is to be performed,
according to Table 4. The OP0 bit selects a read or write transaction, the OP1 bit selects a memory or
register space access, and OP5..OP2 select command options. These command options include B in
OP2 (see byte masking on page 22). D in OP3 for selecting broadcast operations (see refresh on page
35), and b1, b0 in OP5, OP4 (see bit masking on page 23).
ACTV: This bit specifies activation or precharge/activation of a bank at the beginning of a
transaction, and is designated by prepending “ACTV/” or “PRE/ACTV/” to the command.
AUTO: This bit specifies auto-precharge of a bank at the end of the transaction, and is designated
by appending “A” to the command.
START: This bit is always set to a one and indicates the beginning of a request to the RDRAM.
REGSEL: This bit is used for accessing registers.
PEND2...PEND0: This field is set to “000” for noninterleaved transactions, and to a nonzero value
for interleaved transactions. This is the number of previous STRB and TERM packets the RDRAM
is to skip. Refer to the Concurrent RDRAM Design Guide for further details.
M7..M0: This field is used to perform byte masking of the first data octbyte DINa for all memory write
transactions (OP1, OP0 = 01). Refer to byte masking on page 22.
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¡ Semiconductor
MSM5718C50/MD5764802
Table 4 Command Encoding
ACTV AUTO OP5 OP4 OP3 OP2 OP1 OP0
0
0
0
0
0
X
0
Command
Description
0
READ
Read
0
0
b1
b0
D
B
0
1
WRITE
Write (b1, b0, B masking and D broadcast options)
0
0
0
0
0
1
1
0
RREG
Register Read
0
0
0
0
D
1
1
1
WREG
Register Write (D)
0
1
0
0
0
X
0
0
READA
Read/AutoPrecharge
0
1
b1
b0
D
B
0
1
WRITEA
Write/AutoPrecharge (b1, b0, D, B)
1
0
0
0
0
X
0
0
ACTV/READ
Activate/Read
1
0
b1
b0
D
B
0
1
ACTV/WRITE
Activate/Write (b1, b0, D, B)
1
1
0
0
0
X
0
0
ACTV/READA
Activate/Read/AutoPrecharge
1
1
b1
b0
D
B
0
1
ACTV/WRITEA
Activate/Write/AutoPrecharge (b1, b0, D, B)
1
0
0
0
0
X
0
0
PRE/ACTV/READ
Precharge/Activate/Read
1
0
b1
b0
D
B
0
1
PRE/ACTV/WRITE
Precharge/Activate/Write (b1, b0, D, B)
1
1
0
0
0
X
0
0
PRE/ACTV/READA
Precharge/Activate/Read/AutoPrecharge
1
1
b1
b0
D
B
0
1
PRE/ACTV/WRITEA
Precharge/Activate/Write/AutoPrecharge (b1, b0, D, B)
11/45
¡ Semiconductor
MSM5718C50/MD5764802
tPACKET
T0
T1
T2
T3
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
ACTV
/READ
REQ
Packet
BNK/ROW
/COL a
DQ8,..DQ0
(BUSDATA[8:0])
tPACKET = 4 • tCYCLE
T0
tCYCLE
t0
t1
t2
t3
t4
t5
START
OP1
OP5
OP2
OP4
DQ8
OP0
OP3
A26
A35
DQ7
A9
A17
A25
A34
M7
DQ6
A8
A16
A24
A33
M6
DQ5
A7
A15
A23
A32
M5
DQ4
A6
A14
A22
A31
ACTV
M4
DQ3
A5
A13
A21
A30
AUTO
M3
DQ2
A4
A12
A20
A29
PEND2
M2
DQ1
A3
A11
A19
A28
PEND1
M1
DQ0
REGSEL
A10
A18
A27
PEND0
M0
t6
t7
CLK
ADDRESS
COMMAND
Fig. 6 REQ Packet Format
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¡ Semiconductor
MSM5718C50/MD5764802
DATA TRANSFER PACKETS
The next set of packet types are used for data transfer. Their formats are summarized in Figure 7.
As in the REQ packet, eight bits are transferred on each wire during each tPACKET interval. The rising
and falling edges of the RDRAM clock define the transfer windows for each of these bits. The data
transfer packets will align to the tPACKET intervals defined by the START bit of the REQ packet by
simply observing the timing rules that are developed in the next few sections of this document.
DIN and DOUT Packets
There are nine wires allocated for the data bytes. These wires are labeled DQ8..DQ0. The eight bytes
transferred in a DIN or DOUT packet have 72 bits, which are labeled D0..D63 (on the DQ0..DQ7
wires) and E0..E7 (on the DQ8 wire). The 18Mbit RDRAM have storage cells for the E0..E7 bits. The
E0..E7 bits are also used with byte masking operations. This is described in the section on byte
masking on page 22.
COL Packet
The column address A10..A3 of the first octbyte of data (DINa or DOUTa) is provided in the REQ
packet. The COL packet contains an eight bit field A10..A3, which provides the column address for
the second and subsequent data octbytes. The COL packets have a fixed timing relationship with
respect to the DIN and DOUT packets to which they correspond. As the DIN and DOUT packets are
moved (to accommodate interleaving ), the COL packets move with them.
RSTRB and RTERM Packets
The RSTRB and RTERM packets indicate the beginning and end of the DOUT packets that are
transferred during a read transaction. The RSTRB and RTERM packets are each eight bits and consist
of a single “1” in an odd tCYCLE position, with the other seven positions “0”. Note that when a
transaction transfers a single data octbyte, the RSTRB and RTERM packets will overlay one another.
This is permitted and is in fact the reason that each packet consists of a single asserted bit. An example
of this case is shown in Figure 14 (a). There will be transaction situations in which the RTERM
overlays a RSTRB packet (two octbyte interleaved transaction). Again, this is permitted. The general
rule is that the RTERM may overlay any of the other packets on the Command (BUSCTRL) wire, and
RSTRB may overlay any other except for a REQ packet.
WSTRB and WTERM Packets
The WSTRB and WTERM packets indicate the beginning and end of the series of DIN packets that
are transferred during a write transaction. The WSTRB and WTERM packets are each eight bits and
consist of a single “1” in an odd tCYCLE position, with the other seven positions “0”. Note that when
a transaction transfers a single data octbyte, the WSTRB and WTERM packets will not overlay one
another (unlike the case of a one octbyte read). An example of this case is shown in Figure 14 (b). There
will be transaction situations in which the WSTRB overlays a REQ packet (no bank activate). Again,
this is permitted. An example of this is shown in Figure 9 (a). The general rule is that the WSTRB may
overlay any of the other packets on the Command (BUSCTRL) wire, and WTERM may overlay any
other except for a REQ packet.
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¡ Semiconductor
MSM5718C50/MD5764802
CKE PACKET
The average power of the RDRAM can be reduced by using Suspend power mode. This is done by
setting the FR field of the MODE register to a zero (the MODE register is shown in Figure 17). A CKE
packet must be sent a time tCKE ahead of each REQ packet (this is shown in interval T0 in Figure 21
(b)). This causes the RDRAM to transition from Suspend to Enable mode. When the RDRAM has
finished the transaction, it returns to Suspend mode. The CKE packet will overlay the RSTRB and
RTERM packets when transactions are interleaved. If the FR field is set to a one, CKE packets are not
used and the RDRAM remains in Enable mode.
RESET PACKET
The RESET packet is used during initialization. When RESET packets are driven for a time tRESET or
greater, the RDRAM will assume a known state. Because the RESET packet is limited to this one use,
it will not interact with the other packet types. This is illustrated in Figure 21 (a).
PWRUP PACKET
The PWRUP packet is used to cause an RDRAM to transition from Powerdown to Enable mode. This
is illustrated in Figure 21 (c).
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MSM5718C50/MD5764802
t0
t1
t2
t3
t4
t5
t6
t7
DQ8
E0
E1
E2
E3
E4
E5
E6
E7
DIN a
DQ7
D7
D15
D23
D31
D39
D47
D55
D63
DIN b
DQ6
D6
D14
D22
D30
D38
D46
D54
D62
DIN c
DQ5
D5
D13
D21
D29
D37
D45
D53
D61
DIN d
DQ4
D4
D12
D20
D28
D36
D44
D52
D60
DQ3
D3
D11
D19
D27
D35
D43
D51
D59
DOUT a
DQ2
D2
D10
D18
D26
D34
D42
D50
D58
DOUT b
DQ1
D1
D9
D17
D25
D33
D41
D49
D57
DOUT c
DQ0
D0
D8
D16
D24
D32
D40
D48
D56
DOUT d
t0
t1
t2
t3
t4
t5
t6
t7
CLK
COL b
CLK
ADDRESS
A3
A4
A5
A6
A7
A8
A9
A10
COL c
COL d
COMMAND
CKE
1
COMMAND
RSTRB
1
COMMAND
RTERM
1
COMMAND
1
COMMAND
WSTRB
WTERM
1
COMMAND
1
1
1
1
1
1
1
1
RESET
COMMAND
1
1
1
1
1
1
1
1
PWRUP
Fig. 7 DIN, DOUT, COL, CKE, RSTRB, RTERM, WSTRB, WTERM, and RESET Packet Formats
15/45
¡ Semiconductor
MSM5718C50/MD5764802
READ TRANSACTIONS
When a controller issues a read request to an RDRAM, one of three transaction cases will occur. This
is a function of the request address and the state of the RDRAM .
READ: The first case is shown in Figure 8 (a). This occurs when the requested bank has been left in
an activated state and the requested row address matches the address of this activated row. This is
also called a page hit read and is invoked by the READ or READA commands.
There are three timing parameters which specify the positioning of the packets which control the data
transfer. These are as follows:
tSDR
tCDR
tTDR
Start of RSTRB to start of DOUT
Start of COL to start of DOUT
Start of RTERM to end of DOUT
These parameters are all expressed in units of tCYCLE, and the minimum and maximum values are
the same; the RSTRB, RTERM, COL, and DOUT packets move together as a block.
A fourth parameter has a minimum value only, and positions the block of data transfer packets
relative to the REQ (address transfer) packet:
tRSR
Start of REQ to start of RSTRB for READ
When a read transaction is formed, these packet constraints must be observed. In addition, there are
constraints upon the timing of the bank operations which must also be observed. These are shown
in Figure 8 (a) next to the label “Bank Operation”. After the transfer of the REQ packet in T0, the
RDRAM performs a column access (requiring tCAC for the column access time) of the first data
octbyte DOUTa during T1 and T2. The RDRAM performs three column cycles (requiring tCC for the
column cycle time) in order to access the next three data octbytes (DOUTb. DOUTc, DOUTd) during
T3, T4 and T5. Each data octbyte is transferred one tPACKET interval after it is accessed.
ACTV/READ: The second case is shown in Figure 8 (b). This occurs when the requested bank has
been left in a precharged state. This is invoked by the ACTV/READ and ACTV/READA commands.
The RSTRB, RTERM, COL, and DOUT packets remain in the same relative positions as in the READ
case, but they move further from the REQ packet:
tASR
Start of REQ to start of RSTRB for ACTV/READ
After the transfer of the REQ packet in T0, the RDRAM performs an activation operation (requiring
tRCD for the row-column delay) during T1 and T2. This leaves the requested row activated. From this
point the sequence of bank operations are identical to the READ case, except that everything has
shifted two tPACKET intervals further from the REQ packet. The sum of tRCD and tCAC is also known
as tRAC (the row access time).
16/45
¡ Semiconductor
MSM5718C50/MD5764802
PRE/ACTV/READ: The third case is shown in Figure 8 (c). This occurs when the requested bank has
been left in an activated state and the requested row address doesn’t match the address of this
activated row. This is also called a page miss read and is invoked by the PRE/ACTV/READ and
PRE/ACTV/READA commands. The RDRAM knows the difference between a PRE/ACTV/
READ and a ACTV/READ because each RDRAM bank has a flag indicating whether it is precharged
or activated. The external controller tracks this flag, and also tracks the address of each activated bank
in order to distinguish READ and PRE/ACTV/READ accesses.
The RSTRB, RTERM, COL, and DOUT packets remain in the same relative positions as in the READ
case, but they move further from the REQ packet:
tPSR
Start of REQ to start of RSTRB for PRE/ACTV/READ
After the transfer of the REQ packet in T0, the RDRAM performs a precharge operation (tRP) during
T1 and T2, and an activation operation (tRCD) during T3 and T4. This leaves the requested row
activated. From this point the sequence of bank operations are identical to the READ case, except that
everything has shifted four tPACKET intervals further from the REQ packet. The sum of tRP, tRCD, and
tCAC is also known as tRC (the row cycle time).
Auto-Precharge Option: For a READ, ACTV/READ, or a PRE/ACTV/READ command, the bank
operations are complete once the last data octbyte has been accessed. The bank will be left with the
requested row activated. For a READA, ACTV/READA, or a PRE/ACTV/READA command,
there is an additional step. During the two tPACKET intervals after the last data octbyte access, an
auto-precharge operation (requiring tRPA for the row precharge, auto) is performed. This leaves the
bank in a precharged state.
T0
T1
T2
T3
COL b
COL c
COL d
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tRSR
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
tCDR
READA RSTRB
REQ
Packet
BNK
/COL a
RTERM
tSDR
tTDR
DOUT a DOUT b DOUT c DOUT d
tCAC
tCC
tCC
tCC
tRPA
(a) READA - RANDOM READ CYCLES WITHIN A PAGE
17/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
T5
COL b
COL c
COL d
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tASR
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
tCDR
ACTV
/READA
REQ
Packet
BNK/ROW
/COL a
Bank Operation
RSTRB
RTERM
tSDR
tTDR
DOUT a DOUT b DOUT c DOUT d
tRCD
tCAC
tCC
tCC
tCC
tRPA
tRAC
(b) ACTV/READA - BANK ACTIVATE AND RANDOM READ CYCLES WITHIN A PAGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COL b COL c COL d
tPSR
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
tCDR
PRE/ACTV
/READA
REQ
Packet
BNK/ROW
/COL a
RSTRB
RTERM
tSDR
tTDR
DOUT a DOUT b DOUT c DOUT d
tRP
tRCD
tCAC
tCC
tCC
tCC
tRPA
tRC
(c) PRE/ACTV/READA - BANK PRECHARGE/ACTIVATE AND RANDOM READ CYCLES IN A PAGE
Fig. 8 Read Transactions
18/45
¡ Semiconductor
MSM5718C50/MD5764802
WRITE TRANSACTIONS
When a controller issues a write request to an RDRAM, one of three transaction cases will occur. This
is a function of the request address and the state of the RDRAM.
WRITE: The first case is shown in Figure 9 (a). This occurs when the requested bank has been left
in an activated state and the requested row address matches the address of this activated row. This
is called a page hit write and is invoked by the WRITE or WRITEA commands.
There are three timing parameters which specify the positioning of the packets which control the data
transfer. These are as follows:
tSDW
tCDW
tTDW
Start of WSTRB to start of DIN
Start of COL to start of DIN
Start of WTERM to end of DIN
These parameters are all expressed in units of tCYCLE, and the minimum and maximum values are
the same; the WSTRB, WTERM, COL, and DIN packets move together as a block.
A fourth parameter has a minimum value only, and positions the block of data transfer packets
relative to the REQ (address transfer) packet:
tWSW
Start of REQ to start of WSTRB for WRITE
When a write transaction is formed, these packet constraints must be observed. In addition, there are
constraints upon the timing of the bank operations which must also be observed. These are shown
in Figure 9 (a) next to the label “Bank Operation”. After the transfer of the REQ packet in T0, the
RDRAM performs a column access (requiring tCAC for the column access time) of the first data
octbyte DINa during T1 and T2, The RDRAM performs three column cycles (requiring tCC for the
column cycle time) in order to access the next three data octbytes (DINb, DINc. DINd) during T3, T4
and T5. Each data octbyte is transferred one tPACKET interval before it is accessed.
ACTV/WRITE: The second case is shown in Figure 9 (b). This occurs when the requested bank has
been left in a precharged state. This is invoked by the ACTV/WRITE and ACTV/WRITEA
commands.
The WSTRB, WTERM, COL, and DIN packets remain in the same relative positions as in the page
hit case, but they move further from the REQ packet:
tASW
Start of REQ to start of WSTRB for ACTV/WRITE
After the transfer of the REQ packet in T0, the RDRAM performs an activation operation (called tRCD
or row-column delay) during T1 and T2. This leaves the requested row activated. From this point the
sequence of bank operations are identical to the WRITE case, except that everything has shifted two
tPACKET intervals further from the REQ packet. The sum of tRCD and tCAC is also known as tRAC (the
row access time).
19/45
¡ Semiconductor
MSM5718C50/MD5764802
PRE/ACTV/WRITE: The third case is shown in Figure 9 (c). This occurs when the requested bank
has been left in an activated state and the requested row address doesn’t match the address of this
activated row. This is also called a page miss write and is invoked by the PRE/ACTV/WRITE and
PRE/ACTV/WRITEA commands. The RDRAM knows the difference between a PRE/ACTV/
WRITE and a ACTV/WRITE because each RDRAM bank has a flag indicating whether it is
precharged or activated. The external controller tracks this flag, and also tracks the address of each
activated bank in order to distinguish PRE/ACTV/WRITE and WRITE accesses.
The WSTRB, WTERM, COL, and DIN packets remain in the same relative positions as in the WRITE
case, but they move further from the REQ packet:
tPSW
Start of REQ to start of WSTRB for PRE/ACTV/WRITE
After the transfer of the REQ packet in T0, the RDRAM performs a precharge operation (tRP) during
T1 and T2, and an activation operation (tRCD) of during T3 and T4. This leaves the requested row
activated. From this point the sequence of bank operations are identical to the WRITE case, except
that everything has shifted four tPACKET intervals further from the REQ packet. The sum of tRP, tRCD,
and tCAC is also known as tRC (the row cycle time).
Auto-Precharge Option: For a WRITE, ACTV/WRITE or a PRE/ACTV/WRITE command, the
bank operations are complete once the last data octbyte has been accessed. The bank will be left with
the requested row activated. For a WRITEA, ACTV/WRITEA or a PRE/ACTV/WRITEA command,
there is an additional step. During the two tPACKET intervals after the last data octbyte access an autoprecharge operation (requiring tRPA for the row precharge, auto) is performed. This leaves the bank
in a precharged state.
T0
T1
T2
COL b
COL c
COL d
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tWSW
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
tCDW
WSTRB
WRITEA
REQ
Packet
BNK/ROW DIN a
/COL a
tSDW
WTERM
tTDW
DIN b
tCAC
DIN c
DIN d
tCC
tCC
tCC
tRPA
(a) WRITEA - RANDOM WRITE CYCLES WITHIN A PAGE
20/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
T5
COL b
COL c
COL d
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tASW
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
tCDW
ACTV
/WRITEA
REQ
Packet
BNK/ROW
/COL a
WSTRB
WTERM
tSDW
tTDW
DIN a
Bank Operation
tRCD
DIN b
tCAC
DIN c
DIN d
tCC
tCC
tCC
tRPA
tRAC
(b) ACTV/WRITEA - BANK ACTIVATE AND RANDOM WRITE CYCLES WITHIN A PAGE
T0
T1
T2
T3
T4
T5
T6
COL b
COL c
COL d
T7
T8
T9
T10
tCC
tRPA
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tPSW
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
Bank Operation
ACTV
/WRITEA
REQ
Packet
BNK/ROW
/COL a
tCDW
WSTRB
WTERM
tSDW
tTDW
DIN a
tRP
tRCD
DIN b
tCAC
DIN c
DIN d
tCC
tCC
tRC
(c) PRE/ACTV/WRITEA - BANK PRECHARGE/ACTIVATE AND RANDOM WRITE CYCLES IN A PAGE
Fig. 9 Write Transactions
21/45
¡ Semiconductor
MSM5718C50/MD5764802
BYTEMASK OPERATIONS
All memory write transactions (OP1,OP0 = 01) use the M7..M0 field of the REQ packet to control byte
masking of the first octbyte DINa of write data. M7 controls bits D56..D63,E7 while M0 controls bits
D0..D7, E0. A “0” means don’t write and a "1" means write.
The M7..M0 field should be filled with “00000000” for non-memory-write transactions.
OP2 = 1: When OP2 = 1 for a memory write transaction, the remaining data octbytes (DINb, DINc,...)
are written unconditionally (all bytes are written).
OP2 = 0: When OP2 = 0, the remaining data octbytes (DINb, DINc,...) are written with a bytemask.
Each bytemask is carried on the DQ8 wire, pipelined one tPACKET interval ahead of the data octbyte
it controls.
Figure 12 (b) shows the format of the M packet and DIN packet when OP2 = 0. M7 controls bits
D56..D63 (of the next DIN packet) and M0 controls bits D0..D7 (of the next DIN packet). Figure 12
(a) summarizes the location of the M packets and the DIN packets they control.
When 64M RDRAM is used, there is no limitation caused by the use of bytemask operations; the
DQ8 wire is only used for the REQ packet and M packets.
When 18M RDRAM is used, there is a limitation caused by the use of bytemask operations; the E7..E0
bits of the 72 bit DIN packet may not be used when OP2 = 0. To achieve bytemasking, it will be
necessary to use read-modify-write operations or single-octbyte writes with the bytemask in the
REQ packet and OP2 = 1.
DIN/DOUT
M7, M6,...M0 from REQ (Ma) and DQ8 (Mb, Mc,...)
64/72
64/72
8
64/72
Memory
Data
Fig. 10 Details of ByteMask Logic
22/45
¡ Semiconductor
MSM5718C50/MD5764802
BITMASK OPERATIONS
All memory write transactions (OP1,OP0 = 01) may use bitmask operations (OP5,OP4). Bitmask
operations may be used simultaneously with the bytemask operations just described; a particular
data bit is written only if the corresponding bytemask M and bitmask m are set.
OP5,OP4 = 00: This is the default option with no bitmask operation selected; all data bits are written,
subject to any bytemask operation.
OP5,OP4 = 01: This is the write-per-bit option. Figure 13 (a) shows the transaction format. The 64/
72-bit MASK register is used as a static bit mask, controlling whether each of the 64/72 bits of DIN
octbytes is written (m = 1) or not written (m = 0). The MASK register is loaded using the dynamic
bitmask operation (OP5,OP4 = 10).
OP5,OP4 = 10: This is the dynamic bitmask option. Figure 13 (b) shows the transaction format.
Alternate octbytes (ma, mc,..) are loaded into the MASK register to be used as a bitmask for the data
octbytes (DINb, DINd,...). Only the COL packets which correspond to DIN packets (COLb, COLd,..)
contain a valid column address. The MASK register is left with the last bitmask that is transferred
(mc in this case). The write-enable signal is asserted after DIN packet (Figure 11).
OP5,OP4 = 11: This is the mask-per-bit option. Figure 13 (c) shows the transaction format. The 64/
72-bit MASK register is used as a static data octbyte DIN. The bitmask packets (ma, mb,...) control
whether the data is written (m = 1) or not written (m = 0). The MASK register is loaded using the
dynamic bitmask operation (OP5,OP4 = 10).
DIN/DOUT
(DIN packet) • (OP5, OP4 = 10)
(m packet) • (OP5, OP4 = 10)
64/72
64/72
MASK Register
64/72
64/72
64/72
64/72
64/72
64/72
1
Memory Write
Data Enable
11
01, 10
OP5, OP4 value
Enable BitMask Path
Fig. 11 Details of BitMask Logic
23/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
COL b
COL c
COL d
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
ACTV
/WRITE
DQ8
(BUSDATA[8])
BNK/ROW
/COL
Mb
Mc
Md
DQ7,..DQ0
(BUSDATA[7:0])
BNK/ROW
/COL/M a
DIN a
DIN b
DIN c
WSTRB
WTERM
DIN d
(a) OP2 = 0 - WRITE TRANSACTION WITH BYTEMASK
t0
t1
t2
t3
t4
t5
t6
t7
Mb
CLK
Mc
DQ8
M0
M1
M2
M3
M4
M5
M6
M7
DQ7
D7
D15
D23
D31
D39
D47
D55
D63
DQ6
D6
D14
D22
D30
D38
D46
D54
D62
DQ5
D5
D13
D21
D29
D37
D45
D53
D61
DIN a
DQ4
D4
D12
D20
D28
D36
D44
D52
D60
DIN b
DQ3
D3
D11
D19
D27
D35
D43
D51
D59
DIN c
DQ2
D2
D10
D18
D26
D34
D42
D50
D58
DIN d
DQ1
D1
D9
D17
D25
D33
D41
D49
D57
DQ0
D0
D8
D16
D24
D32
D40
D48
D56
Md
(b) OP2 = 0 - DATA AND BYTEMASK PACKET FORMATS
Fig. 12 ByteMask Operations
24/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
COL b
COL c
COL d
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
ACTV
/WRITE
REQ
Packet
BNK/ROW
/COL a
WSTRB
WTERM
DIN a
DIN b
DIN c
DIN d
(a) OP5, OP4 = 0, 1 - BITMASK IN MASK REGISTER, DATA FROM DQ INPUTS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
MASK
PEGISTER
COL b
ACTV
/WRITE
REQ
Packet
BNK/ROW
COL d
WSTRB
WTERM
ma
DIN b
ma
mc
DIN d
mc
(b) OP5, OP4 = 1, 0 - BITMASK FROM DQ INPUTS, DATA FROM DQ INPUTS
25/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
COL b
COL c
COL d
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
ACTV
/WRITE
REQ
Packet
BNK/ROW
/COL a
WSTRB
WTERM
ma
mb
mc
md
(c) OP5, OP4 = 1, 1 - BITMASK FROM DQ INPUTS, DATA IN MASK REGISTER
Fig. 13 BitMask Operations
REGISTERS
There are six control registers in an RDRAM. They contain read-only fields, which allow a memory
controller to determine the type of RDRAM that is present. They also contain read-write fields which
are used to configure the RDRAM.
Registers are read and written with transactions that are identical to one-octbyte memory read and
write transactions. These transaction formats are illustrated in Figure 14. There is one difference with
respect to memory transactions; for a register write, it is necessary to allow a time of tWREG to elapse
before another transaction is directed to the RDRAM.
In the descriptions of some of the read-write fields, the user is instructed to set the field to a default
value (“Set to 1.”, for example). When this is done, the suggested value is the one needed for normal
operation of the RDRAM.
A summary of the control registers and a brief description follows
DEVICETYPE
DEVICEID
MODE
REFROW
RASINTERVAL
DEVICEMFGR
RDRAM size, type information
Set RDRAM base address
Set RDRAM operating modes
Set refresh address for Powerdown
Set RAS intervals
RDRAM manufacturer information
The control register fields are described in detail from Figure 15 to Figure 20. The format of the one
octbyte DIN or DOUT packet that is written to or read from the register is shown. Gray bits are
reserved, and should be written as zero. The value of the A10..A3,REGSEL field needed to access
each register is also shown. The ROW and BANK address fields are not used for register read and
write transactions.
26/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tRSR
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
tTDR
RSTRB
RREG /RTERM
REQ
tSDR
Packet
DEV
/COL a
Next
REQ
DOUT a
(a) REGISTER READ TRANSACTION
T0
T1
T2
T3
T4
T5
T6
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
tWSW
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
WSTRB WTERM
WREG
REQ
Packet tTDW
DEV DIN a
/COL a
tSDW
Next
REQ
tWREG
(b) REGISTER WRITE TRANSACTION
Fig. 14 Register Transactions
27/45
¡ Semiconductor
MSM5718C50/MD5764802
DEVICETYPE Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000000002
t7
CLK
Description
This is a read only register with
fields that describe the
characteristics of the device. This
includes the number of address
bits for bank, row, and column. The
column count includes the
(unimplemented) A2,A1,A0 bits.
The other fields specify the
architecture version, the device
type, and the byte size. This
register is read during initialization
so the memory controller can
determine the proper memory
configuration.
DQ8
DQ7
COL3
BNK3
VER3
DQ6
COL2
BNK2
VER2
DQ5
COL1
BNK1
VER1
DQ4
COL0
BNK0
VER0
DQ3
ROW3
TYP3
DQ2
BONUS ROW2
TYP2
DQ1
ROW1
TYP1
DQ0
ROW0
TYP0
DIN/DOUT Format
Field
18M
64M
Description
VER3... VER0
00102
Architecture Version is Concurrent
TYP3... TYP0
00002
Device is DRAM
BNK3... BNK0
00012 = 1 00102 = 2
Number of bank address bits
ROW3... ROW0
10012 = 9 10102 = 10
Number of row address bits
COL3... COL0
11112 = 11 10112 = 11
Number of column address bits
BONUS
1
0
Specifies ¥ 8(0) or ¥ 9(1) byte length
Fig. 15 DEVICETYPE Register
28/45
¡ Semiconductor
MSM5718C50/MD5764802
DEVICEID Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000000012
t7
CLK
Description
This is a read-write register with a
single field ID35...ID21. This field is
compared to the A35...A21 address
bits of the REQ packet to determine
if the current transaction is directed
to this RDRAM. If the OP3 bit of the
REQ packet is set, then this match
is ignored (broadcast operation to
all RDRAMs). Note that some low
order bits of this field are not
compared for the higher density
RDRAMs.
DQ8
DQ7
ID25
DQ6
ID24
ID33
DQ5
ID23
ID32
DQ4
ID22
ID31
DQ3
ID21
ID30
ID26
ID34
DQ2
ID29
DQ1
ID28
DQ0
ID27
ID35
DIN/DOUT Format
Field
RDRAM Size
Description
ID35..ID21
18M
Compared to A35...A21 for device match
ID35..ID23
64M
Compared to A35...A23 for device match
Fig. 16 DEVICEID Register
29/45
¡ Semiconductor
MSM5718C50/MD5764802
MODE Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000000112
t7
CLK
Description
This is a read-write register with
fields that control the operating
modes of the RDRAM. The modes
include output current control
(C5..C0, CCAsym), clock/power
control (FR), compatibility control
(BASE), tTR skip control (SV, SK,
AS), and initialization control (DE).
Refer to the Concurrent RDRAM
Design Guide for a detailed
discussion of the use of these
fields.
DQ8
DQ7
C5
C4
C3
DQ6
C2
C1
C0
DQ5
DQ4
SV
DQ3
SK
DQ2
AS
DQ1
DE
FR
The reset values in the MODE
registers are all zeros except the
AS = 1 and C5..C0 = 111111.
BASE
CCAsym
DQ0
DIN/DOUT Format
Field
Description
C5... C0
Specifies IOL output current. 1111112Òmin, 0000002Òmax.
FR
Force RXCLK,TXCLK on. FR = 1 Ò RDRAM Enable.
BASE
Set to 1 if Base RDRAMs with acknowledge are present.
CCAsym
Current Control-Asymmetry adjustment.
SV
Skip value for auto tTR control. Read-only.
SK
Specifies Skip value for manual tTR control. Set to 0.
AS
Specifies manual (0) or auto (1) tTR control. Set to 1.
DE
Device Enable. Used during initialization.
Fig. 17 MODE Register
30/45
¡ Semiconductor
MSM5718C50/MD5764802
REFROW Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000001012
t7
CLK
Description
This is a read-write register which
is used to track the bank/row
address that will be refreshed by
the next SIN pulse in Powerdown
mode. This register is not used for
normal refresh in Enable mode the bank/row address is supplied
by the external controller in the
refresh transaction.
DQ8
DQ7
REF6
DQ6
REF5
DQ5
REF4
DQ4
REF3
REF11
DQ3
REF2
REF10
DQ2
REF1
REF9
DQ1
REF0
REF8
DQ0
SP
REF7
Powerdown is entered by setting
the SP field to one. The REF field
should be simultaneously set with
the next bank/row to be refreshed.
When Powerdown is exited, this
register is read from one RDRAM
to set the proper bank/row address
for normal refresh operation.
The reset value of the REFROW
registers are all zeros.
DIN/DOUT Format
Field
RDRAM Size
Description
REF10
18M
Bank address of next row to be refreshed
REF11, REF10
64M
Bank address of next row to be refreshed
REF8...REF0
18M
Row address of next row to be refreshed
REF9...REF0
64M
Row address of next row to be refreshed
SP
—
Set to enter Powerdown mode.
Fig. 18 REFROW Register
31/45
¡ Semiconductor
MSM5718C50/MD5764802
RASINTERVAL Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000001102
t7
CLK
Description
This is a read-write register with
fields that control the length of the
RAS intervals of the RDRAM. The
relationship between the tRC, tRCD,
tRPA and tRP intervals (in tCYCLE
units) and the P, S, and R fields
follows:
DQ8
DQ7
DQ6
tRC = (10012 + R + S + P) • tCYCLE
DQ5
tRCD = (O1012 + S) • tCYCLE
DQ4
P0
S0
R0
DQ3
P1
S1
R1
DQ2
P2
S2
R2
DQ1
P3
S3
R3
tRP = (O1012 + P) • tCYCLE
tRPA = (O1012 + P) • tCYCLE
DQ0
DIN/DOUT Format
Field
Description
R3...R0
Specifies the (tRC - tRCD - tRP) restore interval. Set to 01112.
S3...S0
Specifies the tRCD sence interval. Set to 00112.
P3...P0
Specifies the tRP and tRPA precharge intervals. Set to 00112.
Fig. 19 RASINTERVAL Register
32/45
¡ Semiconductor
MSM5718C50/MD5764802
DEVICEMFGR Register
t0
t1
A10,A9,A8,A7,A6,A5,A4,A3,REGSEL
t2
t3
t4
t5
t6
0000010012
t7
CLK
Description
This is a read-only register with
fields that specify the
manufacturer's identification
number and manufacturer-specific
date-code and version information.
DQ8
DQ7
C7
C15
M7
M15
DQ6
C6
C14
M6
M14
DQ5
C5
C13
M5
M13
DQ4
C4
C12
M4
M12
DQ3
C3
C11
M3
M11
DQ2
C2
C10
M2
M10
DQ1
C1
C9
M1
M9
DQ0
C0
C8
M0
M8
Contact Rambus for a list of
manufacturer's identification
numbers.
DIN/DOUT Format
Field
Description
M15...M0
Manufacturer's identification number
C15...C0
Manufacturer's datecode or version information
Fig. 20 DEVICEMFGR Register
33/45
¡ Semiconductor
MSM5718C50/MD5764802
INITIALIZATION
The first step in initialization is to reset the RDRAM. This is accomplished by driving RESET packets
for a time tRESET or greater. This causes the RDRAM to assume a known state. This also causes the
internal clocking logic (a delay-locked-loop) to begin locking to the external clock. This requires a
time of tLOCK. At this point, the RDRAM is ready to accept transactions. This timing sequence is
shown in Figure 21 (a).
The next step for the memory controller is to read and write the six control registers, in order to
determine the size and type of RDRAM that is present, and to configure it properly. A full
initialization sequence is provided in the Concurrent RDRAM Design Guide.
POWER MANAGEMENT
There are several power modes available in an RDRAM. These modes permit power dissipation and
latency to be traded against one another.
Enable Mode: The simplest option is to remain permanently in Enable power mode. This is done by
setting the FR field to a one in the MODE register (refer to Figure 17). The RDRAM will return to
Enable mode when it is not performing a read or write transaction. This is the operating mode which
has been assumed in all the transaction timing diagrams (except in Figure 21 (b).
Suspend Mode: The average power can be reduced by using Suspend power mode. This is done
by setting the FR field to a zero. A CKE packet must be sent a time tCKE ahead of each REQ packet
(this is shown in T0 in Figure 21 (b)). This causes the RDRAM to transition from Suspend to
Enable mode. When the RDRAM has finished the transaction, it returns to Suspend mode. The
average power of the RDRAM is reduced, but at the cost of slightly greater latency. There is no
loss of effective bandwidth, since the CKE packet may be overlapped with the other packet
types.
Powerdown Mode: The RDRAM power can be reduced to a very low level with Powerdown mode.
Powerdown is entered by setting the SP field of the REFROW register to one (the REF field is
simultaneously set to the next bank and row to be refreshed). As a result, most of the RDRAM’s
circuitry is disabled, although its memory must still be refreshed. This is accomplished by pulsing
the SIN input with a cycle time of tSCYCLE or less.
Powerdown mode is exited when PWRUP packets are asserted for a time tPWRUP on the Command
wire. The internal clocking logic will begin locking to the external clock. After a time of tLOCK the
RDRAM will be in Enable mode, ready for the next REQ packet. This is illustrated in Figure 21 (c).
34/45
¡ Semiconductor
MSM5718C50/MD5764802
REFRESH
Memory refresh (when not in Powerdown) uses a one-octbyte broadcast memory write with the
following REQ field values:
OP5..0
AUTO
ACTV
PEND
M7..0
0010012
1
1
000/001/010
000000002
A35..3
DEV:
BNK:
ROW:
COL:
REGSEL: 0
0..0 (unused)
next bank
next row
0..0 (unused)
The transaction format for memory refresh is shown in Figure 22 (a). The transaction may be
noninterleaved or interleaved (if interleaved, the PEND field must be properly filled). The transaction
causes the requested row of the requested bank of all RDRAMs to be activated and then autoprecharged (note that the interval tRP + tRCD should elapse since the specified bank of some
RDRAMs might be open). This transaction must be repeated at intervals of tREF/ (NBNK•NROW),
where NBNK and NROW are the number of banks and rows in the RDRAM. This interval will be the
same for the different RDRAM configurations. For each refresh transaction, the bank and row field
of A35..A3 must be incremented, with the bank field changing most often so the tRAS, MAX parameter
is not exceeded.
CURRENT CONTROL
The transaction format for current control is shown in Figure 22 (b). This transaction is encoded as
a directed register read operations, and is repeated at intervals of tCCTRL/NDEV, where NDEV is the
number of devices on the Channel. This will maintain the optimal current control value.
OP5..0
AUTO
ACTV
PEND
M7..0
0001102
0
0
000
000000002
A35..3
DEV:
BNK:
ROW:
COL:
REGSEL: 0
next device
0..0 (unused)
0..0 (unused)
000001012
After a tLOCK, a series of 64 of these current control transactions must be directed to each device on
the Channel to establish the optimal current control value.
35/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
•••
T3
T4
T5
•••
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
•••
•••
tRESET
COMMAND
(BUSCTRL)
RESET
RESET
DQ8,..DQ0
(BUSDATA[8:0])
•••
tLOCK
•••
RESET
•••
REQ
Packet
BNK/ROW
/COL a
•••
(a) RESET PACKET FOR INITIALIZATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
•••
tCKE
COMMAND
(BUSCTRL)
•••
CKE
REQ
Packet
BNK/ROW
/COL a1
DQ8,..DQ0
(BUSDATA[8:0])
•••
(b) CKE PACKET FOR SUSPEND-TO-ENABLE POWER MODE TRANSITION
T0
T1
•••
T3
T4
T5
•••
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
•••
tPWRUP
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
PWRUP PWRUP
tLOCK
•••
•••
REQ
Packet
BNK/ROW
/COL a
(c) PWRUP PACKET FOR POWERDOWN-TO-ENABLE POWER MODE TRANSITION
Fig. 21 Transactions using RESET, CKE, and PWRUP Packets
36/45
¡ Semiconductor
T0
MSM5718C50/MD5764802
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
•••
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
ACTV
/WRITEA
REQ
Packet
•••
BNK/ROW
•••
•••
•••
WSTRB WTERM
Next
REQ
•••
DIN a
tRP + tRCD
•••
ACTV
/WRITEA
REQ
Packet
•••
BNK/ROW
•••
tCAC
WSTRB WTERM
Next
REQ
DIN a
tRP + tRCD
tCAC
tREF/ (NBNK • NROW)
(a) REFRESH TRANSACTION
*
**
CLK
(RX/TXCLK)
ADDRESS
(BUSENABLE)
COMMAND
(BUSCTRL)
DQ8,..DQ0
(BUSDATA[8:0])
•••
RREG
REQ
Packet
DEV
/COL a
•••
RSTRB RTERM
Next
REQ
DOUT a DOUT b
•••
RREG
RSTRB RTERM
REQ
Packet
DEV
/COL a
DOUT a
tCCTRL/NDEV
(b) CURRENT CONTROL TRANSACTION
Fig. 22 Refresh and Current Control Transactions
Due to the nature of the current control operation, a delay of 4 BusClks may be needed before
and after the current control transaction.
If the request immediately before the current control request is a write request, there should be
a 4 BusClks (1 Synclk) delay between the end of write data and the beginning of the RDRAM
current control request (see * in Figure 22 (b)). If the request immediately before the current
control request is a read request, no delay is required.
If the current control data is followed by a request using the MODE register address, there must
be a 4BusClks (1 Synclk) delay between the end of current control data transport and the
subsequent requests using the MODE register addresses (see ** in Figure 22 (b)). Any other
request may immediately follow the currrent control data transport.
37/45
¡ Semiconductor
MSM5718C50/MD5764802
ABSOLUTE MAXIMUM RATINGS
The following table represents stress ratings only, and functional operation at the maximum ratings
is not guaranteed. Extended exposure to the maximum ratings may affect device reliability.
Although these devices contain protective circuitry to resist damage from static electric discharge,
always take precautions to avoid high static voltages or electric fields.
Symbol
VI,ABS
Min.
Max.
Unit
Voltage applied to any RSL pin with respect to Gnd
Parameter
–0.3
VDD,MAX+0.3
V
VI,CMOS,ABS
Voltage applied to any CMOS pin with respect to Gnd
–0.3
VDD+0.3
V
VDD,ABS
Voltage on VDD with respect to Gnd
–0.3
VDD,MAX+1.0
V
TJ,ABS
Junction temperature under bias
–55
125
°C
TSTORE
Storage temperature
–55
125
°C
CAPACITANCE
Symbol
CI
Parameter and Conditions
RSL input parasitic capacitance
Min.
Max.
Unit
1.6a/2.0b
2.0a/2.5b
pF
nH
LI
RSL input parasitic inductance
—
2.7a/5.0b
CI,CMOS
CMOS input parasitic capacitance
—
8
pF
Min.
Max.
Unit
—
1.0a/1.5b
mA
mA
mA
Notes:
a. 18M RDRAM
b. 64M RDRAM
IDD-SUPPLY CURRENT PROFILE
Mode
Powerdown
Description
Device shut down, clock unlocked
Suspend
Device inactive, clock locked but Suspended
—
115a/185b
Enable
Device active, clock unlocked and Enabled
—
380a/400b
READ
Device reading column data
—
590
mA
WRITE
Device writing column data
—
495
mA
ACTV/READ
Device reading column data in bank 1 and activating row in bank 2
—
700
mA
ACTV/WRITE
Device writing column data in bank 1 and activating row in bank 2
—
660
mA
Notes:
a. 18M RDRAM
b. 64M RDRAM
38/45
¡ Semiconductor
MSM5718C50/MD5764802
RECOMMENDED ELECTRICAL CONDITIONS
Symbol
Parameter and Conditions
Min.
Max.
Unit
VDD, VDDA
Supply voltage — 3.3 V version
3.15
3.45
V
VREF
Reference voltage
1.9
VDD–0.8
V
VIL
RSL Input low voltageb
VREF–0.35
VREF–0.8
V
VIH
RSL Input high voltageb
VREF+0.35
VREF+0.8
V
VIL,CMOS
CMOS input low voltage
–0.5
0.8
V
VIH,CMOS
CMOS input high voltage
1.8
VDD+0.5
V
TC
Package Surface Temperature
0
90
°C
Min.
Max.
Unit
–10
10
mA
–10
10
mA
ELECTRICAL CHARACTERISTICS
Symbol
Parameter and Conditions
IREF
VREF CURRENT @
IOH
RSL output high current @ (0 £ VOUT £ VDD)
VREF,MAX
a
INONE(manual)
RSL IOL current @ VOUT = 1.6 V @ C[5:0] = 000000 (010)
0.0
4.0
mA
IALL(manual)
RSL IOL current @ VOUT = 1.6 V @ C[5:0] = 111111 (6310)a
30.0
80.0
mA
II,CMOS
CMOS input leakage current @ (0 £ VI,CMOS £ VDD)
–10.0
10.0
mA
VOL,CMOS
CMOS output voltage @ IOL,CMOS = 1.0 mA
0.0
0.4
V
VOH,CMOS
CMOS output high voltage @ IOH,CMOS = –0.25 mA
2.0
VDD
V
Notes:
a. In manual-calibration mode (CCEnable = 0) this is the value written into the C[5:0] field of the
Mode register to produce the indicated IOL value. Values of IOL in between the INONE and IALL
are produced by interpolating C[5:0] to intermediate values. For example, C[5:0] = 011111 (3110)
produces an IOL in the range of 15 to 40 mA.
b. IOL of Bus Data outputs is set at 30 mA when Bus Enable pin VIH/VIL value is measured.
39/45
¡ Semiconductor
MSM5718C50/MD5764802
RECOMMENDED TIMING CONDITIONS
Symbol
Parameter
tCR, tCF
TXCLK and RXCLK input rise and fall times
tCYCLE
TXCLK and RXCLK cycle times
tTICK
tCH, tCL
tTR
Transfer time per bit per pin (this timing interval is
synthesized by the RDRAM's clock generator)
TXCLK and RXCLK high and low times
TXCLK-RXCLK differential
Min.
Max.
0.3
0.8
3.75a/3.33b 4.15a/4.15b
Unit
ns
ns
0.5
0.5
tCYCLE
45%
55%
tCYCLE
0
0.7
tCYCLE
tCYCLE
4
4
tDR, tDF
Transfer time for REQ, DIN, DOUT, COL, WSTRB,
WTERM, RSTRB, RTERM, CKE, PWRUP and RESET
packets
DQ/ADDRESS/COMMAND input rise and fall times
0.3
0.6
ns
tS
DQ/ADDRESS/COMMAND-to-RXCLK setup time
0.35
—
ns
tPACKET
tH
RXCLK-to-DQ/ADDRESS/COMMAND hold time
0.35
—
ns
tREF
Refresh interval
—
17c/33d
ms
tSCYCLE
Powerdown refresh cycle time
0.4
16.6c/8.0d
ms
tSL
Powerdown refresh low time
0.2
10c/7.8d
ms
ms
tSH
Powerdown refresh high time
0.2
10c/7.8d
tCCTRL
Current control interval
—
150
ms
tRAS
RAS interval (time a row may stay activated)
—
133
ms
tLOCK
RDRAM clock-locking time for reset or powerup
—
5.0
ms
Notes:
a. 533 MHz RDRAM
b. 600 MHz RDRAM
c. 18M RDRAM
d. 64M RDRAM
40/45
¡ Semiconductor
MSM5718C50/MD5764802
TIMING CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Unit
tPIO
SIn-to-SOut delay @ CLOAD,CMOS = 40 pF
—
25
ns
tQ
DQ output time
–0.4
0.4
ns
tQR, tQF
DQ output rise and fall times
0.3
0.5
ns
RAMBUS CHANNEL TIMING
The next table shows important timings on the Rambus channel for common operations. All timings
are from the point of view of the channel master, and thus have the bus overhead delay of tCYCLE
per bus transversal included where appropriate.
Symbol and Figure
Parameter
Min. Max.
6a/7b
—
4
—
tCAC - Figure 8,9
Column ACcess time. May overlap tRCD, tRP, or tRPA to another bank
tCC - Figure 8,9
Column Cycle time. May overlap tRCD, tRP, or tRPA to another bank
tRCD - Figure 8,9
Row to Column Delay. May overlap tCAC or tCC to another bank
8
—
tRP - Figure 8,9
Row Precharge time. May overlap tCAC or tCC to another bank
8
—
tRPA - Figure 8,9
Row Precharge Auto. May overlap tRPA, tCAC or tCC to another bank
8
—
tRAC - Figure 8,9
Row ACcess time. (tRAC = tRCD + tCAC).
15
—
tRC - Figure 8,9
Row Cycle time. (tRC = tRP + tRCD + tCAC).
23
—
tRSR - Figure 8 (a)
Start of REQ (READ) to start of RSTRB packet for Read transaction.
2
—
tASR - Figure 8 (b)
Start of REQ (ACTV/READ) to start of RSTRB packet for Read transaction.
11
—
tPSR - Figure 8 (c)
Start of REQ (PRE/ACTV/READ) to start of RSTRB packet for Read transaction.
19
—
tCDR - Figure 8
Start of COL packet to start of DOUT packet for Read transaction.
12
12
tSDR - Figure 8
Start of RSTRB packet to start of DOUT packet for Read transaction.
8
8
tTDR - Figure 8
Start of RTERM packet to end of DOUT packet for Read transaction.
12
12
tWSW - Figure 9 (a)
Start of REQ (WRITE) to start of WSTRB packet for Write transaction.
0
—
tASW - Figure 9 (b)
Start of REQ (ACTV/WRITE) to start of WSTRB packet for Write transaction.
5
—
tPSW - Figure 9 (c)
Start of REQ (PRE/ACTV/WRITE) to start of WSTRB packet for Write transaction.
13
—
tCDW - Figure 9
Start of COL packet to start of DIN packet for Write transaction.
8
8
tSDW - Figure 9
Start of WSTRB packet to start of DIN packet for Write transaction.
4
4
tTDW - Figure 9
Start of WTERM packet to end of DIN packet for Write transaction.
4
4
tRESET - Figure 21 (a)
Length of RESET packets to cause RDRAM to reset.
800 ns
—
tCKE - Figure 21 (b)
Start of CKE packet to start of REQ packet for Suspend-to-Enable.
4
7
tPWRUP - Figure 21 (c) Length of PWRUP packets to cause Powerdown-to-Enable.
8
8
tWREG - Figure 14 (b)
16
—
End of DIN packet for WREG transaction to start of next REQ packet.
Notes: All units are tCYCLE when not mentioned
a. For READ, WRITE commands
b. For ACTV/READ, ACTV/WRITE, PRE/ACTV/READ, PRE/ACTV/WRITE commands
41/45
¡ Semiconductor
MSM5718C50/MD5764802
TIMING WAVEFORM
RSL Rise/Fall Timing
VIH,MIN
80%
20%
VIL,MAX
VRxClk
VTxClk
tCF
tCR
VIH,MIN
80%
20%
VIL,MAX
VDQ,IN
VCOMMAND
VADDRESS
tDF
tDR
VOH,MIN
80%
20%
VOL,MAX
VDQ,OUT
tQF
tQR
Where:
VOH,MIN = VTERM,MIN
VOL,MAX = VTERM,MAX - ZO* (IOL,MIN)
RSL Clock Timing
Logic 0, VIH
VTxClk
VREF
tCL
Logic 1, VIL
tCH
tCYCLE
tTR
tCYCLE
tCL
tCH
Logic 0, VIH
VRxClk
VREF
Logic 1, VIL
42/45
¡ Semiconductor
MSM5718C50/MD5764802
,,,
,
,
,
RSL Input (Receive) Timing
tCYCLE
tTICK (even)
tTICK (odd)
Logic 0, VIH
VRxClk
VREF
Logic 1, VIL
tS
tH
tS
tH
Logic 0, VIH
VCOMMAND
VREF
VADDRESS
Logic 1, VIL
RSL Output (Transmit) Timing
tCYCLE
tTICK (even)
tTICK (odd)
Logic 0, VOH
VTxClk
50%
tQ,MAX
tQ,MAX
Logic 1, VOL
Logic 0, VOH
VDQ,OUT
50%
Logic 1, VOL
tQ,MIN
tCYCLE/4
tQ,MIN
tCYCLE/4
43/45
¡ Semiconductor
SIN/SOUT Timing
VSIN
,
MSM5718C50/MD5764802
Logic 1
VSW,CMOS
Logic 0
tPIO,MAX
VSOUT
tPIO,MIN
VSIN
tSL
tSH
Logic 1
VSW,CMOS
Logic 0
Logic 1
VSW,CMOS
Logic 0
tSCYCLE
VSW,CMOS = 1.5 V
44/45
¡ Semiconductor
MSM5718C50/MD5764802
PACKAGE DIMENSIONS
(Unit : mm)
SHP32-P-1125-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.87 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
See also the PACKAGE INFORMATION DATA BOOK for thermal resistances qjc and qja.
45/45
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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