ETC1 MDT2005 8-bit micro-controller uses a fully static cmos design technology Datasheet

MDT2005
MDT2005
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology
combines higher speeds and smaller size with the low power and high noise immunity of
CMOS.
On chip memory system includes 0.5 K(for MDT2005) bytes of ROM, and 32 bytes of static
RAM.
2. Features
The followings are some of the features on the hardware and software :
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
Fully COMS static design
8-bit data bus
On chip ROM size : 512 words for MDT2005
Internal RAM size : 32 bytes
(25 general purpose registers, 7 special registers)
36 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.3V ~ 6.3 V
Operating frequency : 0 ~ 20 MHz
The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except
the branch instruction
Addressing modes include direct, indirect and relative addressing modes
Power-on Reset
Power edge-detector Reset
Sleep Mode for power saving
8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler
4 types of oscillator can be selected by programming option:
RC-Low cost RC oscillator
LFXT-Low frequency crystal oscillator
XTAL-Standard crystal oscillator
HFXT-High frequency crystal oscillator
u 4 oscillator start-up time can be selected by programming option:
150 µs, 20 ms, 40 ms, 80 ms
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P. 1
VER1.1
MDT2005
u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely
u 12 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT2005 range from appliance motor control and high speed
automotive to low power remote transmitters/receivers, pointing devices, and
telecommunications processors, such as Remote controller, small instruments, chargers, toy,
automobile and PC peripheral … etc.
4. Pin Assignment
PA2
PA3
RTCC
/MCLR
Vss
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PA1
PA0
OSC1
OSC2
Vdd
PB7
PB6
PB5
PB4
5. Pin Function Description
Pin Name
I/O
Function Description
PA0~PA3
I/O
Port A, TTL input level
PB0~PB7
I/O
Port B, TTL input level
RTCC
I
Real Time Clock/Counter, Schmitt Trigger input levels
/MCLR
I
Master Clear, Schmitt Trigger input levels
OSC1
I
Oscillator Input
OSC2
O
Oscillator Output
Vdd
Power supply
Vss
Ground
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P. 2
VER1.1
MDT2005
6. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
RTCC
02
PC
03
STATUS
04
MSR
05
Port A
06
Port B
07~1F
Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0
(2) RTCC (Real Time Counter/Counter Register) : R1
(3) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTIW, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- always 0 (ROM 0.5K)
LJUMP, LCALL --- from instruction word
RTIW, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTIW, RET --- from STACK
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P. 3
VER1.1
MDT2005
(4) STATUS (Status register) : R3
Bit
Symbol
Function
0
C
Carry bit
1
HC
Half Carry bit
2
Z
Zero bit
3
PF
Power loss Flag bit
4
TF
Time overflow Flag bit
——
General purpose bit
5-7
(5) MSR (Memory Select Register) : R4
(6) PORT A : R5
PA3~PA0, I/O Register
(7) PORT B : R6
PB7~PB0, I/O Register
(8) TMR (Time Mode Register)
Bit
Symbol
Function
Prescaler Value
2—0
PS2—0
3
PSC
4
TCE
5
TCS
RTCC rate
WDT rate
0 0 0
1:2
1:1
0 0 1
1:4
1:2
0 1 0
1:8
1:4
0 1 1
1 : 16
1:8
1 0 0
1 : 32
1 : 16
1 0 1
1 : 64
1 : 32
1 1 0
1 : 128
1 : 64
1 1 1
1 : 256
1 : 128
Prescaler assignment bit :
0 — RTCC
1 — Watchdog Timer
RTCC signal Edge :
0 — Increment on low-to-high transition on RTCC pin
1 — Increment on high-to-low transition on RTCC pin
RTCC signal set :
0 — Internal instruction cycle clock
1 — Transition on RTCC pin
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P. 4
VER1.1
MDT2005
(9) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is “write-only”
=“0”, I/O pin in output mode;
=“1”, I/O pin in input mode.
(10) EPROM Option by writer programming :
Oscillator Type
RC
Oscillator
Oscillator Start-up Time
150 µs,20ms,40ms,80ms
HFXT Oscillator
20 ms,40ms,80ms
XTAL Oscillator
20ms,40 ms,80ms
LFXT Oscillator
40 ms,80 ms
Watchdog Timer control
Watchdog timer disable all the time
Watchdog timer enable all the time
Power Edge Detect
PED
Security bit
Disable
Security weak Disable
PED Enable
Security Disable
Security Enable
The default EPROM security is weak disable. Once the IC was set in enable or disable, it’s
forbidden to set in disable or enable again.
(B) Program Memory
Address
Description
000-1FF
Program memory for MDT2005
1FF
The starting address of the power on, external reset
or WDT for MDT2005
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P. 5
VER1.1
MDT2005
7. Reset Condition for all Registers
Register
Address
Power-On Reset
/MCLR or WDT Reset
IAR
00h
-
-
RTCC
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
000# #uuu
MSR
04h
111x xxxx
111u uuuu
PORT A
05h
- - - - xxxx
- - - - uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
Note : u=unchanged, x=unknown, - =unimplemented, read as “0”
#=value depends on the condition of the following table
Condition
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
u
u
/MCLR reset during SLEEP
1
0
WDT reset (not during SLEEP)
0
1
WDT reset during SLEEP
0
0
8. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0→WT
010000 00000010
SLEEP
Sleep mode
0→WT, stop OSC TF, PF
010000 00000011
TMODE
Load W to TMODE register
W→TMODE
None
010000 00000100
RET
Return
Stack→PC
None
010000 00000rrr
CPIO R
Control I/O port register
W→CPIO r
None
010001 1rrrrrrr
STWR R
Store W to register
W→R
None
011000 trrrrrrr
LDR R, t
Load register
R→t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3) ↔
R(4~7)]→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1→t
TF, PF
Z
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P. 6
VER1.1
MDT2005
Instruction Code
Mnemonic
Operands
Function
Operating
Status
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R ﹣W→t
(R+/W+1→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R ﹣1→t
011110 trrrrrrr
DECRSZ R, t Decrement register, skip if zero R ﹣1→t
010010 trrrrrrr
ANDWR R, t
AND W and register
R ∩ W→t
Z
110100 iiiiiiii
ANDWI i
AND W and immediate
i ∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R ∪ W→t
Z
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
i ∪ W→W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R ⊕ W→t
Z
110110 iiiiiiii
XORWI i
Exclu. OR W and immediate
i ⊕ W→W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R→t
Z
010110 trrrrrrr
RRR
R, t
Rotate right register
R(n) →R(n-1), C
→R(7), R(0)→C
C
010101 trrrrrrr
RLR
R, t
Rotate left register
R(n)→r(n+1),C→
R(0), R(7)→C
C
010000 1xxxxxxx
CLRW
Clear working register
0→W
Z
010001 0rrrrrrr
CLRR
Clear register
0→R
Z
0000bb brrrrrrr
BCR
R, b
Bit clear
0→R(b)
None
0010bb brrrrrrr
BSR
R, b
Bit set
1→R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
1000nn nnnnnnnn
LCALL n
Long CALL subroutine
n→PC,
PC+1→Stack
None
1010nn nnnnnnnn
LJUMP n
Long JUMP to address
n→PC
None
110000 nnnnnnnn
CALL
n
Call subroutine
n→PC,
PC+1→Stack
None
110001 iiiiiiii
RTIW
i
Return, place immediate to W
Stack→PC, i→W
None
11001n nnnnnnnn
JUMP
n
JUMP to address
n→PC
None
R
Z
None
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
b
t
0
1
R
C
HC
Z
:
:
:
:
:
:
:
:
Bit position
Target
Working register
General register
General register address
Carry flag
Half carry
Zero flag
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P. 7
VER1.1
MDT2005
Inclu.
Exclu.
AND
:
:
:
Inclusive ‘∪’
Exclusive ‘⊕’
Logic AND ‘∩’
/
x
i
n
:
:
:
:
Complement
Don’t care
Immediate data ( 8 bits )
Immediate address
9. Electrical Characteristics
(A) Operating Voltage & Frequency
Vdd ﹕2.3V ~ 6.3 V
Frequency﹕0 Hz ~ 20 MHz
(B) Input Voltage
@ V dd=5.0 V, Temperature=25 ℃
Vil
Port
Min.
Max.
PA, PB
Vss
1.0 V
RTCC, /MCLR
Vss
1.5V
PA, PB
2.0 V
Vdd
Vih
RTCC, /MCLR
3.5 V
Vdd
*Threshold Voltage :
Port A, Port B V th=1.5V
RTCC, /MCLR V il =1.8 V, V ih =3.4 V (Schmitt Trigger)
(C) Output Voltage﹕
@ V dd=5.0 V, Temperature=25 ℃, the typical value as followings :
PA, PB Port
Ioh=-20.0 mA
Voh=4.0 V
Iol =20.0 mA
Vol =0.5 V
Ioh=-5.0 mA
Voh=4.7 V
Iol =5.0 mA
Vol =0.2 V
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P. 8
VER1.1
MDT2005
(D) Leakage Current
@ V dd=5.0 V, Temperature=25 ℃, the typical value as followings :
Iil
- 0.1µA (Max.)
Iih
+ 0.1µA (Max.)
(E) Sleep Current
@WDT-Disable, Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V
Idd<1.0 µA
Vdd=3.0 V
Idd<1.0 µA
Vdd=4.0 V
Idd=2.0 µA
Vdd=5.0 V
Idd=6.0 µA
Vdd=6.3V
Idd=10.0 µA
@WDT-Enable, Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V
Idd<1.0 µA
Vdd=3.0 V
Idd=3.0 µA
Vdd=4.0 V
Idd=8.0 µA
Vdd=5.0 V
Idd=16.0 µA
Vdd=6.3 V
Idd=34.0 µA
(F) Operating Current
Temperature=25 ℃, the typical value as followings :
(i) OSC Type=RC ; WDT-Enable; @ V dd=5.0 V
Cext. (F)
3P
Rext. (Ohm)
Frequency (Hz)
Current (A)
4.7 K
12.3M
2.1 mA
10.0 K
6.3 M
1.2 mA
47.0 K
1.5 M
508 µA
100.0 K
710 K
385 µA
300.0 K
240 K
320 µA
470.0 K
155 K
310 µA
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P. 9
VER1.1
MDT2005
Cext. (F)
20P
100P
300P
Rext. (Ohm)
Frequency (Hz)
Current (A)
4.7 K
6.2M
1.2 mA
10.0 K
3.1 M
740 µA
47.0 K
740 K
385 µA
100.0 K
340 K
320 µA
300.0 K
115 K
300 µA
470.0 K
74 K
290 µA
4.7 K
1.9 M
560 µA
10.0 K
960 K
420 µA
47.0 K
215 K
310 µA
100.0 K
100 K
300 µA
300.0 K
35 K
285 µA
470.0 K
22 K
280 µA
4.7 K
765 K
400 µA
10.0 K
380 K
330 µA
47.0 K
85 K
285 µA
100.0 K
40 K
280 µA
300.0 K
13.5 K
275 µA
470.0 K
8.5 K
270 µA
(ii) OSC Type=LF (C=20 p); WDT-Disable
Voltage/Frequency
32 K
455 K
1M
Sleep
2.3 V
45 µA
70 µA
X
<1.0 µA
3.0 V
78 µA
115 µA
176 µA
<1.0 µA
4.0 V
135 µA
120 µA
265 µA
2 µA
5.0 V
210 µA
275 µA
375 µA
6 µA
6.3 V
350 µA
420 µA
570 µA
10 µA
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P. 10
VER1.1
MDT2005
(iii) OSC Type=XT (C=10 p); WDT-Enable
Voltage/Frequency
1M
4M
10 M
Sleep
2.1 V
126 µA
255 µA
535 µA
<1.0 µA
3.0 V
240 µA
430 µA
845 µA
2 µA
4.0 V
420 µA
670 µA
1.3 mA
8 µA
5.0 V
705 µA
945 µA
1.78 mA
16 µA
6.3 V
935 µA
1.45 mA
2.55 mA
32 µA
(iv) OSC Type=HF (C=10 p); WDT-Enable
Voltage/Frequency
4M
10 M
20 M
Sleep
<1.0 µA
2.1 V
270µA
555µA
998µA
3.0 V
470 µA
895µA
1.64 mA
4.0 V
740 µA
1.42 mA
2.45 mA
8 µA
5.0 V
1.1 mA
1.96 mA
3.3 mA
16 µA
6.3 V
1.7 mA
2.82 mA
4.7 mA
32 µA
2 µA
(G) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V dd=5.0 V
Vpr≦1.1~1.3 V
Vpr ﹕Vdd (Power Supply)
(H) The basic WDT time-out cycle time
@ V dd=5.0v ,Temperature=25 ℃, the typical value as followings :
Voltage (V)
Basic WDT time-out cycle time (ms)
2.3
26.4
3.0
22.7
4.0
20.1
5.0
18.1
6.3
16.4
(I) MCLRB Filter:@ V dd=5.0v
Wm >1.2us
Wm : Filter pulse width (low) in /MCLR pin.
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P. 11
VER1.1
MDT2005
10. Port A and Port B Equivalent Circuit
Working Register
D
QB
Data I/P
I/O
Control
Latch
I/O Control
CK
Q
Port I/O Pin
D
Data O/P
Latch
Write
CK
Q
Data Bus
D
QB
Read
Data I/P
Latch
Input Resistor
TTL Input Level
CK
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P. 12
VER1.1
MDT2005
11. MCLRB and RTCC Input Equivalent Circuit
R≒1K
MCLRB
Schmitt Trigger
R≒1K
RTCC
Schmitt Trigger
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P. 13
VER1.1
MDT2005
12. Block Diagram
Stack Two Levels
EPROM
512×14 (MDT2005)
RAM
25×8
Port
PA0~PA3
4 bits
Port A
9 or10 bits
9 or 10 bits
Program Counters
14 bits
Instruction
Register
Special Register
D0~D7
OSC1 OSC2
MCLR
Oscillator Circuit
Port B
Instruction
Decoder
Control Circuit
Data 8-bit
Power on Reset
Power Down Reset
Working Register
Status Register
ALU
8-bit Timer/Counter
WDT/OST
Timer
Prescale
RTCC
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P. 14
VER1.1
Port
PB0~PB7
8 bits
MDT2005
13. External Capacitor Selection For Crystal Oscillator
@ V dd=3.0V~5.0 V
Osc. Type
HF
XT
LF
Resonator Freq.
C1
C2
20 MHz
5 pF ~10 pF
10 pF~20 pF
10 MHz
10 pF ~50 pF
20 pF ~100 pF
4 MHz
10 pF ~30 pF
20 pF ~100 pF
10 MHz
10 pF ~30 pF
10 pF ~50 pF
4 MHz
10 pF ~50 pF
10 pF ~100 pF
1 MHz
10 pF ~30 pF
10 pF ~50 pF
1 MHz
5 pF ~10 pF
5 pF ~10 pF
455 K
10 pF ~50 pF
10 pF ~50 pF
32 K
10 pF ~30 pF
20 pF ~50 pF
MDT2005
OSC1
OSC2
C1
C2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range
can be recommended for reference, but the higher capacitance also increases the start-up time.
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P. 15
VER1.1
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