Mitsubishi MH4S64DBKG-8L 268435456-bit (4194304 - word by 64-bit)synchronousdram Datasheet

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH4S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
Utilizes industry s t andard 4M x 16 Sy nchronous DRAMs
TSOP and industry s t andard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
FEATURES
Burst length- 1/2/4/8/Full Page(programmable)
Frequency
CLK Access Time
Burst type- sequential / interleave(programmable)
(Component SDRAM)
-7,-7L
100MHz
6.0ns(CL=3)
Column access - random
-8,-8L
100MHz
6.0ns(CL=3)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
PC100 compliant
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
MIT-DS-0338-0.0
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2
143
144
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
PIN
Number
Front side
Pin Name
PIN
Number
Back side
Pin Name
1
Vss
2
Vss
73
NC
74
CLK1
3
5
DQ0
DQ1
4
6
DQ32
DQ33
75
Vss
76
Vss
77
NC
78
NC
NC
7
9
DQ2
DQ3
8
10
DQ34
DQ35
79
80
NC
81
Vcc
82
Vcc
11
13
Vcc
DQ4
12
14
Vcc
DQ36
83
DQ16
84
DQ48
85
DQ17
86
DQ49
15
DQ5
16
DQ37
87
DQ18
88
DQ50
17
DQ6
18
DQ38
89
DQ19
90
DQ51
19
21
DQ7
Vss
20
DQ39
91
Vss
92
Vss
22
Vss
93
DQ20
94
DQ52
23
DQMB0
25
DQMB1
24
DQMB4
95
DQ21
96
DQ53
26
DQMB5
97
DQ22
98
DQ54
Vcc
99
DQ23
100
DQ55
Vcc
27
Vcc
29
A0
30
A3
101
102
Vcc
31
A1
32
A4
103
A6
104
A7
33
A2
34
A5
105
A8
106
BA0
35
Vss
36
Vss
107
Vss
108
Vss
37
DQ8
38
DQ40
109
A9
110
BA1
39
DQ9
40
DQ41
111
A10
112
A11
41
DQ10
42
DQ42
113
Vcc
114
43
DQ11
44
DQ43
115
DQMB2
116
DQMB6
45
Vcc
46
Vcc
117
DQMB3
118
DQMB7
47
DQ12
48
DQ44
119
Vss
120
Vss
49
DQ13
50
DQ45
121
DQ24
122
DQ56
51
DQ14
52
DQ46
123
DQ25
124
DQ57
53
DQ15
54
DQ47
125
DQ26
126
DQ58
55
Vss
56
Vss
127
DQ27
128
DQ59
57
NC
58
NC
129
Vcc
130
Vcc
59
NC
60
NC
131
DQ28
132
DQ60
61
CLK0
62
CKE0
133
DQ29
134
DQ61
63
Vcc
64
Vcc
135
DQ30
136
DQ62
65
/RAS
66
/CAS
137
DQ31
138
DQ63
67
/WE
68
CKE1
139
Vss
140
Vss
69
/S0
70
NC
141
SDA
142
SCL
71
/S1
72
NC
143
Vcc
144
Vcc
28
Vcc
NC = No Connection
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
DQML /CS
DQMB1
DQML /CS
DQMB3
DQMU
10Ω
I/O 0
I/O 1 D3
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB7
DQMU
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D0 - D3
BA0,BA1,A<11:0>
D0 - D3
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CLK1
D0 - D3
D0 - D3
D0 - D3
D0 - D3
SERIAL PD
SCL
Vcc
MIT-DS-0338-0.0
DQML /CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
CLK0
CKE0
/RAS
/CAS
/WE
Vss
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB6
I/O 0
I/O 1 D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMU
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1 D2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB5
DQMU
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML /CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1 D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
SDA
D0 - D3
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
08
2
Total # bytes of SPD memory device
Fundamental memory type
256 Bytes
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A7
08
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
10ns
A0
6ns
60
1
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
00
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x16
10
14
Error Checking SDRAM data width
N/A
00
15
Minimum Clock Delay,Back to Back Random Column Addresses
1
01
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
2/3
06
19
CS# Latency
0
01
1/2/4/8/Full page
8F
20
Write Latency
0
01
21
SDRAM Module Attributes
non-buffered,non-registered
00
22
SDRAM Device Attributes:General
23
24
Precharge All,Auto precharge
0E
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
-7,7L
10ns
-8,8L
13ns
A0
D0
SDRAM Access form Clock(2nd highest CAS latency)
-7,7L
6ns
60
tAC for CL=2
-8,8L
7ns
70
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
26
27
SDRAM Access form Clock(3rd highest CAS latency)
N/A
00
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
29
RAS to CAS Delay Min
20ns
20ns
14
30
Active to Precharge Min
50ns
32
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31
32MByte
08
32
Command and Address signal input setup time
2ns
20
33
Command and Address signal input hold time
1ns
10
34
35
Data signal input setup time
Data signal input hold time
2ns
20
36-61
Density of each bank on module
Superset Information (may be used in future)
62
SPD Revision
63
Checksum for bytes 0-62
1ns
10
option
00
rev 1.2A
12
Check sum for -7,7L
04
Check sum for -8,-8L
44
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
73-90
Manufactures Part Number
91-92
93-94
95-98
MH4S64DBKG-7
MH8S64DBKG-7L
MH8S64DBKG-8
4D483453363444424B472D38202020202020
MH8S64DBKG-8L
4D483453363444424B472D384C2020202020
PCB revision
Manufacturing date
year/week code
yyww
serial number
ssssssss
option
00
100MHz
64
Assembly Serial Number
Manufacture Specific Data
126
Intetl specification frequency
-7,7L-8,8L
127
Intel specification CAS# Latency support
-7,7L
Unused storage locations
rrrr
8F
-8,8L
MIT-DS-0338-0.0
4D483453363444424B472D37202020202020
Revision Code
99-125
128+
04
4D483453363444424B472D374C2020202020
8D
open
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0
Input
Chip Select: When /S is high,any command means
No Operation.
Input
Combination of /RAS,/CAS,/WE defines basic commands.
Input
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
CLK0
/RAS,/CAS,/WE
A0-11
BA0,1
DQ0-63
DQMB0-7
Vdd,Vss
Input/Output Data In and Data out are referenced to the rising edge
of CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input
Serial clock for serial PD
SDA
Output
Serial data for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH4S64DBKG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Ref resh Option @ref resh
command
Precharge Option @precharge or read/write
command
A10
def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CKE CKE
n-1
n
/RAS /CAS
A10 A0-9
MNEMONIC
Deselect
No Operation
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
PREA
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
H
X
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
X
L
V
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
L
H
L
L
V
X
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
X
L
V
Column Address Entry
& Read with Auto
Precharge
READA
H
X
L
H
L
H
V
X
H
V
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H
H
L
L
H
H
H
L
H
H
X
X
L
L
H
L
L
L
L
L
X
H
H
L
L
L
X
H
H
L
H
H
X
H
L
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V*1
Row Adress Entry &
Bank Activate
/S
/WE BA0,1
A11
COMMAND
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
/S
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
L
L
L
H
BA,A10
X
PRE/PREA
REFA
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
Bank Active/ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
ROW ACT IVE
READ
/RAS /CAS
/WE
Address
Command
Current State
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Action
READ/WRITE ILLEGAL*2
MRS
READ/READA
Bank Active,Latch RA
NOP*4
Auto-Refresh*5
Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
Begin Write,Latch CA,
WRITEA
Determine Auto-Precharge
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
MIT-DS-0338-0.0
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
/RAS /CAS
Command
Action
X
DESEL
NOP(Continue Burst to END)
H
X
NOP
NOP(Continue Burst to END)
L
BA
TBST
Terminate Burst
Current State
/S
/WE
WRITE
H
X
X
X
L
H
H
L
H
H
Address
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin Read,Determine AutoPrecharge*3
L
H
L
L
BA,CA,A10
WRITE/
WRITEA
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
H
X
X
X
X
AUTO
L
H
H
H
PRECHARGE
L
H
H
L
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
WRITE with
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUTO
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
H
H
L
TBST
ILLEGAL
L
H
L
H
BA
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
REFA
ILLEGAL
L
Op-Code,
Mode-Add
MRS
ILLEGAL
L
MIT-DS-0338-0.0
L
L
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
DESEL
NOP(Continue Burst to END)
X
NOP
NOP(Continue Burst to END)
BA
TBST
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
Op-Code,
Mode-Add
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
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ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
/S
PRE -
H
X
X
X
X
DESEL
NOP(Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
MIT-DS-0338-0.0
/RAS /CAS
/WE
Address
Command
Current State
Action
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
( 11 / 55 )
REFA
ILLEGAL
MRS
ILLEGAL
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
Command
Action
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CK
n-1
CK
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
Action
/WE
Add
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0338-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
IDLE
AUTO
REFRESH
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
READA
WRITEA
CKEL
WRITE
SUSPEND
READ
READ
WRITE
WRITE
CKEL
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
SUSPEND
POWER
APPLIED
READ
SUSPEND
CKEL
PRE
WRITEA
CKEH
POWER
ON
PRE
PRE
READA
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0338-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
BA0 BA1 A11 A10 A9
A8
A7 A6
A5
A4 A3
A2
A1 A0
/RAS
/CAS
0
0
0
0
WM
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
CL
LATENCY
MODE
/CAS LATENCY
000
001
R
R
0
0
1
1
1
1
2
3
R
R
R
R
WRITE
MODE
MIT-DS-0338-0.0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BURST
SINGLE BIT
BURST
LENGTH
BURST
TYPE
V
BL
BT= 0
BT= 1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
R
1
2
4
8
R
101
110
111
R
R
FP
R
R
R
0
0
0
0
1
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
ACT
Command
READ
tRCD
Address
X
Y
CL=2
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
CL=2
CL=3
DQ
Q3
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burs t
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
READ
X
Y
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1 Q2
Q3
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
BL=1
BL=2
BL=4
m=255
MIT-DS-0338-0.0
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ELECTRIC
( 16 / 55 )
BL=8
Q8
Qm Q0
Q1
BL=FP
Full Page counter rolls over
and continues to count.
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
D0
Q3
Burst Length
D1
D2
D3
Burst Length
Burst Type
Initial Address
BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command
ACT
ACT READ
tRRD
A0-9,11
Xa
PRE
ACT
tRAS
Xb
tRP
Y
Xb
tRCD
A10
Xa
Xb
0
BA0,1
00
01
00
DQ
1
Xb
01
Qa0
Qa1
Qa2
Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active
bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case
of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the autoprecharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same
bank is inhibited till the internal precharge is complete. The internal precharge start timing
depends on /CAD Latency. The next ACT command can be issued after tRP from the internal
precharge timing.
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CK
Command
ACT
READ ACT
READ PRE
tRCD
A0-9,11
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
BA0,1
0
0
1
1
0
Qa1
Qa2
DQ
Qa0
/CAS latency
Qa3
Qb0
Qb1
Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
Command
ACT
READ
ACT
tRCD
A0-9,11
tRP
Xa
Y
Xa
A10
Xa
1
Xa
BA0,1
0
0
0
DQ
Qa0
Qa1
Qa2
Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK
Command
CL=3
DQ
CL=2
DQ
ACT
READ
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal Precharge Start Timing
MIT-DS-0338-0.0
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A WRITE command may be applied to any active
bank, so the row precharge time(tRP) can be hidden behind continuous input data (in case
of BL=8) by interleaving the dual banks. From the last input data to the PRE command, the
write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same
bank is inhibited till the internal precharge is complete. The internal precharge begins at
tWR after the last input data cycle. The next ACT command can be issued after tRP from the
internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CK
Command
ACT
Write
ACT
tRCD
Write
PRE
tRCD
A0-9,11
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
0
0
1
1
0
Da0
Da1
Db0
Db1
tWR
BA0,1
DQ
Da2
Da3
Db2
Db3
Burst Length
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRCD
tRP
A0-9,11
Xa
Y
Xa
A10
Xa
1
Xa
0
0
BA0,1
0
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge begins
MIT-DS-0338-0.0
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in
the same cycle as a write command set.(The latency of data input is 0.) The
burst length can be set to 1,2,4,8,and full-page,like burst read operations .
tRCD
CK
Command
ACT
READ
X
Y
Address
DQ
Q0
DQ
Q0
Q1
DQ
Q0
Q1 Q2
Q3
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
DQ
Q0
Q1 Q2
Q3
Q4 Q5
Q6
Q7
BL=1
BL=2
BL=4
m=255
BL=8
Q8
Qm Q0
BL=FP
Q1
Full Page counter rolls over
and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1 at MRS.In a single write
operation,data is written only to the column address specified by the write
command set cycle without regard to the burst length setting.(The latency of data
input is 0.)
CK
Command
READ
ACT
tRCD
Address
DQ
MIT-DS-0338-0.0
X
Y
Q0
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank.
MH8S64BBKG allows random column access. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
READ READ
READ
READ
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
0
0
1
0
DQ
Qai0
Qaj0
Qaj1 Qbk0 Qbk1 Qbk2
Qal0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
A0-9,11
READ
Write
Yi
Yj
A10
0
0
BA0,1
0
0
DQMB0-7
Q
D
Qai0
Daj0
Daj1
Daj2
DQM control
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Daj3
Write control
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank.
Read to PRE interval is minimum 1 CK. A PRE command disables the data output,
depending on the /CAS Latency. The figure below shows examples, when the dataout is
terminated.
Read Interrupted by Precharge (BL=4)
CK
Command
PRE
READ
DQ
Q0
Q1
Q0
Q1
Q2
Q3
CL=3
Command
READ
PRE
DQ
Command
PRE
READ
DQ
Q0
Q1
Q2
Q3
CL=2
Command
DQ
MIT-DS-0338-0.0
READ
PRE
Q0
Q1
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Preliminary Spec.
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Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST
is mainly used to interrupt FP bursts.The figure below show examples, of how the output
data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
Command
READ
TBST
DQ
Command
Q0
READ
Q1
Q2
Q1
Q2
Q3
TBST
CL=3
DQ
Command
Q0
READ TBST
Q0
DQ
Command
TBST
READ
DQ
Command
CL=2
DQ
Q1
Q2
Q3
TBST
READ
DQ
Command
MIT-DS-0338-0.0
Q0
Q0
Q1
Q2
READ TBST
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9,11
Write Write
Write
Write
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
0
0
1
0
DQ
Dai0
Daj0
Daj1
Dbk0 Dbk1 Dbk2 Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9,11
Write READ
Write
READ
Yi
Yj
Yk
Yl
A10
0
0
0
0
BA0,1
0
0
0
1
DQMB0-7
DQ
MIT-DS-0338-0.0
Dai0
Qaj0
Qaj1
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Dak0 Dak1
Qbl0
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required
between the last input data and the next PRE, 3rd data should be masked with
DQMB0-7 shown as below.
Write Interrupted by Precharge (BL=4)
CK
Command
Write
PRE
tWR
A0-9,11
ACT
tRP
Yi
Xb
A10
0
0
Xb
BA0,1
0
0
0
DQMB0-7
DQ
Dai0
Dai1
This data should be masked to satisf y tWR requirement.
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active. The figure below
shows the case 3 words of data are written. Random column access is allowed.
WRITE to TERM interval is minimum 1 CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
A0-9,11
Write
TERM
Yi
A10
0
BA0,1
0
DQMB0-7
DQ
MIT-DS-0338-0.0
Dai0
Dai1
Dai2
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks
must be in the idle state. Additional commands must not be supplied to the device
before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-11
BA0,1
Auto Refresh on Bank 0
MIT-DS-0338-0.0
Auto Refresh on Bank 1
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input (but asynchronous), all other inputs including CK0 are disabled and ignored,
and power consumption due to synchronous inputs is saved. To exit the selfrefresh, supplying stable CK0 inputs, asserting DESEL or NOP command and then
asserting CKE(REFSX). After tRC from REFSX both banks are in the idle state and a
new command can be issued after tRC, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
X
BA0,1
0
Self Refresh Entry
MIT-DS-0338-0.0
Self Refresh Exit
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minimum tRC
for recovery
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, but a command at the following cycle is ignored.
CK
(ext.CLK)
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Activ e Power Down
CKE
Command
NOP NOP NOP NOP NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
DQ
MIT-DS-0338-0.0
Write
D0
READ
D1
D2
D3
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Q0
Q1
Q2
Q3
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
READ
Write
DQMB0-7
DQ
D0
D2
D3
Q0
masked by DQM=H
MIT-DS-0338-0.0
Q1
Q3
disabled by DQM=H
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
4
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
Ta=25°C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
Vdd+0.3
V
-0.3
0.8
V
VIL
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
Limits(max.)
Unit
CI(A)
Input Capacitance, address pin
VI = 1.4V
30
pF
CI(C)
Input Capacitance, control pin
30
pF
CI(K)
Input Capacitance, CK pin
35
pF
CI/O
Input Capacitance, I/O pin
22
pF
MIT-DS-0338-0.0
f=1MHz
Vi=200mVrms
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
operating current
one bank activ e (discrete)
Icc3N
Test Condition
tRC=min.tCLK=min, BL=1, CL=3
Icc1
precharge stanby current Icc2N
in non power-down mode Icc2NS
active stanby current
Icc3P
in power-down mode
Icc3PS
active stanby current
in non power-down mode
Limits
(max)
CKE=/CS=VIHmin,tCLK=15ns(Note) , VIH>Vcc-0.2V, VIL<0.2V
CKE=VIHmin,CLK=VILmax(fixed), VIH>Vcc-0.2V, VIL<0.2V
CKE=VILmax,tCLK=15ns
CKE=CLK=VILmax(fixed)
CKE=/CS=VIHmin,tCLK=15ns
burst current
auto-refresh current
Icc3NS CKE=VIHmin,CLK=VILmax(f ixed)
tCLK=min, BL=4, CL=3,All banks activ e(discerte)
Icc4
tRC=min,
tCLK=min
Icc5
self-refresh current
Icc6
one bank activ e (discrete)
-7, -8
-7L,-8L
CKE <0.2V
-7, -7L
-8, -8L
Unit
320
mA
80
60
mA
mA
8
mA
4
mA
120
mA
100
mA
320
440
4
mA
mA
mA
2
mA
Note:Input signals are changed one time during 30ns.
Note:All other pins not under test are 0V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
VOH(DC)
VOL(DC)
IOZ
VOH(AC)
Ii
VOL(AC)
MIT-DS-0338-0.0
Limits
Unit
Min. Max.
High-Level Output Voltage(DC) IOH=-2mA
2.4
V
Low-Level Output Voltage(DC) IOL=2mA
0.4
V
Off-stare
Output
Current
floating VO=0
High-Level
Output
Voltage(AC) Q
CL=50pF,
IOH=- ~ Vdd -102 10 uA
V
2mA ~ Vdd+0.3V
Input
Current
uA
Low-Level
Output Voltage(AC) VIH=0
CL=50pF,
IOL=2mA
0.8
V
-20
20
Parameter
Test Condition
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
AC TIM ING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-7,-7L
-8,-8L
Min. Max. Min. Max.
Symbol Parameter
tCLK
CK cycle time
CL=2
10
10
3
3
1
10
2
1
70
20
50 100K
20
20
20
10
10
64
CL=3
tCH
CK High pulse width
tCL
CK Low pilse width
tT
Transition time of CK
tIS
Input Setup time(all inputs)
tIH
Input Hold time(all inputs)
tRC
Row cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP
Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
tSRX Self Refresh Exit time
tREF Refresh Interval time
Unit Note
ns
13
10
ns
3
ns
3
ns
1
10 ns
2
ns
ns
1
70
ns
20
ns
50 100K ns
20
ns
20
ns
20
ns
10
ns
10
ns
64 ms
1
1
1
1
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
CK
1.4V
Any AC timing is
referenced to the input
Signal
1.4V
signal crossing
through 1.4V.
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.165V, Vss = 0V, unless otherwise noted)
Limits
-7,-7L
-8,-8L
Unit
Min. Max. Min. Max.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
Access time from CK
CL=2
6
7
ns
CL=3
6
6
ns
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
3
3
ns
0
0
ns
3
6
3
6
ns
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
V TT =1.4V
CK
1.4V
50Ω
DQ
1.4V
V OUT
50pF
Output Timing
Measurement
Reference Point
CK
1.4V
DQ
1.4V
tAC
MIT-DS-0338-0.0
tOH
tOHZ
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Preliminary Spec.
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
Y
A0-7
X
A10
X
X
A8,9,11
X
X
BA0,1
0
0
D0
DQ
ACT#0
X
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-7
X
X
A10
X
A8,9,11
BA0,1
Y
X
X
X
X
X
X
X
X
X
0
1
0
D0
DQ
ACT#0
Y
D0
WRITE#0
ACT#1
D0
D0
1
0
D1
D1
0
D1
PRE#0
WRITE#1
D1
1
2
Y
0
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRP
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-7
X
A10
X
X
A8,9,11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-7
X
X
A10
X
A8,9,11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
CL=3
ACT#0
READ#0
ACT#1
0
1
2
Q1
Q1
Q1
0
CL=3
Q0
DQ
0
Y
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-7
X
X
A10
X
X
X
X
A8,9,11
X
X
X
X
BA0,1
0
1
Y
0
D0
DQ
ACT#0
ACT#1
Y
X
1
D0
D0
D0
WRITE#0 with
AutoPrecharge
D1
D1
D1
Y
X
0
0
1
D1
D0
D0
ACT#0
WRITE#1 with
AutoPrecharge
Y
1
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
Y
Y
Y
A0-7
X
X
A10
X
X
X
X
A8,9,11
X
X
X
X
BA0,1
0
1
0
1
CL=3
ACT#0
ACT#1
0
0
CL=3
Q0
DQ
X
READ#0 with
Auto-Precharge
Q0
Q0
X
Y
1
1
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-7
X
X
A10
X
X
A8,9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
WRITE#0
D1
D1
D0
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-7
X
X
A10
X
X
A8,9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
CL=3
Q0
Q0
Q0
Q0
READ#0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tCCD
tRCD
/CAS
/WE
CKE
DQM
A0-7
X
X
A10
X
X
A8,9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-7
X
X
A10
X
X
X
X
0
1
A8,9,11
BA0,1
DQ
ACT#0
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
Y
A0-7
X
X
A10
X
X
X
A8,9,11
X
X
X
0
1
BA0,1
0
D0
DQ
Y
D0
ACT#0
WRITE#0
ACT#1
D0
D0
X
1
0
D1
D1
1
1
1
D1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
Y
ACT#1
D1
D1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
Y
A0-7
X
X
A10
X
X
X
X
X
X
0
1
A8,9,11
BA0,1
Y
0
Q0
DQ
ACT#0
READ#0
ACT#1
X
1
0
1
Q0
Q0
Q0
1
Q1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-7
X
Y
X
A10
X
A8,9,11
0
BA0,1
0
0
D0
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-7
X
A10
X
A8,9,11
X
0
BA0,1
Y
0
D0
DQ
D0
D0
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-7
X
A10
X
A8,9,11
X
0
BA0,1
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-7
X
A10
X
A8,9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
masked
D0
WRITE#0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-7
X
A10
X
Y
Y
Y
0
0
0
X
A8,9,11
0
BA0,1
masked
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
READ#0
masked
Q0
Q0
Q0
READ#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-7
X
A10
X
A8,9,11
X
BA0,1
0
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-7
X
A10
X
A8,9,11
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
D0
D0
D0
WRITE#0
READ#0
CLK suspended
Q0
Q0
Q0
Q0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0338-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
4.00
MIT-DS-0338-0.0
6.00
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
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