Mitsubishi MH8V64AWZJ-5 Fast page mode 536870912 - bit ( 8388608 - word by 64 - bit ) dynamic ram Datasheet

MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION
The MH8V64AWZJ is 8388608-word x 64-bit dynamic
ram module. This consist of eight industry standard 8M x
8 dynamic RAMs in SOJ and one industry standard
EEPROM is TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
85pin
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
FEATURES
Type name
/RAS
/CAS Address /OE
access access access access
time
time
time
time
Cycle
Power
time
dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
(typ.W)
MH8V64AWZJ-5
50
13
25
13
90
2.40
MH8V64AWZJ-6
60
15
30
15
110
2.00
Utilizes industry standard 8M x 8 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
8.64mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V64AWZJ -5 . . . . . . . . . . . . . . . . . . 2.88W(Max)
MH8V64AWZJ -6 . . . . . . . . . . . . . . . . . . 2.60W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 8) decoupling capacitors
4096 refresh cycle every 64ms
Fast-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
JEDEC standard pin configuration and SPD
Gold plating contact pads
FRONT SIDE
BACK SIDE
Row Address
A0 ~ A12
Column Address A0 ~ A9
APPLICATION
Main memory unit for computers , Microcomputer memory
MIT-DS-0107-0.5
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ELECTRIC
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25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
/WE0
/CAS0
/CAS1
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
A10
A12
Vcc
Vcc
DU
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
/OE2
/RAS2
/CAS2
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Vss
DQ32
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DU
NC
/CAS6
/CAS3
/WE2
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
DU
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
NC
NC
NC
SDA
SCL
Vcc
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
DU
/CAS4
/CAS5
NC
DU
Vss
A1
A3
A5
A7
A9
A11
NC
Vcc
DU
DU
/CAS7
DU
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
DU
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
SA0
SA1
SA2
Vcc
NC: No Connect
DU: Don't Use
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25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/RAS2
/WE0
/WE2
/OE0
/OE2
/OE
/W
/RAS
M5M467800AJ
/CAS0
D0
/OE
/CAS1
/W
/RAS
M5M467800AJ
D1
/OE
/W
/RAS
/CAS2
M5M467800AJ
D3
/OE
/W
/RAS
/CAS3
M5M467800AJ
D4
A0~A12
Vcc
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/OE
/W
/RAS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
/RAS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/RAS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/RAS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M5M467800AJ
/CAS4
D5
/OE
/CAS5
/W
M5M467800AJ
D6
/OE
/CAS6
/W
M5M467800AJ
D7
/OE
/W
/CAS7
M5M467800AJ
D8
D0~D8
SCL
C0.~C
. .8
SDA
A0 A1 A2
D0~D8
Vss
MIT-DS-0107-0.5
EEPROM
SA0 SA1 SA2
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Serial Presence Detect TABLE
Bytes
Function described
SPD entry data
SPD DATA entry(Hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
FPM DRAM
01
3
# Row Addresses on this assembly
A0-A12
0D
4
# Column Addresses on this assembly
A0-A9
0A
5
# Module Banks on this assembly
1bank
01
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
3.3V LVTTL
02
9
RAS# access time of this assembly
10
CAS# access time of this assembly
-5
50ns
32
-6
60ns
3C
-5
13ns
0D
-6
15ns
0F
11
DIMM Configuration type (Non-parity,Parity,ECC)
non parity
00
12
Refresh Rate/Type
N/R(15.625uS)
00
13
DRAM width,Primary DRAM
x8
08
14
Error Checking DRAM data width
N/A
00
15-31
Reserved for future offerings
open
00
32-61
Superset Memory type(may be used in future)
open
00
62
SPD Data Revision Code
Rev 1
01
63
Checksum for bytes 0-62
Check sum for -5
2B
Check sum for -6
37
64-71
Manufacturers JEDEC ID code per JEP-106
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufacturer's Part Number
MH8V64AWZJ-5
4D483856363441575A4A2D352D35202020202020
91-92
Revision Code
MH8V64AWZJ-6
4D483856363441575A4A2D362D36202020202020
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yy/ww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacturer Specific Data
open
00
126-127
Reserved
open
00
128-255
Open User Free-Form area not defined
open
00
MIT-DS-0107-0.5
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ELECTRIC
( 4 / 20 )
25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
FUNCTION
The MH8V64AWZJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Fast page mode, /RASonly refresh, and delayed-write. The input conditions for
each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/CAS before /RAS refresh
Standby
Inputs
/RAS
ACT
ACT
ACT
ACT
ACT
NAC
/CAS
ACT
ACT
ACT
ACT
ACT
DNC
/W
NAC
ACT
ACT
ACT
NAC
DNC
Input/Output
/OE
ACT
DNC
DNC
ACT
DNC
DNC
Row Column
address address
APD
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
Input
OPN
VLD
VLD
VLD
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
OPN
Refresh
Remark
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
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ELECTRIC
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25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc
Supply voltage
VI
VO
IO
Pd
Topr
Tstg
Input Voltage
Output Voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to Vss
Ta=25°C
Vcc
Vss
VIH
VIL
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Unit
V
V
V
mA
W
°C
°C
(Ta=0~70°C, unless otherwise noted) (Note 1)
RECOMMENDED OPERATING CONDITIONS
Symbol
Ratings
-0.5~ 4.6
-0.5~ Vcc+0.5
-0.5~ Vcc+0.5
50
8
0~70
-40~125
Min
3.0
0
2.0
-0.3
Limits
Nom Max
3.3
3.6
0
0
Unit
Vcc+0.3
V
V
V
0.8
V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
Parameter
Test conditions
VOH
VOL
IOZ
II
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /CAS)
Input current (/CAS)
I I (CAS)
Average supply
ICC1 (AV) current
from Vcc operating
(Note 3,4,5)
IOH=-2.0mA
IOL=2.0mA
Q floating 0V ≤VOUT≤ Vcc
0V≤VIN≤Vcc+0.3, Other input pins=0V
0V≤VIN≤Vcc+0.3, Other input pins=0V
-5
-6
ICC2
Supply current from Vcc , stand-by
-5
ICC4(AV)
Average supply current
from Vcc
Fast-Page-Mode
Average supply current from
Vcc
/CAS before /RAS refresh
(Note 3,5)
mode
-5
(Note 3,4,5)
ICC6(AV)
-6
-6
Min
2.4
0
-10
-80
-10
Limits
Max
Typ
Vcc
0.4
10
80
10
/RAS, /CAS cycling
tRC=tWC=min.
output open
800
Unit
V
V
uA
uA
uA
mA
720
/RAS=/CAS =VIH, output open
8
4
/RAS=/CAS=WE≥Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
820
mA
mA
640
/CAS before /RAS refresh cycling
tRC=min.
output open
1040
mA
960
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE
Symbol
CI (/CAS)
CI
C(DQ)
C(SCL)
C(SDA)
C(SA0~3)
MIT-DS-0107-0.5
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
Parameter
Input capacitance, /CAS input
Input capacitance, except /CAS input
Input/Output capacitance,DATA
Input capacitance, SPD clock
Input/Output capacitance,SPD DATA
Input capacitance, SPD address
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
Min
Limits
Typ
Max
22
75
22
7
7
7
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ELECTRIC
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Unit
pF
pF
pF
pF
pF
pF
25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Limits
Symbol
Parameter
-5
Min
tCAC
tRAC
tAA
tCPA
tOEA
tCLZ
tOFF
tOEZ
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Access time from /OE
Output low impedance time /CAS low
Output disable time after /CAS high
Output disable time after /OE high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 7)
5
0
0
(Note 12)
(Note 12)
Unit
-6
Max
13
50
25
30
13
Min
Max
15
60
30
35
15
5
0
0
13
13
15
15
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF.The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD ≥ tRCD(max), tASC ≥ tASC(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOFF (max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ I ± 10uA I ) and is not reference to
VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
Symbol
-5
Parameter
Min
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
(Note15)
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low (Note16)
Row address setup time before /RAS low
Column address setup time before /CAS low(Note17)
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
(Note18)
Delay time, data to /OE low
(Note18)
Delay time, /CAS high to data
(Note19)
Delay time, /OE high to data
(Note19)
Transition time
(Note20)
-6
Max
Min
64
30
18
5
0
10
13
0
0
8
13
0
0
13
13
1
37
25
5
50
Unit
Max
64
40
20
10
0
10
15
0
0
10
15
0
0
15
15
1
45
30
10
50
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics are
2.0V and 0.8V respectively
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tT + tASC(min) .
16: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tOCH
tORH
Parameter
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
-5
(Note 21)
(Note 21)
/CAS hold time after /OE low
/RAS hold time after /OE low
Min
90
50
15
50
15
0
0
10
25
13
13
-6
Max
10000
10000
Min
110
60
15
60
15
0
0
10
30
15
15
Unit
Max
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
MIT-DS-0107-0.5
Parameter
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
(Note 23)
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after W low
Write pulse width
Data setup time before /CAS low or W low
Data hold time after /CAS low or W low
/OE hold time after /W low
Min
90
50
15
50
15
0
10
15
15
10
0
10
13
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ELECTRIC
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Unit
-6
-5
Max
10000
10000
Min
110
60
15
60
15
0
10
15
15
10
0
10
15
Max
10000
10000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/CAS hole time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /W loe
Data hold time after /W low
tOEH
/OE hold time after /W low
-5
(Note22)
(Note23)
(Note23)
(Note23)
Min
130
85
50
85
50
0
30
65
40
15
15
10
0
10
Unit
-6
Max
Min
150
95
50
95
50
0
30
75
45
10000
10000
Max
10000
10000
15
15
10
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Fast page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is
satisfied,the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)
Limits
Symbol
Parameter
tPC
tPRWC
Fast page mode read/write cycle time
tRAS
tCP
tCPRH
tCPWD
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
Fast page mode read write/read modify write cycle time
(Note25)
(Note26)
(Note23)
Max
Min
35
70
85
5
30
30
Unit
-6
-5
51200
10
Max
Min
40
75
100
10
35
35
51200
15
ns
ns
ns
ns
ns
ns
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.
25: tRAS(min) is specified as two cycles of /CAS input are performed.
26: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 27)
Limits
Symbol
tCSR
tCHR
tRSR
tRHR
Parameter
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
-5
Min
5
10
10
10
Unit
-6
Max
Min
10
10
10
10
Max
ns
ns
ns
ns
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
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MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Timing Diagrams
Read Cycle
(Note 28)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
VIH
Address
tRAD
tRAL
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
tCPN
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tRRH
tRCH
tRCS
VIH
W
VIL
tDZC
DQ
(INPUTS)
tCDD
VIH
Hi-Z
VIL
tCAC
tAA
tOFF
tCLZ
DQ
(OUTPUTS)
VOH
DATA VALID
Hi-Z
Hi-Z
VOL
tRAC
tOEZ
tDZO
tOEA
tOCH
tODD
VIH
OE
VIL
tORH
Note 28
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Write Cycle (Early write)
tWC
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
CAS
tRCD
tRSH
tCAS
tRPC
tCRP
VIH
VIL
tASR
Address
VIH
tASR
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tWCS
W
tWCH
VIH
VIL
tDS
DQ
(INPUTS)
VIH
tDH
DATA VALID
VIL
DQ
(OUTPUTS)
VOH
Hi-Z
VOL
OE
VIH
VIL
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tASR
Address
VIH
tRAH
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tCWL
tRWL
tWP
tRCS
VIH
W
VIL
tWCH
tDZC
DQ
(INPUTS)
VIH
tDS
tDH
DATA
VALID
Hi-Z
VIL
tCLZ
DQ
(OUTPUTS)
VOH
Hi-Z
Hi-Z
VOL
tDZO
tOEH
tOEZ
tODD
OE
VIH
VIL
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tCRP
tRPC
tRSH
tCAS
tCRP
VIH
CAS
VIL
tRAD
tASR
Address
VIH
tRAH
tCAH
tASC
ROW
ADDRESS
COLUMN
ADDRESS
VIL
ROW
ADDRESS
tAWD
tCWD
tRWD
tRCS
W
tASR
tCWL
tRWL
tWP
VIH
VIL
tDH
tDS
tDZC
DQ
(INPUTS)
VIH
DATA VALID
Hi-Z
VIL
tCAC
tAA
tCLZ
DQ
(OUTPUTS)
VOH
DATA
VALID
Hi-Z
VOL
tODD
tDZO
OE
Hi-Z
tRAC
tOEA
tOEZ
tOEH
VIH
VIL
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRP
tRC
tRAS
tRAS
tRP
VIH
RAS
VIL
tRPC
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH
CAS
VIL
tCPN
tASR
Address
VIH
ROW
ADDRESS
COLUMN
ADDRESS
VIL
tRCH tRSR
tRHR
tRSR
tRHR
tRCS
VIH
W
VIL
DQ
(INPUTS)
VIH
VIL
tOFF
DQ
(OUTPUTS)
VOH
Hi-Z
VOL
tOEZ
VIH
OE
VIL
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Preliminary Spec.
Specifications subject to
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MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tCRP
tRCD
tRSH
tCHR
VIH
CAS
VIL
tRAD
tASR
VIH
Address
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tRCS
tRRH
tRAL
VIH
W
VIL
tDZC
DQ
(INPUTS)
tCDD
VIH
Hi-Z
VIL
tCAC
tAA
tCLZ
DQ
(OUTPUTS)
tOFF
VOH
Hi-Z
Hi-Z
DATA VALID
VOL
tRAC
tDZO
tOEA
tORH
tOEZ
tODD
VIL
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
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MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tPC
tRCD
tCAS
tCP
tCAS
tRSH
tCAS
tCP
VIH
CAS
VIL
tCPRH
tRAD
tASR
Address
VIH
tRAH
tCAH
tASC
ROW
ADDRESS
tASC
COLUMN-1
tCAH
tASC
COLUMN-2
tCAH
tASR
ROW
ADDRESS
COLUMN-3
VIL
tRAL
tRCS
tRCS tRCH
tRCH
tRRH
tRCS
tRCH
VIH
W
VIL
tDZC
DQ
(INPUTS)
tDZC
tDZC
VIH
Hi-Z
VIL
Hi-Z
tCAC
tOFF
tCAC
tAA
VOH
tCAC
tOFF
tAA
tCLZ
tCLZ
DATA
VALID-1
Hi-Z
tOFF
tAA
tCLZ
DQ
(OUTPUTS)
tCDD
DATA
VALID-2
DATA
VALID-3
VOL
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
tCPA
tOEA
tOCH
tOEZ
tOEA
tOCH
tOEZ
VIL
OE
VIH
tDZO
tODD
MIT-DS-0107-0.5
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tODD
tDZO
tODD
tORH
25/Feb./1997
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tPC
tCAS
tCP
tCAS
tRSH
tCAS
tCP
VIH
CAS
VIL
tASR
Address
VIH
tRAH
ROW
ADDRESS
tCAH
tASC
tCAH
tASC
COLUMN-1
COLUMN-2
tCAH
tASC
COLUMN-3
tASR
ROW
ADDRESS
VIL
tWCS
tWCH
tWCS
tWCH
tWCS
tDS
tDH
tDS
tDH
tDS
tWCH
VIH
W
VIL
DQ
(INPUTS)
DQ
(OUTPUTS)
OE
VIH
DATA
VALID-1
DATA
VALID-2
tDH
DATA
VALID-3
VIL
VOH
Hi-Z
VOL
VIH
VIL
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
tPC
tCAS
tCAS
tCP
VIH
CAS
VIL
tASR
Address
VIH
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN-1
tCAH
tRWL
tCWL
ROW
ADDRESS
COLUMN-2
VIL
tCWL
tRCS
tASR
tPCS
tWP
tWP
VIH
W
VIL
tWCH
tDZC
DQ
(INPUTS)
tWCH
tDH
tDS
VIH
DATA
VALID-1
Hi-Z
VIL
tCLZ
DQ
(OUTPUTS)
tDZC
tDS
tDH
DATA
VALID-2
Hi-Z
tCLZ
VOH
Hi-Z
Hi-Z
Hi-Z
VOL
tDZO
tOEZ
tOEZ
tODD
tDZO
tODD
tOEH
VIH
OE
VIL
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
RAS
tRP
VIH
VIL
tCSH
tCRP
tRWL
tRCD
tCAS
tPRWC
tCAS
tCP
CAS
VIH
VIL
tRAD
tASR
VIH
Address
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN-1
tCAH
tCWL
ROW
ADDRESS
COLUMN-2
VIL
tAWD
tRCS
tAWD
tCWL
tCWD
tCWD
tRCS
tWP
W
tASR
tWP
VIH
VIL
tRWD
tCPWD
tDZC
DQ
(INPUTS)
VIH
tDZC
tDS
DATA
VALID-1
Hi-Z
tCAC
VIL
tDH
tDS
tAA
tAA
DATA
VALID-1
Hi-Z
tRAC
tDZO
OE
tCLZ
VOH
VOL
DATA
VALID-2
Hi-Z
tCAC
tCLZ
DQ
(OUTPUTS)
tDH
tCPA
tODD
tOEA
DATA
VALID-1
Hi-Z
tOEZ
Hi-Z
tODD
tDZO
tOEZ
tOEH
tOEA
VIH
VIL
MIT-DS-0107-0.5
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Unit:mm
Package outline
133.35
3.0
8.6MAX
127.35
4.0
3.0
17.78
25.4
17.78
3.0
4.0
2-R2.0
2.0
2-ø3.0
2.0
6.35
1.27
29x1.27=36.83
8.89
1.27
6.35
43x1.27=54.61
9x1.27=11.43
24.495
MIT-DS-0107-0.5
42.18
MITSUBISHI
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