ON MJB42CT4 Complementary silicon plastic power transistor Datasheet

MJB41C (NPN),
MJB42C (PNP)
Preferred Devices
Complementary Silicon
Plastic Power Transistors
D2PAK for Surface Mount
http://onsemi.com
Features
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
• Electrically the Same as TIP41 and T1P42 Series
• Pb−Free Packages are Available
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COMPLEMENTARY SILICON
POWER TRANSISTORS
6 AMPERES,
100 VOLTS, 65 WATTS
MARKING
DIAGRAM
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCEO
100
Vdc
Collector−Base Voltage
VCB
100
Vdc
Emitter−Base Voltage
VEB
5.0
Vdc
IC
6.0
10
Adc
Base Current
IB
2.0
Adc
Total Power Dissipation
@ TC = 25_C
Derate above 25_C
PD
Total Power Dissipation
@ TA = 25_C
Derate above 25_C
PD
Collector−Emitter Voltage
Collector Current
− Continuous
− Peak
Unclamped Inductive Load Energy (Note 1)
Operating and Storage Junction
Temperature Range
65
0.52
W
W/_C
2.0
0.016
W
W/_C
E
62.5
mJ
TJ, Tstg
−65 to +150
_C
D2PAK
CASE 418B
STYLE 1
J4xC
A
Y
WW
G
Package
Shipping †
MJB41C
D2PAK
50 Units/Rail
MJB41CG
D2PAK
50 Units/Rail
Device
Symbol
Max
Unit
Thermal Resistance, Junction−to−Case
RqJC
1.92
_C/W
MJB41CT4
Thermal Resistance,
Junction−to−Ambient
RqJA
62.5
_C/W
MJB41CT4G
Thermal Resistance,
Junction−to−Ambient (Note 2)
RqJA
50
_C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
_C
260
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. IC = 2.5 A, L = 20 mH, P.R.F. = 10 Hz, VCC = 10 V, RBE = 100 W
2. When surface mounted to an FR−4 board using the minimum recommended
pad size.
= Specific Device Code
x = 1 or 2
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
THERMAL CHARACTERISTICS
Characteristic
J4xCG
AYWW
(Pb−Free)
D2PAK
800/Tape & Reel
D2PAK
(Pb−Free)
800/Tape & Reel
MJB42C
D2PAK
50 Units/Rail
MJB42CG
D2PAK
50 Units/Rail
(Pb−Free)
MJB42CT4
D2PAK
800/Tape & Reel
MJB42CT4G
D2PAK
800/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 1
1
Publication Order Number:
MJB41C/D
MJB41C (NPN),
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ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
VCEO(sus)
100
−
Vdc
Collector Cutoff Current (VCE = 60 Vdc, IB = 0)
ICEO
−
0.7
mAdc
Collector Cutoff Current (VCE = 100 Vdc, VEB = 0)
ICES
−
100
mAdc
Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0)
IEBO
−
50
mAdc
hFE
30
15
−
75
−
Collector−Emitter Saturation Voltage (IC = 6.0 Adc, IB = 600 mAdc)
VCE(sat)
−
1.5
Vdc
Base−Emitter On Voltage (IC = 6.0 Adc, VCE = 4.0 Vdc)
VBE(on)
−
2.0
Vdc
Current−Gain − Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, ftest = 1.0 MHz)
fT
3.0
−
MHz
Small−Signal Current Gain (IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz)
hfe
20
−
−
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 3) (IC = 30 mAdc, IB = 0)
ON CHARACTERISTICS (Note 3)
DC Current Gain
(IC = 0.3 Adc, VCE = 4.0 Vdc)
(IC = 3.0 Adc, VCE = 4.0 Vdc)
DYNAMIC CHARACTERISTICS
PD, POWER DISSIPATION (WATTS)
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
TA
4.0
TC
80
3.0
60
2.0
40
1.0
20
0
0
TC
TA
0
20
40
60
100
80
T, TEMPERATURE (°C)
120
140
160
Figure 1. Power Derating
VCC
+30 V
2.0
RC
0.7
0.5
SCOPE
+11 V
−9.0 V
tr, tf ≤ 10 ns
DUTY CYCLE = 1.0%
t, TIME (s)
μ
RB
0
TJ = 25°C
VCC = 30 V
IC/IB = 10
1.0
25 ms
D1
0.3
0.2
tr
0.1
0.07
0.05
−4 V
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
0.03
0.02
0.06
D1 MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
Figure 2. Switching Time Test Circuit
td @ VBE(off) ≈ 5.0 V
0.1
0.2
0.4 0.6
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
Figure 3. Turn−On Time
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2
4.0
6.0
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
MJB41C (NPN),
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.02
0.03
0.02
0.01
SINGLE PULSE
0.01
0.01
0.02
0.05
1.0
P(pk)
ZqJC(t) = r(t) RqJC
RqJC = 1.92°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) ZqJC(t)
0.05
0.2
0.5
1.0
2.0
5.0
t, TIME (ms)
10
20
t1
t2
DUTY CYCLE, D = t1/t2
50
100
200
500
1.0 k
Figure 4. Thermal Response
IC, COLLECTOR CURRENT (AMP)
10
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 5 is based on T J(pk) = 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T J(pk)
v 150_C. T J(pk) may be calculated from the data in
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
0.5ms
5.0
1.0ms
3.0
2.0
1.0
0.5
0.3
0.2
SECONDARY BREAKDOWN LTD
BONDING WIRE LTD
THERMAL LIMITATION @ TC = 25°C
(SINGLE PULSE)
CURVES APPLY BELOW RATED VCEO
0.1
5.0
5.0ms
40
10
20
60
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
80 100
Figure 5. Active−Region Safe Operating Area
5.0
300
ts
t, TIME (s)
μ
1.0
TJ = 25°C
TJ = 25°C
VCC = 30 V
IC/IB = 10
IB1 = IB2
200
C, CAPACITANCE (pF)
3.0
2.0
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.06
tf
Cib
100
70
Cob
50
0.1
0.2
0.4 0.6
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
4.0
30
0.5
6.0
Figure 6. Turn−Off Time
1.0
2.0 3.0
5.0
10
20
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance
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3
30
50
VCE , COLLECTOR−EMITTER VOLTAGE (VOLTS)
MJB41C (NPN),
hFE , DC CURRENT GAIN
500
300
200
VCE = 2.0 V
TJ = 150°C
100
70
50
25°C
30
20
10
7.0
5.0
0.06
−55 °C
0.1
0.2 0.3 0.4 0.6
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
4.0
6.0
2.0
TJ = 25°C
1.6
1.2
IC = 1.0 A
0.4
0
10
θV, TEMPERATURE COEFFICIENTS (mV/°C)
V, VOLTAGE (VOLTS)
1.6
1.2
VBE(sat) @ IC/IB = 10
0.8
VBE @ VCE = 4.0 V
0.4
VCE(sat) @ IC/IB = 10
0.2 0.3 0.4
IC, COLLECTOR CURRENT (A)
μ
50
100
200 300
IB, BASE CURRENT (mA)
500
0.6
1.0
2.0 3.0 4.0
6.0
+2.0
1000
*APPLIES FOR IC/IB ≤ hFE/4
+1.5
+1.0
+0.5
+25 °C to +150°C
* qVC FOR VCE(sat)
0
−55 °C to +25°C
−0.5
+25 °C to +150°C
−1.0
−1.5
qVB FOR VBE
−55 °C to +25°C
−2.0
−2.5
0.06
0.1
0.2 0.3
0.5
2.0 3.0 4.0
IC, COLLECTOR CURRENT (AMP)
Figure 10. “On” Voltages
Figure 11. Temperature Coefficients
VCE = 30 V
TJ = 150°C
100°C
VCE = 30 V
100
IC = ICES
10−1
REVERSE
FORWARD
0
+0.1 +0.2 +0.3
IC = 10 x ICES
IC ≈ ICES
100k
25°C
+0.4 +0.5 +0.6
+0.7
6.0
10M
1.0M
10−3
−0.3 −0.2 −0.1
1.0
IC, COLLECTOR CURRENT (AMP)
R BE , EXTERNAL BASE−EMITTER RESISTANCE (OHMS)
0.1
103
10−2
30
+2.5
TJ = 25°C
101
20
Figure 9. Collector Saturation Region
2.0
102
5.0 A
0.8
Figure 8. DC Current Gain
0
0.06
2.5 A
10k
IC = 2 x ICES
1.0k
0.1k
(TYPICAL ICES VALUES
OBTAINED FROM FIGURE 12)
20
40
60
80
100
120
140
160
VBE, BASE−EMITTER VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Collector Cut−Off Region
Figure 13. Effects of Base−Emitter Resistance
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4
MJB41C (NPN),
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
H
D 3 PL
0.13 (0.005)
M
T B
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
VARIABLE
CONFIGURATION
ZONE
N
R
P
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
L
M
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
MJB41C (NPN),
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your
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MJB41C/D
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