MK2712 NTSC/PAL Clock Source Description Features The MK2712 is the ideal way to generate clocks for NTSC/PAL video encoders and decoders. Stored in the device are two sets of popular frequencies for NTSC and PAL. In an 8 pin SOIC, the chip can save component count, board space, and cost over surface mount crystals and oscillators, and increase reliability by eliminating one or two mechanical devices from the board. The power down pin turns off the device, drawing less than 20µA. • Packaged in 8 pin SOIC • Ideal for chips such as Analog Devices AD722 and Brooktree BT819 • Input clock frequency of 27.0000 MHz • Power down turns off chip • Output enable tri-states output for system testing • Frequencies are within 1 ppm with accurate input clock ICS/MicroClock offers many other clocks for computers and computer peripherals. Consult us when you need to remove crystals and oscillators from your board. • Low jitter • Output clock frequencies of 14.31818MHz, 17.7345MHz, 28.6364MHz, or 35.46896MHz • 25mA drive capability at TTL levels • 3.3V or 5V supply voltage • Advanced, low power CMOS process • Insensitive to input clock duty cycle Block Diagram VDD FS0, 1 PD GND 2 PLL Clock Synthesis Circuitry Output Buffer NTSC/PALCL OCK 27.00 MHz clock input OE MDS 2712 C 1 Revision 061401 Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com MK2712 NTSC/PAL Clock Source Pin Assignment Decoding Table ICLK 1 8 FS0 VDD 2 7 PD GND 3 6 OE NPCLK 4 5 FS1 FS1 0 0 1 1 FS0 0 1 0 1 NPCLK (MHz) 14.31818 17.73447 28.63636 35.46894 Error (ppm) 0.3 ppm 0.3 ppm 0.3 ppm 0.3 ppm 8 pin SOIC Pin Descriptions Number Name 1 ICLK 2 VDD 3 GND 4 NPCLK 5 FS1 6 OE 7 PD 8 FS0 Type I P P O I I I I Description Input Clock. Connect to a 27.0000 MHz clock. Connect to +3.3V or +5V. Connect to ground. NTSC or PAL output clock. Selected by FS1, FS0 per tables above. Frequency Select pin #1. Selects NTSC or PAL frequency per table above. Output Enable. Tri-states clock output when this input is low. Internal pull-up. Power Down. Active low. Clocks stop low. Frequency Select pin #0. Selects NTSC or PAL frequency per table above. Key: I = Input, O = output, P = power supply connection External Components/Crystal Selection A minimum number of external components are required for proper oscillation. Connect a 27.000 MHz clock to ICLK. A decoupling capacitor of 0.1µF should be connected between VDD and GND on pins 2 and 3, and a 33Ω terminating resistor should be used on the clock output if the trace is longer than 1 inch. MDS 2712 C 2 Revision 061401 Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com MK2712 NTSC/PAL Clock Source Electrical Specifications Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (note 1) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Outputs Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (at 5.0V unless otherwise noted) Operating Voltage, VDD 4.5 Input High Voltage, VIH, input clock only ICLK pin 3.5 Input Low Voltage, VIL, input clock only ICLK pin Input High Voltage, VIH 2 Input Low Voltage, VIL Output High Voltage, VOH IOH=-4mA VDD-0.4 Output High Voltage, VOH IOH=-25mA 2.4 Output Low Voltage, VOL IOL=25mA Operating Supply Current, IDD No Load, FS1=1. FS0=1 Power Down Supply Current, IDDPD No Load Input Capacitance Actual Mean Frequency versus Target With exact ICLK AC CHARACTERISTICS (at 5.0V unless otherwise noted) Input Clock Frequency Input Clock Duty Cycle Time above 2.5V 20 Output Clock Rise Time 0.8 to 2.0V Output Clock Fall Time 2.0 to 0.8V Output Clock Duty Cycle Time above 1.5V 40 Absolute Maximum Clock Period Jitter, 15 pF Variation from mean One Sigma Clock Period Jitter, 15 pF load Absolute Maximum Clock Period Jitter, 15 pF VDD=3.3V One Sigma Clock Period Jitter, 15 pF load VDD=3.3V Typical 2.5 2.5 Maximum Units 7 VDD+.5V VDD+.5V 70 260 150 V V V °C °C °C 5.5 V V V V V V V V mA µA pF ppm 1.5 0.8 0.4 13 10 5 0.3 0.3 27 50 ± 90 30 ± 180 50 80 1.5 1.5 60 MHz % ns ns % ps ps ps ps Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. Typical values are at 25°C. MDS 2712 C 3 Revision 061401 Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com MK2712 NTSC/PAL Clock Source Package Outline and Package Dimensions 8 pin SOIC E Symbol A b D E H e h L Q H Pin 1 h x 45° Inches Min Max 0.055 0.061 0.013 0.019 0.185 0.200 0.150 0.160 0.225 0.245 .050 BSC 0.015 0.016 0.035 0.004 0.01 Millimeters Min Max 1.397 1.5494 0.330 0.483 4.699 5.080 3.810 4.064 5.715 6.223 1.27 BSC 0.381 0.406 0.889 0.102 0.254 A Q c b e L D Ordering Information Part/Order Number Marking Package Temperature MK2712S MK2712S 8 pin SOIC 0-70°C MK2712STR MK2712S Add tape and reel 0-70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 2712 C 4 Revision 061401 Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com