OKI MK31VT432-10YC 4,194,304 word x 32 bit synchronous dynamic ram module (1bank) Datasheet

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MK31VT432-10YC 98.07.21
Semiconductor
MK31VT432-10YC
4,194,304 Word x 32 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK):
DESCRIPTION
The Oki MK31VT432-10YC is a fully decoded, 4,194,304 x 32bit synchronous dynamic
random access memory composed of two 64Mb DRAMs (4Mx16) in TSOP packages
mounted with decoupling capacitors on a 100-pin glass epoxy Dual-in-Line Package
supports any application where high density and large capacity of storage memory are
required, like for example PCs or servers.
FEATURES
•
•
•
•
•
•
•
•
•
•
4-Meg Word x 32-Bit (1Bank 4 Byte) organization
100-pin Dual Inline Memory Module
10Ω Damping Resister for DQ and CLK Pins
Single 3.3V power supply, ±0.3V tolerance
Input
:LVTTL compatible
Output :LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
• /CAS latency (2, 3)
• Burst length (2, 4, 8)
• Data scramble(sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
PRODUCT ORGANIZATION
Product Name
MK31VT432 - 10YC
Operation
Access Time (Max.)
Frequency (Max.)
tAC2
tAC3
100 MHz
13.0ns
9.0ns
Note. Specification are subject to change without notice.
Page 1/11
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MK31VT432-10YC 98.07.21
BLOCK DIAGRAM
CKE0
/CS0
DQMB0
DQ0
LDQM /CS CKE
DQ0
DQ7
DQ7
DQMB1
UDQM
DQ8
DQ8
DQ15
DQ15
DQMB3
DQ24
LDQM /CS CKE
DQ0
DQ31
DQ7
DQMB2
UDQM
DQ16
DQ8
DQ23
DQ15
1
2
Serial PD
SCL
5
SDA
A0 A1 A2
1
CLK1
CLK0
SA0 SA1 SA2
2
10pF
10pF
/RAS,/CAS,/WE
A0-A11,BA0,BA1
1
á
Vcc
2
SDRAMs
Vss
0.22µF x2
Note. The Value of all resistors is 10Ω .
MODULE OUTLINE
(Front)
(Back)
1
51
6
7
56 57
22 23
72 73
50
100
Page 2/11
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MK31VT432-10YC 98.07.21
PIN CONFIGURATION
Front side
Pin No. Pin name
1
VSS
2
DQ0
3
DQ1
4
DQ2
5
DQ3
6
VCC
7
DQ4
8
DQ5
9
DQ6
10
DQ7
11
DQMB0
12
VSS
13
A0
14
A2
15
A4
16
A6
17
A8
18
A10
19
BA1
20
NC
21
VCC
22
NC
23
NC
24
NC
25
CLK0
Pin Name
VCC
VSS
CLK#
/CS#
CKE#
A0-A11
BA0, BA1
/RAS
/CAS
Back side
Pin No. Pin name
51
VSS
52
DQ8
53
DQ9
54
DQ10
55
DQ11
56
VCC
57
DQ12
58
DQ13
59
DQ14
60
DQ15
61
DQMB1
62
VSS
63
A1
64
A3
65
A5
66
A7
67
A9
68
BA0
69
A11
70
NC
71
VCC
72
/RAS
73
/CAS
74
NC
75
CLK1
Function
Power Supply (3.3V)
Ground (0V)
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Front side
Pin No. Pin name
26
VSS
27
CKE0
28
/WE
29
/CS0
30
/CS2
31
VCC
32
NC
33
NC
34
NC
35
NC
36
VSS
37
DQMB2
38
DQ16
39
DQ17
40
DQ18
41
DQ19
42
VCC
43
DQ20
44
DQ21
45
DQ22
46
DQ23
47
VSS
48
SDA
49
SCL
50
VCC
Pin Name
/WE
DQMB#
DQ#
SDA
SCL
SA#
NC
Back side
Pin No. Pin name
76
VSS
77
NC
78
NC
79
NC
80
NC
81
VCC
82
NC
83
NC
84
NC
85
NC
86
VSS
87
DQMB3
88
DQ24
89
DQ25
90
DQ26
91
DQ27
92
VCC
93
DQ28
94
DQ29
95
DQ30
96
DQ31
97
VSS
98
SA0
99
SA1
100
SA2
Function
Write Enable
Data Input / Output Mask
Data Input / Output
Data I/O for SPD
CLK input for SPD
Socket Position Address for SPD
No Connection
Page 3/11
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MK31VT432-10YC 98.07.21
SERIAL PRESENCE DETECT
Byte
No.
0
SPD
Hex Value
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
08
04
0C
08
01
20
00
01
A0
90
00
80
10
00
01
0E
04
06
01
01
00
06
F0
90
00
00
1E
14
1E
3C
04
30
10
30
10
00-00
02
35
41,45,20,20,20,20,20,20
01 / 06
4D,4B,33,31,56,54,34,33,32,
2D,31,30,59,43,20,20,20,20
20, 20
91, 92
00-00
93-125
66
126
06
127
FF-FF
128-255
73-90
Remark
Notes
Defines the number of bytes written into
SPD memory
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
Number of columns
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
Cycle time (CL=3)
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
128 byte
Manufacturer’s part number
MK31VT432-10YC
256 byte
SDRAM
12 rows
8 columns
1 bank
32 bits
0
LVTTL
CL=3 tCC=10ns
CL=3 tAC3=9ns
None Parity
Normal / Self
x16
tCCD: 1 CLK
2, 4, 8
4 banks
2, 3
0
0
CL=2 tCC2=15ns
CL=2 tAC2=9ns
Not support
Not support
tRP=30ns
tRRD=20ns
tRCD=30ns
tRAS=60ns
16MB
Command and address signal input setup time 3ns
Command and address signal input hold time
1ns
Data signal input setup time
3ns
Data signal input hold time
1ns
Superset Information
R.F.U
SPD data revision code
02
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
66MHz
CL=2,3
Page 4/11
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MK31VT432-10YC 98.07.21
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 to Vcc+0.5
V
Vcc supply voltage
Vcc, VccQ
-0.5 to 4.6
V
Storage temperature
Tstg
- 55 to 150
°C
Power dissipation
PD*
2
W
Short circuit current
IOS
50
mA
Topr
0 to 70
°C
Operating temperature
*: Ta=25°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vcc, VccQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
-
Vcc+0.3
V
Input low voltage
VIL
-0.3
-
0.8
V
Power supply voltage
Capacitance
(Vcc=3.3V ± 0.3V, Ta=25 °C f=1MHz)
Parameter
Symbol
Max.
Unit
Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE)
CIN1
16
pF
Input capacitance (/CS0,/CS2)
CIN2
16
pF
Input capacitance (DQMB0-DQMB3)
CIN3
11
pF
Input capacitance (CKE0)
CIN4
16
pF
I/O capacitance (DQ0-DQ32)
CI/O
13
pF
Input capacitance (CLK0)
CCLK
25
pF
Page 5/11
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MK31VT432-10YC 98.07.21
DC CHARACTERISTICS
(Vcc=3.3V ± 0.3V, Ta = 0 to 70 °C)
Parameter
Condition
Symbol
Module Spec.
CKE
Others
Min.
Max.
Unit
Output High Voltage
VOH
-
IOH = -2.0mA
2.4
-
V
Output Low Voltage
VOL
-
IOL = 2.0mA
-
0.4
V
ILI
µA
Input Leakage Current
-20
20
Output Leakage
ILO
-10
10
µA
Current
Average Power Supply
tCC=min.
Current
ICC1
CKE ≥ VIH
290
mA
tRC=min.
(Operating)
No Burst
Power Supply Current
ICC2
tCC=min.
CKE ≥ VIH
80
mA
(Stand by)
Average Power
ICC3S
tCC=min.
CKE ≤ VIL
30
mA
Supply Current
(Clock Suspension)
Average Power
CKE ≥ VIH,
ICC3
tCC=min.
Supply Current
190
mA
/CS ≥ VIH
(Active Stand by)
Power Supply
ICC4
tCC=min.
CKE ≥ VIH
420
mA
Current (Burst)
Power Supply
tCC=min.
ICC5
CKE ≥ VIH
Current
370
mA
tRC=min.
(Auto-Refresh)
Average Power
ICC6
tCC=min.
Supply Current
4
CKE ≤ 0.2V
mA
(Self-Refresh)
Average Power
ICC7
tCC=min.
CKE ≤ VIL
Supply Current
4
mA
(Power down)
Notes: 1.
Measured with the output open.
2.
Address and data can be changed once or not be changed during one cycle.
3.
Address and data can be changed once or not be changed during two cycle.
Note
1, 2
3
2
3
1, 2
2
MODE SET ADDRESS KEYS
/CAS Latency
A6
0
0
0
0
1
1
1
1
Note:
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CL
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
A3
0
1
BT
Sequential
Interleave
Burst Length
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
BT=0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
BT=1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
A7, A8, A10, A11, BA0, BA1 and All should stay "L" during mode set cycle.
Page 6/11
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MK31VT432-10YC 98.07.21
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the VCC voltage has reached the specified level, take a pause of 200µs or more
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
Page 7/11
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MK31VT432-10YC 98.07.21
AC CHARACTERISTIC
(Vcc=3.3V ± 0.3V, Ta = 0 to 70 °C)
NOTE 1, 2
Parameter
Clock Cycle Time
Access Time from Clock
Symbol
CL=3
CL=2
CL=3
CL=2
tCC
tAC
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Hold Time
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
/RAS Cycle Time
/RAS Precharge Time
/RAS Active Time
/RAS to /CAS Delay Time
Write Recovery Time
/RAS to /RAS Bank Active Delay Time
Refresh Time
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
Data Output High Impedance Time from
Data Input Mask Time from DQMB
Data Input Time from Write Command
Data Output High Inpedance
Time from Precharge Command
tCH
tCL
tHI
tOLZ
tOHZ
tOH
tRC
tRP
tRAS
tRCD
tWR
tRRD
tREF
tPDE
tT
ICCD
ICKE
IDOZ
IDOD
IDWD
IROH
Active Command Input Time from MODE
Write Command Input Time from Output
IMRD
tOWD
Module Spec.
Min.
Max.
10
15
3
3
1
3
3
100
40
60
30
20
20
tSI+1CLK
-
9
13
8
100,000
64
3
Unit
Note
1
1
2
0
0
2
ns
ns
ns
3, 4
ns
3, 4
ns
ns
ns
ns
ns
ns
3
ns
ns
ns
ns
ns
ns
ms
ns
ns
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
3
2
Cycle
Cycle
NOTES:
1)
AC measurements assume tT=1ns.
2)
The reference level for timing of input signals is 1.4V.
3)
This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(RLoad is 50ohm).
4)
An access time is measured at 1.4V.
5)
If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.
1.4v
50Ω
OUTPUT
50pF
OUTPUT LOAD CONDITION
Page 8/11
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MK31VT432-10YC 98.07.21
FUNCTION TRUTH TABLE
Current State
Idle
Row Active
Read
Write
Read with
Auto Precharge
Write with
Auto Precharge
/CS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
/RAS
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
X
H
H
H
H
L
L
/CAS
X
H
H
L
H
H
L
L
X
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
L
X
H
H
L
L
H
L
(Table1)
/WE
X
H
L
X
H
L
H
L
X
X
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
X
X
X
H
L
H
L
X
X
BA
X
X
BA
BA
BA
BA
X
L
X
X
BA
BA
BA
BA
X
X
X
BA
BA
BA
BA
BA
X
X
X
BA
BA
BA
BA
BA
X
X
X
BA
BA
X
BA
X
X
X
BA
BA
X
BA
X
(1/2)
ADDR
X
X
X
CA
RA
A10
X
OP Code
X
X
CA, A10
CA, A10
RA
A10
X
X
X
X
CA, A10
CA, A10
RA
A10
X
X
X
X
CA, A10
CA, A10
RA
A10
X
X
X
X
CA, A10
X
RA, A10
X
X
X
X
CA, A10
X
RA, A10
X
Action
NOP
NOP
2
ILLEGAL
2
ILLEGAL
Row Active
4
NOP
5
Auto-Refresh or Self-Refresh
Mode Register write
NOP
NOP
Read
Write
2
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved
3
Term Burst, start new Burst Read
3
Term Burst, start new Burst Write
2
ILLEGAL
Term Burst, execute Row Precharge
ILLEGAL
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved
3
Term Burst, start new Burst Read
3
Term Burst, start new Burst Write
2
ILLEGAL
3
Term Burst, execute Row Precharge
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
ILLEGAL
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
ILLEGAL
ILLEGAL
Page 9/11
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MK31VT432-10YC 98.07.21
FUNCTION TRUTH TABLE
Current State
Precharge
Write
Recovery
Row Active
Refresh
Mode Resister
Access
/CS
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
/RAS
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
/CAS
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
(Table1)
/WE
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
BA
X
X
BA
BA
BA
BA
X
X
X
BA
BA
BA
BA
X
X
X
BA
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
(2/2)
ADDR
X
X
X
CA
RA
A10
X
X
X
X
CA
RA
A10
X
X
X
X
CA
RA
A10
X
X
X
X
X
X
X
X
X
X
X
Action
NOP Idle after tRP
NOP Idle after tRP
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
4
NOP
ILLEGAL
NOP
NOP
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
NOP Row Active after tRCD
NOP Row Active after tRCD
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
NOP Idle after tRC
NOP Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
Æ
Æ
Æ
Æ
Æ
Æ
ABBREVIATIONS
RA = Row Address
BA = Bank Address
CA = Column Address
AP = Auto Precharge
NOP = No Operation command
Notes:
1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3. Satisfy the timing of ICCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
Page 10/11
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MK31VT432-10YC 98.07.21
FUNCTION TRUTH TABLE
Current State(n)
Self Refresh
Power Down
All Banks idle
(ABI)
Any State
Other than
Listed Above
6
CKEn-1
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
CKEn
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
/CS
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
(CKE)
/RAS
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
(Table2)
/CAS
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
/WE
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
L
H
L
X
X
X
X
X
ADDR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Action
INVALID
Exit Self Refresh ABI
Exit Self Refresh ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down ABI
Exit Power Down ABI
ILLEGAL
ILLEGAL
6
ILLEGAL
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self Refresh
ILLEGAL
NOP
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
Æ
Æ
Æ
Æ
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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