OKI ML2201-XXX Speech synthesizer lsi with on-chip 384k mask rom Datasheet

FEDL2201-01
1Semiconductor
ML2201-XXX
This version: Mar. 2000
Speech Synthesizer LSI with on-chip 384K Mask ROM
GENERAL DESCRIPTION
The ML2201 is a PCM-based speech synthesizer LSI having an on-chip 384K Mask ROM, D/A Converter and
Low Pass Filter. Utilizing the serial interface enables smaller footprint packaging, which makes the chip an ideal
choice for a pre-recorded message subsystem used with today’s size-critical applications.
FEATURES
• Sampling Frequency (Selectable for each single phrase)
4.0/5.3/6.4/8.0/10.6/12.8/16.0 kHz
• On-chip 384 Kbit Mask ROM
• Maximum Playback Time (At fEXTCLK = 4.096 MHz)
12.0 sec
At fSAM = 4.0 kHz
6.0 sec
At fSAM = 8.0 kHz
3.0 sec
At fSAM = 16.0 kHz
• External Clock Frequency Range *
fEXTCLK = 3.5 to 4.096 MHz (Typ.) to 17.0 MHz
• On-chip Phrase Control Table
• Maximum Number of Phrases:
31 Phrases
• Built-in 10-bit Current-Output Type D/A Converter
• Built-in LPF
• Packaging:
8-pin Plastic SSOP (SSOP8-P-44-0.65-K)
(Product Code: ML2201-XXX MBZ060)
• Power Supply Voltage:
+2.0 to +5.5 V
* Note:
As of February 2000, ceramic oscillation on this chip is under development and thus the chip is not
functional with a ceramic oscillator. The manufacturer intends to add a ceramic oscillation option to the
chip. For more information on availability in commercial quantity, contact your sales representative.
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FEDL2201-01
1Semiconductor
ML2201–XXX
PIN LAYOUT (TOP VIEW)
ST
1
8
PDWN
PI
2
7
XT
GND
3
6
XT
AOUT
4
5
VDD
8-Pin Plastic SSOP
BLOCK DIAGRAM
16
384 Kbit ROM
8
ST
PI
Edit ROM 2 Kbit
5
Serial
Interface
16 bit Address
controller
(Phrase Control Table)
8
Address ROM 2 Kbit
PDWN
(Phrase Address Table)
Reset, Power Down
Test ROM 2 Kbit
Timing
Controller
XT
XT
8
PCM
Synthesizer
OSC
Circuit
VDD
GND
PCM data Area
378 Kbit
10
10 bit DAC
LPF
AOUT
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ML2201–XXX
PIN DESCRIPTION
Pin No.
Pin Name
I/O
Description
The playback trigger pin.
1
ST
I
The number of pulses input to the PI pin, while this pin is held “L”,
determines the Phrase Address for playback. At the ST’s rising edge, the
phrase address data is loaded into the LSI and playback starts. When no
pulse input to PI occurs while this pin is held “L”, the LSI recognizes it as the
“Stop Code” that results in stopping playback.
The address input pin.
2
PI
I
The number of pulses input to this pin, while the ST pin is held “L”,
determines the Phrase Address for playback.
When 32 pulses are input, the internal counter returns to its initial value, “0”.
3
GND
—
The ground pin.
The analog output pin.
4
AOUT
O
Configured as N-MOS open drain, analog signal is output in the form of
change in output (attraction) current. While the PDWN pin being held “H”,
this pin is sustained at 1/2 level and thus the current keeps on flowing.
When shifting to standby state and shifting back to ready state from
standby, the pop-noise canceller is put to work.
5
VDD
—
6
XT
I
The power supply pin.
Insert a 0.1 µF bypass capacitor between this pin and the GND pin.
The external clock input pin.
The ceramic resonator connection pin for ceramic oscillation option under
development.
Keep this pin open.
7
XT
O
The LSI’s operations may become unstable if this pin includes any
capacitive component.
The ceramic resonator connection pin for ceramic oscillation option under
development.
8
PDWN
I
The power down pin.
The LSI stays standby state while the pin being held “L”.
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FEDL2201-01
1Semiconductor
ML2201–XXX
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V)
Parameter
Symbol
Power Supply Voltage
VDD
Input Voltage
VIN
Storage Temperature
Power Drain Allowance
Condition
Ta = 25°C
Rating
Unit
–0.3 to +7.0
V
–0.3 to VDD +0.3
V
TSTG
—
–55 to +150
°C
Pd
Ta = 25°C
250
mW
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V)
Parameter
Power Supply Voltage
External Clock Frequency
Operating Temperature
Symbol
VDD
fEXTCLK
TOP
Condition
Range
Unit
fEXTCLK = 3.5 to 4.5 MHz
+2.0 to +5.5
V
fEXTCLK = 3.5 to 13.5 MHz
+2.6 to +5.5
V
fEXTCLK = 3.5 to 17.0 MHz
+3.0 to +5.5
V
Min.
Typ.
Max.
VDD = 2.0 to 5.5 V
3.5
4.096
4.5
VDD = 2.6 to 5.5 V
3.5
—
13.5
VDD = 2.7 to 5.5 V
3.5
—
14.5
VDD = 3.0 to 5.5 V
3.5
—
17.0
—
–40 to +85
MHz
°C
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ML2201–XXX
ELECTRICAL CHARACTERISTICS
DC Characteristics
VDD = 2.0 to 5.5 V, GND = 0 V, fEXTCLK = 4.096 MHz, Ta = –40 to +85°C (unless otherwise specified)
Parameter
“H” Input Voltage
Symbol
VIH
Condition
Min.
FEXTCLK > 14.5 MHz
VDD
VDD = 3.0 to 5.5 V
× 0.85
fEXTCLK ≤ 14.5 MHz
VDD
VDD = 2.7 to 5.5 V
× 0.8
Max.
Unit
—
—
V
—
—
V
—
—
V
—
V
fEXTCLK ≤ 13.5 MHz
VDD
VDD = 2.6 to 2.7 V
× 0.85
fEXTCLK ≤ 4.5 MHz
VDD
VDD = 2.0 to 5.5 V
× 0.8
—
—
—
× 0.15
—
—
× 0.2
—
—
—
—
× 0.2
V
FEXTCLK > 14.5 MHz
VDD = 3.0 to 5.5 V
fEXTCLK ≤ 14.5 MHz
VDD = 2.7 to 5.5 V
“L” Input Voltage
Typ.
VDD
VDD
V
V
VIL
fEXTCLK ≤ 13.5 MHz
VDD = 2.6 to 2.7 V
fEXTCLK ≤ 4.5 MHz
VDD = 2.0 to 5.5 V
VDD
× 0.15
VDD
V
“H” Input Current
IIH
VIH = VDD
—
—
10
µA
“L” Input Current
IIL
VIL = GND
–10
—
—
µA
—
1.7
3.9
mA
—
0.9
2.1
mA
—
0.5
1.4
mA
—
4.6
12.0
mA
—
1.8
6.5
mA
—
—
10
µA
VDD = 5.5 V
fEXTCLK = 4.096 MHz
VDD = 3.0 V
fEXTCLK = 4.096 MHz
Supply Current
IDD
Except AOUT
VDD = 2.0 V
output current
fEXTCLK = 4.096 MHz
VDD = 5.5 V
fEXTCLK = 16 MHz
VDD = 3.0 V
fEXTCLK = 16 MHz
Standby Current
AOUT Output Current
Ta = –40 to +70°C
IDS
IAOUT
—
—
50
µA
VDD = 2.0 to 5.5 V
0.5
—
10.0
mA
VDD = 5.5 V
4.3
6.8
10.0
mA
Ta = –40 to +85°C
At max.
output current
VDD = 3.0 V
1.4
2.7
3.9
mA
VDD = 2.0 V
0.5
1.2
2.2
mA
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ML2201–XXX
AC Characteristics
VDD = 2.0 to 5.5 V, GND = 0 V, fEXTCLK = 4.096 MHz, Ta = –40 to +85°C (unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
fDUTY
—
40
50
60
%
Reset Input Time after Powering Up
tRST
—
10
—
—
µs
PDWN Hold Time after Reset Input
tPDH
—
10
—
—
µs
tDAR, tDAF
—
60
64
68
ms
PDWN – ST Setup Time
tPDSS
—
1
—
—
µs
ST – PI Setup Time
tSPS
—
1
—
—
µs
PI Pulse Width
tPW
—
0.35
—
2000
µs
PI Cycle Time
tPC
—
0.7
—
4000
µs
ST – PI Hold Time
tSPH
—
1
—
—
µs
tSAS
At fSAM = 8.0 kHz
—
1050
µs
tDPS
At fSAM = 8.0 kHz
—
700
µs
tBLN
At fSAM = 8.0 kHz
—
700
µs
tSSW
—
0.35
—
2000
µs
tPP
At fSAM = 8.0 kHz
1050
—
—
µs
tPS
At fSAM = 8.0 kHz
1050
—
—
µs
tSP
At fSAM = 8.0 kHz
500
—
—
µs
fSAM
—
3.9
—
28.0
kHz
Clock Oscillation Duty Cycle
D/A Converter Transit Time
(Pop-Noise Canceller Work Time)
Note *1
ST – AOUT Setup Time
Note *2
Phrase Stop Time
Note *2
Silence Time between Phrases
Note *2
Stop ST Pulse Width
Phrase ST – Phrase ST Pulse Duration
Note *2
Phrase ST – Stop ST Pulse Duration
Note *2
Stop ST – Phrase ST Pulse Duration
Note *2
Sampling Frequency
Note *3
Note *1: The value changes in proportion to the external clock frequency, fEXTCLK.
Note *2: The value changes in proportion to the sampling frequency, fSAM.
Note *3: The sampling frequency is determined by the external clock frequency, fEXTCLK, and the dividing
factor that is selected for each phrase.
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ML2201–XXX
TIMING DIAGRAMS
Timing Diagram at Powering On
VDD
PDWN
tPDH
tRST
ST
PI
Reset
Power Down
NOTE: The LSI’s reset operation can be performed by using a level input combination of PDWN = “L”,
ST = “L” and PI = “H”. After powering on, the initial reset operation is required at the above timing.
Timing Diagram at Powering Up and Standby State
PDWN
1/2 IAOUT
AOUT
tDAR
tDAF
Timing Diagram for Playback
PDWN
ST
PI
......
tSPS
tSPH
tPW
AOUT
tPDSS
tPC
tSAS
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ML2201–XXX
Timing Diagram on Re-addressing while Playing
ST
PI
AOUT
tDPS
tBLN
tPP
Stop playing the current phrase
Start playing the next phrase
Timing Diagram on Stop Code Input
ST
PI
tSSW
AOUT
tDPS
tPS
tSP
Stop playing the current phrase
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ML2201–XXX
FUNCTIONAL DESCRIPTION
Sampling Frequency
You can select a sampling frequency for each phrase address from the following list while you are working on
sound data. Select a sampling frequency that satisfies fSAM = 3.9 to 28.0 kHz from the values obtained with the
dividing factors as shown in the Table 1 below.
Table 1 Sampling Frequency
Sampling Frequency
At fEXTCLK = 4.096 MHz
Dividing Factor
4.0 kHz
fEXTCLK/1024
5.3 kHz
fEXTCLK/768
6.4 kHz
fEXTCLK/640
8.0 kHz
fEXTCLK/512
10.6 kHz
fEXTCLK/384
12.8 kHz
fEXTCLK/320
16.0 kHz
fEXTCLK/256
Memory Allocation and Playback Time Length
As shown in the Figure 1, the on-chip Mask ROM of ML2201 is partitioned into four areas, Phrase Control Table,
Address Control Table, Test Data area and User’s Data area. The actual data area where user’s sound data can be
stored is 378 Kbit, that is the total on-chip Mask ROM capacity minus 6 Kbit.
Phrase Control Table Area
2 Kbit
Address Control Table Area
2 Kbit
Test Data Area
2 Kbit
User’s Sound Data Area
378 Kbit
Figure 1 On-chip Mask ROM (384 Kbit) Memory Allocation
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ML2201–XXX
You can calculate playback time length with memory size divided by a bit rate. The following formula can be used
for 8-bit PCM-based ML2201;
Playback Time (sec) =
Memory Size (Bit)
Bit Rate (bps)
=
Memory Size (Bit)
Ext. Clock Frequency (Hz) × 8
For example, when you store all phrases at 8.0 kHz Sampling Frequency, the maximum playback time is
calculated as follows;
Playback Time (sec) =
(384 – 6) × 1024 Bit
≅ 6.0 sec
8000 (Hz) × 8 Bit
Playback Algorithm
ML2201 uses OKI Non-Linear PCM algorithm, an advanced variation of PCM.
In mid-range wave-form, this algorithm has precision and quality equivalent to those of 10-bit Straight PCM.
Inserting Silence
In addition to playing normal recorded sound phrases, ML2201 allows you to insert silence (a silent phrase) . You
can define time length of silence freely in 32 ms steps, within the range of minimum 32 ms and maximum 992 ms
at fEXTCLK = 4.096 MHz. Those time length vary in proportion to the external clock frequency, fEXTCLK.
Phrase Control Table
The user-definable on-chip Phrase Control Table feature enables you to play back multiple phrases in a single
continuous session with just the same simple control as in a regular single phrase playback. You can assign up to 8
phrases including a silent phrase (s) to a single address. This allows you to get the most out of limited memory
space because you can eliminate duplicate sound data.
As an example, let’s assume you want to create several similar phrases like “It will be xxxxx today”. “xxxxx” can
be “sunny”, “rainy” or “cloudy”. The common words such as “It”, “will be” and “today” are created separately as
an independent phrase, and phrasing order information is stored in the Phrase Control Table, as shown in the Table
2 and Figure 2.1. From the external control, simply selecting an X address causes the LSI to play multiple phrases
continuously. In this example shown in the Table 2, selecting [01] address starts to play “It will be fine today,
while selecting [02] “It will be rainy today”.
You can also insert a silent phrase to the Phrase Control Table without consuming any memory space.
Minimum Time Length of Silence
32 ms
Maximum Time length of Silence
992 ms
Incremental Step
32 ms
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ML2201–XXX
Table 2 Phrase Control Table Data
No.
X Address
Y Address (Phrasing Order)
(HEX)
(Up to 8 phrases)
1
01
[01]
[02]
Silence
[04]
[03]
2
02
[01]
[02]
Silence
[05]
[03]
3
03
:
:
30
1E
31
1F
[01]
[02]
[04]
[09]
[06]
Playback
It will be (Silence) fine today.
It will be (Silence) rainy today.
[0A]
[05]
[03]
It will be fine, later cloudy,
occasionally rainy.
:
Phrase Control Table Data
Address Control Table Data
No.
X Address
Phrasing Order
No.
Y Address
Phrase
1
01
1
[01] “It”
1
01
It
2
02
2
[02] “Will be”
2
02
will be
3
03
3
Silence (64 ms)
3
03
today
4
04
4
[05] “rainy”
4
04
fine
5
05
5
[03] “today”
5
05
rainy
6
06
6
—
6
06
cloudy
7
07
7
—
7
07
snowy
8
08
8
—
8
08
occasionally
9
09
later
10
0A
in some area
Set length of silence
:
:
:
:
:
:
31
(32 ms × n)
1F
n
Length of
Silence
:
:
:
:
:
:
1
32 ms
:
:
:
2
64 ms
:
:
31
992 ms
31
1F
—
Time unit of silence varies
in proportion to the dividing
factor of fEXTCLK.
Figure 2.1 Phrase Data Combination for Use with Phrase Control Table
11/20
Reset
AOUT
PI
ST
PDWN
VDD
Power Down
Playing
Playing
2nd Phrase
It will be rainy
today
2nd Phrase
1st Phrase
Stop Code
Stop playing
Playing
1st Phrase
Stop playing the
earlier phrase
Playing
3rd Phrase
It will be fine today, It will be……….
later occasionally...
3rd Phrase
Shifting to
Standby
Power Down
1Semiconductor
Figure 2.2 Timing Diagram for Playback with Phrase Control Table Function
Shifting to
Standby
1st Phrase
It will be fine
today
1st Phrase
FEDL2201-01
ML2201–XXX
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ML2201–XXX
External Clock Input
The Figure 3 shows wiring of an external timing source.
(A type of the external clock should be determined at selecting chip options.)
XT
XT
Keep this
pin open
An external
timing source
Figure 3 External Clock Input
* Note:
As of July 1999, ceramic oscillation on this chip is under development and thus the chip is not
functional with a ceramic oscillator. The manufacturer intends to add a ceramic oscillation option to the
chip. For more information on availability in commercial quantity, contact your sales representative.
13/20
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ML2201–XXX
Low Pass Filter
ML2201’s analog output goes through the built-in Low Pass Filter. The Figure 4 below shows Frequency
Characteristics and the Table 3 shows Cut-Off Frequency of the LPF.
The LPF’s Frequency Characteristics and Cut-Off Frequency change in proportion to the sampling frequency. No
analog output directly from the D/A converter is unavailable on this chip.
[dB] 20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
10
100
1k
10 k
[Hz]
Figure 4 LPF Frequency Characteristics (fSAM = 8.0 kHz)
Table 3 LPF Cut-Off Frequency
Sampling Frequency (kHz)
Cut-Off Frequency (kHz)
(fSAM)
(fCUT)
4.0
1.2
5.3
1.6
6.4
2.0
8.0
2.5
10.6
3.2
12.8
4.0
16.0
5.0
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ML2201–XXX
CONNECTING ML2201 TO A SPEAKER DRIVER
ML2201 uses a D/A converter of current-output type.
To connect ML2201 to a voltage-input type speaker driver, you should convert “Changes in Current” output to
“Changes in Voltage” signal. The following samples show connections of ML2201 and MSC1157 (OKI Speaker
Driver Amplifier) using a resistor (RL) for conversion.
SAMPLE CIRCUIT 1: AT VDD = 5.0 V, MSC1157’S Ain AMPLIFICATION = 2.5 VP-P
+5 V
+5 V
0.1 µF
ST
P1.1
PI
P1.0
PDWN
MCU
430 Ω
47 µF
VDD
P1.2
0.1 µF
AOUT
VCC
Ain
SP
SP
MSC1157
ML2201
CLK
10 µF
XT
STBY
XT
VR
4.7 µF
GND
SEL
GND
SAMPLE CIRCUIT 2: AT VDD = 3.0 V, MSC1157’S Ain AMPLIFICATION = 1.5 VP-P
+3 V
+3 V
0.1 µF
ST
P1.1
PI
P1.0
PDWN
10 µF
510 Ω
47 µF
VDD
P1.2
0.1 µF
AOUT
VCC
Ain
SP
MSC1157
ML2201
MCU
CLK
SP
XT
XT
STBY
VR
4.7 µF
GND
SEL
GND
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Co-relationship between output voltage and the value of a resistor for current-voltage conversion is shown in the
figure below. You may want to use the figure as a reference in determining a proper value for the resistor.
AOUT Voltage VS. AOUT Output Current at VDD = 5.0 V
RL = 500 Ω
RL = 200 Ω
2
4
5
4
3
2
RL = 5 kΩ
1
(1) At RL = 200 Ω
Proper waveform output shown.
Distorted waveform and obvious pop-noise shown.
Power
Down
Power
Down
Shifting to
Standby
Playing
Ready
(2) At RL = 5 kΩ
Shifting to
Standby
Power
Down
5
Shifting to
Standby
3
VAOUT (V)
Ready
1
Playing
0
Shifting to
Standby
0
Power
Down
IAOUT (mA)
6
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ML2201–XXX
A SAMPLE CHARACTERISTICS OF D/A CONVERTER OUTPUT CURRENT
A Sample Characteristics : Power Supply Voltage VS. AOUT Output Current
(Ta = 25°C, VAOUT = VDD, PCM at Max. level)
8
7
IAOUT (mA)
6
5
4
3
2
1
0
0
1
2
3
VDD (V)
4
5
6
A Sample Characteristics : Operating Temperature VS. AOUT Output Current
(VAOUT = VDD, PCM at Max. level)
8
7
IAOUT (mA)
6
VDD = 5 V
5
4
3
VDD = 3 V
2
1
0
–40
–20
0
20
40
60
80
100
Ta (°C)
A Sample Characteristics: Voltage on AOUT Pin VS. AOUT Output Current
(Ta = 25°C, PCM at Max. level)
6
VDD = 5 V
IAOUT (mA)
5
4
3
VDD = 3 V
2
1
0
0
1
2
3
4
5
VAOUT (V)
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NOTES ON USAGE
Type of the Built-in D/A Converter
ML2201 has the built-in current-output type D/A converter and thus the design of analog output circuit is different
from the one with a voltage-output type D/A converter (e.g. MSM6650 family).
ML2201’s D/A converter is designed as current attraction type with the same circuit configuration with the one
used on MSM9831. So, the analog output circuit is different from MSM9800 family that uses a current discharge
type D/A converter. (See the table below)
Product
D/A Converter Type
D/A Converter Output Circuit
ML2201
Current Output
N-MOS Open Drain
MSM9831
Current Output
N-MOS Open Drain
MSM9800 Family
Current Output
P-MOS Open Drain
MSM6650 Family
Voltage Output
—
A sample circuit of connecting ML2201 and an amplifier chip
A resistor for converting current to voltage
VDD
ML2201
AOUT
D/A Converter
AMP
GND
Direction of flowing current
A sample circuit of connecting MSM9800 family and an amplifier chip
VDD
Direction of flowing current
D/A Converter
AOUT
AMP
MSM9800 Family
GND
A resistor for converting current to voltage
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ML2201–XXX
PACKAGE DIMENSIONS
(Unit: mm)
SSOP8-P-44-0.65-K
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.044 TYP.
1/May.12,1999
Notes for Mounting the Surface Mount Type Packages
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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ML2201–XXX
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
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