MICRO-LINEAR ML2283CIP

May 1997
ML2280*, ML2283**
Serial I/O 8-Bit A/D Converters
GENERAL DESCRIPTION
FEATURES
The ML2280 and ML2283 are 8-bit successive
approximation A/D converters with serial I/O and
configurable input multiplexers with up to 4 input
channels.
■
Conversion time: 6µs
■
ML2280 capable of digitizing a 5V, 40kHz sine wave
■
Total unadjusted error with external
reference: ±1/2LSB or ±1LSB
■
Sample-and-hold: 375ns acquisition
■
0 to 5V analog input range with single 5V
power supply
■
2.5V reference provides 0 to 5V analog input range
■
No zero- or full-scale adjust required
■
Low power: 12.5mW MAX
■
Analog input protection: 25mA (min) per input
■
Differential analog voltage inputs (ML2280)
■
Programmable multiplexer with differential or single
ended analog inputs (ML2283)
■
0.3" width 8- or 14-pin DIP, or 8-Pin SOIC (ML2280)
■
Superior pin-compatible replacement for ADC0833
All errors of the sample-and-hold incorporated on the
ML2280 and ML2283 are accounted for in the analog-todigital converters accuracy specification.
The voltage reference can be externally set to any value
between GND and VCC, thus allowing a full conversion
over a relatively small voltage span if desired.
The ML2283 is an enhanced double polysilicon, CMOS,
pin-compatible second source for the ADC0833 A/D
converter. All parameters are guaranteed over temperature
with a power supply voltage of 5V ±10%.
* This Part Is Obsolete
** This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
ML2283
ML2281
CS
CONTROL
AND
TIMING
DI
INPUT
SHIFT-REGISTER
CLK
SARS
VIN+
4-BIT
DO
OUTPUT
SHIFT-REGISTER
A/D WITH SAMPLE & HOLD FUNCTION
+
SUCCESSIVE
+
APPROXIMATION
COMP
–
–
REGISTER
8pF
CS
DO
SE
CH0
VREF/2
VIN–
D/A
CONVERTER
VCC
CLK
OUTPUT
SHIFT-REGISTER
Σ
8pF
CONTROL
AND
TIMING
4-CHANNEL
S.E.
OR
2-CHANNEL
CH2
DIFF
MULTIPLEXER
CH1
DGND
A/D
CONVERTER
WITH
SAMPLE & HOLD
FUNCTION
CH3
GND
SHUNT
REGULATOR
AGND VREF/2
VCC
V+
1
ML2280, ML2283
PIN CONFIGURATION
ML2280
Single Differential Input
8-Pin PDIP
ML2280
Single Differential Input
8-Pin SOIC
CS
1
8
VCC
CS
1
8
VCC
VIN+
2
7
CLK
VIN+
2
7
VIN–
3
6
DO
VIN–
3
GND
4
5
VREF/2
GND
4
TOP VIEW
ML2283
4-Channel MUX
14-Pin PDIP
V+
1
8
VCC
CLK
CS
2
9
DI
6
DO
CH0
3
10
CLK
5
VREF/2
CH1
4
11
SARS
CH2
5
12
DO
CH3
6
13
VREF/2
DGND
7
14
AGND
TOP VIEW
TOP VIEW
PIN DESCRIPTION
NAME
FUNCTION
VCC
Positive supply. 5V ± 10%
DGND
Digital ground. 0 volts. All digital inputs and
outputs are referenced to this point.
AGND
Analog ground. The negative reference voltage
for A/D converter.
GND
Combined analog and digital ground.
CH0,
Analog inputs. Digitally selected to be single
VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential
input. Analog range = GND - VIN - VCC.
VREF/2
Reference. The analog input range is twice the
positive reference voltage value applied to this
pin.
V+
Input to the Shunt Regulator.
DO
Data out. Digital output which contains result
of A/D conversion. The serial data is clocked
out on falling edges of CLK.
2
NAME
FUNCTION
SARS
Successive approximation register status.
Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When CS = 1, SARS
is in high impedance state.
CLK
Clock. Digital input which clocks data in on
DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.
DI
Data input. Digital input which contains serial
data to program the MUX and channel
assignments.
CS
Chip select. Selects the chip for multiplexer
and channel assignment and A/D conversion.
When CS = 1, all digital outputs are in high
impedance state. When CS = 0, normal A/D
conversion takes place.
ML2280, ML2283
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Current into V+ ...................................................... 15mA
Supply Voltage, VCC ................................................. 6.5V
Voltage
Logic Inputs ........................................... –7 to VCC +7V
Analog Inputs ................................ –0.3V to VCC +0.3V
Input Current per Pin (Note 1) .............................. ±25mA
Storage Temperature ................................ –65°C to 150°C
Package Dissipation
at TA = 25°C (Board Mount) ............................. 800mW
Lead Temperature (Soldering 10 sec.)
Dual-In-Line Package (Molded) .......................... 260°C
Dual-In-Line Package (Ceramic) ......................... 300°C
OPERATING CONDITIONS
Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC
Temperature Range (Note 2) ................. TMIN - TA - TMAX
ML2280 BIP, ML2283 BIP ...................... –40°C to 85°C
ML2280 CIP, ML2283 CIP
ML2280 BCP, ML2283 BCP ...................... 0°C to 70°C
ML2280 CCP, ML2283 CCP
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = 5V ±10%, fCLK = 1.333MHz, and VREF/2 = 2.5V.
SYMBOL
PARAMETER
CONDITIONS
ML228XB
TYP
MIN
NOTE 3
MAX
MIN
ML228XC
TYP
NOTE 3
MAX
UNITS
±1
±2
LSB
LSB
20
kW
VCC
+0.05
V
±1/4
LSB
±1/4
LSB
±1/4
LSB
±1/4
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted
Error
VREF/2 = 2.5V
VREF/2 not connected
(Notes 4, 6)
Reference Input
Resistance
(Note 4)
Common-Mode
Input Range
(Notes 4, 7)
±1/2
±2
10
15
GND
–0.05
DC Common-Mode Common mode voltage
Error
voltage GND to VCC/2
(Note 5)
±1/16
AC Common-Mode Common mode voltage
Error
GND to VCC,
0 to 50kHz (Note 5)
DC Power Supply
Sensitivity
VCC = 5V ±10%
VREF - VCC +0.1V
(Note 5)
AC Power Supply
Sensitivity
100mVP-P, 25kHz sine
on VCC (Note 5)
Change in Zero
Error from VCC=5V
to Internal Zener
Operation
15mA into V+
VCC = N.C.
VREF/2 = 2.5V (Note 5)
VZ
Internal Diode
Regulated Breakdown (at V+)
15mA into V+
V+
Input Resistance
(Note 4)
20
10
VCC
+0.05
GND
–0.05
±1/4
15
±1/16
±1/4
±1/32
±1/4
±1/32
±1/4
20
±1/2
±1/2
LSB
6.9
6.9
V
35
kW
35
20
3
ML2280, ML2283
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Continued)
ML228XB
TYP
MIN
NOTE 3
CONDITIONS
MAX
MIN
ML228XC
TYP
NOTE 3
MAX
UNITS
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
IOFF
Off Channel
Leakage Current
On channel = VCC
Off channel = 0V
(Notes 4, 8)
–1
On channel = 0V
Off channel = VCC
(Notes 4, 8)
ION
On Channel
Leakage Current
On channel = 0V
Off channel = VCC
(Notes 4, 8)
PARAMETER
µA
+1
+1
–1
On channel = VCC
Off channel = 0V
(Notes 4, 8)
SYMBOL
–1
–1
µA
+1
CONDITIONS
+1
MIN
µA
TYP
NOTE 3
MAX
µA
UNITS
DIGITAL AND DC CHARACTERISTICS
4
VIN(1)
Logical “1” Input Voltage
(Note 4)
VIN(0)
Logical “0” Input Voltage
(Note 4)
IIN(1)
Logical “1” Input Current
VIN = VCC (Note 4)
IIN(0)
Logical “0” Input Current
VIN = 0V (Note 4)
–1
µA
VOUT(1
Logical “1” Output Voltage
IOUT = –2mA (Note 4)
4.0
V
VOUT(0)
Logical “0” Output Voltage
IOUT = 2mA (Note 4)
IOUT
HI-Z Output Current
VOUT = 0V (Note 4)
VOUT = VCC
–1
–6.5
ISOURCE
Output Source Current
VOUT = 0V (Note 4)
ISINK
Output Sink Current
VOUT = VCC (Note 4)
ICC
Supply Current
(Note 4)
2.0
V
0.8
V
1
µA
0.4
V
1
µA
µA
mA
1.3
8.0
mA
2.5
mA
ML2280, ML2283
ELECTRICAL CHARACTERISTICS
SYMBOL
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
NOTE 3
MAX
UNITS
1333
kHz
AC ELECTRICAL CHARACTERISTICS
fCLK
Clock Frequency
tACQ
Sample-and-Hold Acquisition
tC
Conversion Time
SNR
(Note 4)
10
1/2
1/fCLK
Not including MUX adddressing time
8
1/fCLK
Signal to Noise Ratio
ML2280
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING @ 120kHz). Noise is sum of all
nonfundamental components up to 1/2
of fSAMPLING (Note 11)
47
dB
THD
Total Harmonic Distortion
ML2280
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING @ 120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
–60
dB
IMD
Intermodulation Distortion
ML2280
VIN = fA + fB. fA = 40kHz, 2.5V sine.
fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz
(fSAMPLING @ 120kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental (Note 11)
–60
dB
Clock Duty Cycle
(Notes 4, 9)
40
tSET-UP
CS Falling Edge or Data Input
Valid to CLK Rising Edge
(Note 4)
130
ns
tHOLD
Data Input Valid after
CLK Rising Edge
(Note 4)
80
ns
tPD1,
tPD0
CLK Falling Edge to Output
Data Valid
CL = 100pF (Note 4 & 10)
Data MSB first
Data LSB first
t1H,
t0H
Rising Edge of CS to Data
Output and SARS Hi-Z
60
%
90
50
200
110
ns
ns
CL = 10pF, RL = 10kW (see high impedance
test circuits) (Note 5)
40
90
ns
CL = 100pF, RL = 2kW (Note 5)
80
160
ns
CIN
Capacitance of Logic Input
5
pF
COUT
Capacitance of Logic Outputs
5
pF
Note 1:
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND < or VIN > VCC) the absolute value of current at that pin should be limited to
25mA or less.
Note 2:
0°C to 70°C and –40°C to 85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3:
Typicals are parametric norm at 25°C.
Note 4:
Parameter guaranteed and 100% tested.
Note 5:
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6:
Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7:
For VIN– • VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V IN or VREF does not exceed the supply voltage by more than 50mV, the output code will
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial
tolerance and loading.
Note 8:
Leakage current is measured with the clock not switching.
Note 9:
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 10: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time..
Note 11: Because of multiplexer addressing, test conditions for the ML2283 is VIN = 30kHz, 5V sine (fSAMPLING ª 89kHz)
5
ML2280, ML2283
t1H
t1H
tr
VCC
DATA
OUTPUT
90%
50%
10%
CS
RL
CL
GND
t1H
DO AND
SARS OUTPUTS
VOH
90%
GND
t0H
t0H
VCC
tr
VCC
90%
50%
10%
CS
RL
GND
DATA
OUTPUT
t0H
CL
DO AND
SARS OUTPUTS
VCC
10%
VOL
Figure 1. High Impedance Test Circuits and Waveforms
Data Input Timing
Data Output Timing
CLK
CLK
tPD0, tPD1
tSET-UP
CS
DATA
OUT (DO)
tSET-UP
tHOLD
tSET-UP
tHOLD
DATA
IN (DI)
SE
ML2281 Start Conversion Timing
CLK
tSET-UP
CS
START CONVERSION
DO
BIT 7
(MSB)
Figure 2. Timing Diagrams
6
tPD0, tPD1
BIT 6
ML2280, ML2283
ML2280 Timing
1
2
3
4
5
6
7
8
9
10
4
3
2
1
0
(LSB)
11
CLOCK (CLK)
tSET-UP
CHIP SELECT (CS)
tC
DATA OUT (DO)
*
HI-Z
7
(MSB)
SAMPLE & HOLD
ACQUISITION (tACQ)
6
5
HI-Z
*LSB FIRST OUTPUT NOT AVAILABLE ON ML2280
ML2283 Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CLOCK (CLK)
tSET-UP
CHIP SELECT (CS)
OUTPUT DATA
ADDRESS MUX
START
BIT
ODD/SIGN
SELECT
BIT 0
DATA IN (DI)
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION
SGL/DIF
SAR STATUS (SARS)
SELECT
BIT 1
A/D CONVERSION IN PROCESS
HI-Z
HI-Z
MSB FIRST DATA
DATA OUT (DO)
LSB FIRST DATA
HI-Z
SAMPLE & HOLD
ACQUISITION (tACQ)
HI-Z
7
6
(MSB)
5
4
3
2
1
0
1
2
3
4
5
6
7
Figure 2. Timing Diagrams (Continued)
7
ML2280, ML2283
1.0
LINEARITY ERROR (LSB)
VCC = 5V
VREF = 5V
0.75
0.5
125 C
–55 C
0.25
25 C
0
0
0.01
0.1
1
CLOCK FREQUENCY (MHz)
Figure 3. Linearity Error vs fCLK
START
1
S
LS193
LOAD
VCC = 5V
fCLK = 1.333MHz
A B
B0
COUNT
C D DOWN
TMS320
SERIES
D
5V
LINEARITY ERROR (LSB)
Q
R
Q
Q
0.75
D
Q
DSP
Q
D
Q
Q
0.5
ML2280
125 C
FSR
CLK
CLK
VIN+
VIN–
–55 C
CS
DO
DR
CLK
25 C
0.25
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
START
0
CS
0
1
2
3
4
5
FSR
VREF (VDC)
Figure 4. Linearity Error vs VREF Voltage
8
DO
HI-Z
D7
D6
D5
D4
D3
D2
D1
D0
HI-Z
Figure 5. Unadjusted Offset Error vs VREF Voltage
ML2280, ML2283
DI*
CS
13
2
R
START
R
R
R
5-BIT SHIFT-REGISTER
ODD/
SGL/DIF
SELECT 1
SIGN
D
R
CS
SELECT 0 C
START
CLK
16
MUX
ADDRESS
VCC
CH0*
3
CS
+
SARS*
11
Σ
Tx
–
CH1
CH2*
4
TIME
DELAY
DSTART 2
ANALOG
MUX
(EQUIVALENT)
5
R
Q
D
D
Q
C
R
D
Q
C
R
–
6
CS
COMP
VCC
V+*
C
9
14
7V SHUNT
REGULATOR
INPUT V
CC
13
TO
16
INTERNAL
17
CIRCUITS
18
EOC
B7
R
B6
SAR
LOGIC
AND
LATCH
LADDER
AND
DECODER
8
DEOC
CS
CS
C
R
Q
10
DO
D
9-BIT
SHIFT
REGISTER
B4
B3
B2
B1
B0
EOC
COMP
AGND*
C
B5
R
TO INTERNAL
CIRCUITRY
1
DGND*
R
DSTART 1
CS
CS
VCC
VREF/2
CS
+
C
CH3*
C
INPUT PROTECTION—ALL LOGIC INPUTS
LSB FIRST
MSB FIRST
* SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH ML2280.
PARALLEL XFR
TO SHIFT REGISTER
Figure 6. ML2288 Functional Block Diagram
9
ML2280, ML2283
FUNCTIONAL DESCRIPTION
SINGLE-ENDED MUX MODE
MUX ADDRESS
MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample data
comparator structure which provides for a differential analog
input to be converted by a successive approximation routine.
The actual voltage converted is always the difference
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned “+” input is less than the “–”
input, the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized
to provide multiple analog channels with software
configurable single ended, differential, or pseudo
differential options.
A particular input configuration is assigned during the
MUX addressing sequence, prior to the start of a
conversion. The MUX address selects which of the analog
inputs are to be enabled and whether this input is single
ended or differential. In the differential case, it also assigns
the polarity of the analog channels. Differential inputs are
restricted to adjacent channel pairs. For example, channel
0 and channel 1 may be selected as a different pair but
channel 0 or channel 1 cannot act differentially with any
other channel. In addition to selecting the differential
mode, the sign may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is
illustrated by the MUX addressing codes shown in Table 1.
SGL/ ODD/
DIF SIGN
SELECT
1
0
+
1
0
0
1
0
1
1
1
0
1
1
1
SGL/ ODD/
DIF SIGN
+
+
CHANNEL#
SELECT
1
0
1
0
0
0
+
–
0
0
1
0
1
0
–
+
0
1
1
2
3
+
–
–
+
Table 1. ML2283 MUX Addressing 4 Single-Ended
or 2 Differential Channel
2 Differential
4 Single-Ended
0
+
+ (–)
0, 1
2
+
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A
channel can be treated as a single-ended, ground
referenced input for one conversion; then it can be
reconfigured as part of a differential channel for another
conversion. Figure 7 illustrates these different input modes.
3
+
– (+)
+ (–)
2, 3
– (+)
AGND
Mixed Mode
DIGITAL INTERFACE
10
3
+
MUX ADDRESS
+
A clock is applied to the CLK input. On each rising edge
of the clock, the data on DI is clocked into the MUX
address shift register. The start bit is the first logic “1” that
appears on the DI input (all leading edge zeros are
ignored). After the start bit, the device clocks in the next 2
to 4 bits for the MUX assignment word.
2
DIFFERENTIAL MUX MODE
1
A conversion is initiated when CS is pulsed low. This line
must me held low for the entire conversion. The converter is
now waiting for a start bit and its MUX assignment word.
1
COM is internally tied to AGND
The MUX address is shifted into the converter via the DI
input. Since the ML2280 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The block diagram and timing diagrams in Figures 2-5
illustrate how a conversion sequence is performed.
CHANNEL#
+
0, 1
2
+
3
+
AGND
Figure 7. Analog Input Multiplexer Functional Options
for ML2288
ML2280, ML2283
REFERENCE
When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1/2
clock period is used for sample & hold settling through the
selected MUX channels. The SAR status output goes high
at this time to signal that a conversion is now in progress
and the DI input is ignored.
The ML2280 and ML2283 are intended primarily for use in
circuits requiring absolute accuracy. In this type of system,
the analog inputs vary between very specific voltage limits
and the reference voltage for the A/D converter must remain
stable with time and temperature. For ratiometric
applications, see the ML2281 and ML2284 which have a
VREF input that can be tied to VCC.
The DO output comes out of High impedance and
provides a leading zero for this one clock period.
The voltage applied to the VREF/2 pin defines the voltage
span of the analog input (the difference between VIN+ and
VIN–) over which the 256 possible output codes apply. A
full-scale conversion (an all 1s output code) will result when
the voltage difference between a selected “+”input and “–”
input is approximately twice the voltage at the VREF/2 pin.
This internal gain of 2 from the applied reference to the fullscale input voltage allows biasing a low voltage reference
diode from the 5VDC converter supply. To accommodate a
5V input span, only a 2.5V reference is required. The output
code changes in accordance with the following equation:
When the conversion begins, the output of the
comparator, which indicates whether the analog input is
greater than or less than each successive voltage from the
internal DAC, appears at the DO output on each falling
edge of the clock. This data is the result of the conversion
being shifted out (with MSB coming first) and can be read
by external logic or µP immediately.
After 8 clock periods, the conversion is completed. The SAR
status line returns low to indicate this 1/2 clock cycle later.
 V (+) − VIN(−) 
Output Code = 256  IN

 2(VREF / 2) 
The serial data is always shifted out MSB first during the
conversion. After the conversion has been completed, the
data can be shifted out a second time with LSB first. The
2280 data is shifted out only once, MSB first.
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term VREF/2 is
the voltage to ground.
All internal registers are cleared when the CS input is
high. If another conversion is desired, CS must make a
high to low transition followed by address information.
The VREF/2 pin is the center point of a two resistor divider
(each resistor is 10kW) connected from VCC to ground. Total
ladder input resistance is the parallel combination of these
two equal resist. As show in Figure 8, a reference diode
requiring an external biasing resistor if its current
requirements meet the indicated level.
The DI input and DO output can be tied together and
controlled through a bidirectional µP I/O bit with one
connection. This is possible because the DI input is only
latched in during the MUX addressing interval while the
DO output is still in the high impedance state.
The minimum value of VREF/2 can be quite small (See
Typical Performance Curves) to allow direct conversions of
transducer outputs providing less than a 5V output span.
Particular care must be taken with regard to noise pickup,
circuit layout and system error voltage sources when
operating with a reduced span due to the increased
sensitivity of the converter (1LSB equals VREF/256).
VCC
5V
VCC
10kΩ
10kΩ
VREF/2
ML2280
ML2283
5V
+
ML2280
ML2283
IZ
10kΩ
VREF/2
10kΩ
VZ
1.2V
GND
2.5V
GND
–
VFULL-SCALE ≅ 2.4V
VFULL-SCALE ≅ 5.0V
NOTE: NO EXTERNAL BIASING RESISTOR NEENED IF: VZ <
VCC/2 – VZ
VCC
AND IZ min. <
2
5kΩ
Figure 8. Reference Biasing
11
ML2280, ML2283
ANALOG INPUTS AND SAMPLE/HOLD
ZERO ERROR ADJUSTMENT
An important feature of the ML2280 and ML2283 is that
they can be located at the source of the analog signal and
then communicate with a controlling µP with just a few
wires. This avoids bussing the analog inputs long distances
and thus reduces noise pickup on these analog lines.
However, in some cases, the analog inputs have a large
common mode voltage or even some noise present along
with the valid analog signal.
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, VIN MIN is not ground,
a zero offset can be done. The converter can be made to
output 00000000 digital code for this minimum input
voltage by biasing any VIN– input at this VIN MIN value.
This utilizes the differential mode operation of the A/D.
The differential input of these converters reduces the effects
of common mode input noise. Thus, if a common mode
voltage is present on both “+” and “–” inputs, such as 60Hz,
the converter will reject this common mode voltage since it
only converts the difference between “+” and “–” inputs.
The ML2280 and ML2283 have a true sample and hold
circuit which samples both “+” and “–” inputs
simultaneously. This simultaneous sampling with a true S/H
will give common mode rejection and AC linearity
performance that is superior to devices where the two input
terminals are not sampled at the same instant and where
true sample and hold capability does not exist. Thus, these
A/D converters can reject AC common mode signals from
DC-50kHz as well as maintain linearity for signals from DC50kHz.
The signal at the analog input is sampled during the interval
when the sampling switch is closed prior to conversion start.
The sampling window (S/H acquisition time) is 1/2 CLK
period wide and occurs 1/2 CLK period before DO goes
from high impedance to active low state. When the
sampling switch closes at the start of the S/H acquisition
time, 8pF of capacitance is thrown onto the analog input. 1/
2 CLK period later, the sampling switch is opened and the
signal present at the analog input is stored. Any error on the
analog input at the end of the S/H acquisition time will
cause additional conversion error. Care should be taken to
allow adequate charging or settling time from the source.
If more charging or settling time is needed to reduce these
analog input errors, a longer CLK period can be used.
For latchup immunity each analog input has dual diodes to
the supply rails, and a minimum of ±25mA (±100mA
typically) can be injected into each analog input without
causing latchup.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be
measured by grounding the VIN– input and applying a
small magnitude positive voltage to the VIN+ input. Zero
error is the difference between the actual DC input
voltage which is necessary to just cause an output digital
code transition from 00000000 to 00000001 and the ideal
1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC).
FULL-SCALE ADJUSTMENT
The full-scale adjustment can be made by applying a
differential input voltage which is 1-1/2 LSB down from
the desired analog full-scale voltage range and then
adjusting the magnitude of the VREF input or VCC for a
digital output code which is just changing from 11111110
to 11111111.
ADJUSTMENT FOR AN ARBITRARY ANALOG
INPUT VOLTAGE RANGE
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero
reference should be properly adjusted first. A VIN+ voltage
which equals this desired zero reference plus 1/2 LSB
(where the LSB is calculated for the desired analog span,
1 LSB = analog span/256) is applied to selected “+” input
and the zero reference voltage at the corresponding “–”
input should then be adjusted to just obtain the 00000000
to 00000001 code transition.
The full-scale adjustment should be made by forcing a
voltage to the VIN+ input which is given be:
 (V
− VMIN) 
VIN + fs adjust = VMAX − 1.5 ×  MAX

256


where
VMAX = high end of the analog input range
VMIN = low end (offset zero) of the analog range
The VREF or VCC voltage is then adjusted to provide a
code change from 11111110 to 11111111.
12
ML2280, ML2283
SHUNT REGULATOR
A unique feature of the ML2283 is the inclusion of a shunt
regulator connected from V+ terminal to ground which
also connects to the VCC terminal (which is the actual
converter supply) through a silicon diode as shown in
Figure 8. When the regulator is turned on, the V+ voltage
is clamped at 11VBE set by the internal resistor ratio. The
typical I-V of the shunt regulator is shown in Figure 9.
12V
I+
VCC
V+
I+→
CURRENT LIMITING
RESISTOR, I+ ≤15mA
It should be noted that before V+ voltage is high enough
to turn on the shunt regulator (which occurs at about
5.5V), 35kW resistance is observed between V+ and GND.
When the shunt regulator is not used, V+ pin should be
either left floating or tied to GND. The temperature
coefficient of the regulator is –22mV/°C.
28.8kΩ
15mA
3.2kΩ
3.2kΩ
GND
SLOPE = 1
35kΩ
V+
5.5V 6.9V
Figure 9. Shunt Regulator
Figure 10. I-V Characteristic of the Shunt Regulator
13
ML2280, ML2283
APPLICATIONS
CH0
ML2283
CH3
CS
P13
CLK
P12
DI
P11
DO
P10
8051
8051 Interface and Controlling Software
MNEMONIC
START:
ANL
MOV
MOV
P1, #0F7H
B, #5
A, #ADDR
;SELECT A/D (CS = 0)
;BIT COUNTER ¨ 5
;A ¨ MUX BIT
LOOP 1: RRC
JC
A
ONE
;CY ¨ ADDRESS BIT
;TEST BIT
;BIT = 0
ZERO:
ANL
SJMP
P1, #0FEH
CONT
;DI ¨ 0
;CONTINUE
;BIT = 1
ONE:
ORL
P1, #1
;D1 ¨ 1
CONT:
ACALL
DJNZ
ACALL
MOV
PULSE
B, LOOP 1
PULSE
B, #8
;PULSE SK 0 Æ 1 Æ 0
;CONTINUE UNTIL DONE
;EXTRA CLOCK FOR SYNC
;BIT COUNTER ¨ 8
LOOP 2: ACALL
MOV
RRC
RRC
MOV
RLC
MOV
DJNZ
PULSE
A, P1
A
A
A, C
A
C, A
B, LOOP 2
;PULSE SK 0 Æ 1 Æ 0
;CY ¨ DO
RETI
PULSE:
14
INSTRUCTION
;A ¨ RESULT
;A(0) BIT ¨ AND SHIFT
;C ¨ RESULT
;CONTINUE UNTIL DONE
;PULSE SUBROUTINE
ORL
NOP
ANL
RET
P1, #04
P1, #0FBH
;SK ¨ 1
;DELAY
;SK ¨ 0
ML2280, ML2283
APPLICATIONS
(Continued)
MUX ADDRESS
5VDC
51kΩ (4)
START BIT
SGL/DIF
11
15
CLK
12
13
CLK INT
2
START
3
4
5
6
8
GND
7
NC
DO
INPUT SHIFT REGISTER
74HC165
CLK
1 SHIFT/
LOAD SIN
10
+
14
PARALLEL INPUTS
DO
VCC
9
14
NC
5VDC
5VDC (OR VIN)
1kΩ
1kΩ
6
START
5 VDC
0.01µF
5
3
2
10kΩ
3
1
0
13
D1
ANALOG INPUTS
12
CLK
NC
1kΩ
4
2
CS
CLK
1kΩ
5VDC
ML2283
11
SARS
51kΩ
VREF/2
9
CLK
AGND
8
DGND
7
VCC
V+
1
DO
14
14
2.5V
CLOSE TO
START THE
A/D CONVERSION
10kΩ
0.001µF
7
CLOCK
GENERATOR
9
CLR
14
VCC
SI A
GND
1
+ 10µF
OUTPUT SHIFT REGISTER
74HC164
8
CLK
CLK
Q
2
CLK
QH
13
SI B
QA
12
11
10
6
5
4
3
D
CLK
1.3kΩ (8)
1/2 74HC74
MSB
DATA DISPLAY
LSB
5VDC
ML2283 “Stand-Alone” or Evaluation Circuit
15
ML2280, ML2283
APPLICATIONS
(Continued)
VCC
(5VDC)
VCC
(5 VDC)
15VDC
OP
AMP
+
VIN (+)
RSET
VCC
600Ω
–
+
10µF
VIN (+)
VCC
+
10µF
–15VDC
RL
ML2280
ML2283
7.5kΩ
5VDC
10kΩ
TA MIN
ADJ.
VIN (–)
5kΩ
TA MAX
ADJ.
VREF/2
VIN (–)
DIODE CLAMPING IS NOT NEEDED
IF CURRENT IS LIMITED TO 25mA
Protecting the Input
Low-Cost Remote Temperature Sensor
VCC
(5VDC)
0.1Ω
→ ILOAD
(2A FULL-SCALE)
VCC
(5VDC)
100Ω
VCC
VIN (–)
240kΩ
2kΩ
9.1kΩ
ML2280
100Ω
ZERO
ADJ.
LOAD
+
10µF
2.5V
–
VREF/2
+
VIN (+)
+
1µF
3kΩ
1kΩ
FS
ADJ.
120kΩ
Digitizing a Current Flow
VCC
(5VDC)
20kΩ
VIN (+)
1kΩ
ZERO
ADJ.
VCC
VIN (–)*
3kΩ
+
10µF
ML2280
VREF/2
16kΩ
–
VXDR
0.35 VCC
+
XDR
+
1µF
*VIN (–) = 0.15VCC
15% OF VCC ≤ VXDR ≤ 85% OF VCC
Operating with Ratiometric Transducers
16
1kΩ
FS
ADJ.
8.2kΩ
ML2280, ML2283
APPLICATIONS
(Continued)
VCC
(5VDC)
VCC
(5VDC)
VIN (+)
+
VCC
+
10µF
VIN
VIN (+)
VCC
+
10µF
ML2280
1kΩ
VIN (–)
1kΩ
–
VIN (–)
VREF/2
+
1.2kΩ
2kΩ
10kΩ
FS
ADJ.
ML2280
10kΩ
FS
ADJ.
300Ω
SETS ZERO
CODE VOLTAGE
+
+
VIN
330Ω
1µF SET FOR 1.5V
VREF/2
1.5
+
1µF
330Ω
SETS
VOLTAGE SPAN
1.2V
1.2V
1kΩ
2VDC
ZERO ADJ.
2.7kΩ
Span Adjust: 0V - VIN - 3V
Zero-Shift and Span Adjust: 2V - VIN - 5V
330Ω
10V
5.1V
6.8kΩ
1kΩ
GAIN
STRAIN GUAGE
LOAD CELL
300Ω/30mV FS
VCC
+
VREF/2
–
CLK
DUAL
1.3kΩ
10kΩ
ML2280
1MΩ
CS
+
–IN
–
DUAL
DO
+IN
GND
1MΩ
• USES ONE MORE WIRE THAN LOAD CELL ITSELF
• TWO MINI-DIPs COULD BE MOUNTED INSIDE
LOAD CELL FOR DIGITAL OUTPUT TRANSDUCER
• ELECTRONIC OFFSET AND GAIN TRIMS RELAX
MECHANICAL SPECS FOR GUAGE FACTOR AND OFFSET
• LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY
FOR HIGH NOISE IMMUNITY
20kΩ
10V
10kΩ
OFFSET
20kΩ
Digital Load Cell
17
ML2280, ML2283
APPLICATIONS
(Continued)
START
S
LS193
LOAD
A B
B0
COUNT
C D DOWN
Q
R
TMS320
SERIES
D
5V
Q
Q
D
Q
DSP
Q
D
Q
Q
ML2280
VIN+
VIN–
FSR
CLK
CLK
CS
DO
DR
CLK
Sampling Rate 111kHz, Data Rate 1.33MHz
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
START
CS
FSR
DO
HI-Z
D7
D6
D5
D4
D3
D2
Interfacing ML2280 to TMS320 Series
18
D1
D0
HI-Z
ML2280, ML2283
PHYSICAL DIMMENSIONS inches (millimeters)
Package: P08
8-Pin PDIP
0.365 - 0.385
(9.27 - 9.77)
0.055 - 0.065
(1.39 - 1.65)
8
0.240 - 0.260 0.299 - 0.335
(6.09 - 6.60) (7.59 - 8.50)
PIN 1 ID
1
0.020 MIN
(0.51 MIN)
(4 PLACES)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.020
(0.40 - 0.51)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
SEATING PLANE
Package: S08
8-Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
PIN 1 ID
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
SEATING PLANE
19
ML2280, ML2283
PHYSICAL DIMMENSIONS inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.25)
PIN 1 ID
1
0.070 MIN
(1.77 MIN)
(4 PLACES)
0.050 - 0.065
(1.27 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0º - 15º
ORDERING INFORMATION
PART NUMBER
ALTERNATE
PART NUMBER
TOTAL
UNADJUSTED ERROR
TEMPERATURE
RANGE
PACKAGE
SINGLE ANALOG INPUT, 8-PIN PACKAGE
ML2280BIP (Obs)
ML2280BIS (Obs)
ML2280BCP (Obs)
ML2280BCS (Obs)
ML2280CIP (Obs)
ML2280CIS (Obs)
ML2280CCP (Obs)
ML2280CCS (Obs)
±1/2 LSB
±1 LSB
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°CQ
0°C to 70°C
0°C to 70°C
8-Pin DIP (P08)
8-Pin SOIC (S08)
8-Pin DIP (P08)
8-Pin SOIC (S08)
8-Pin DIP (P08)
8-Pin SOIC (S08)
8-Pin DIP (P08)
8-Pin SOIC (S08)
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
14-Pin DIP (P014)
14-Pin DIP (P014)
14-Pin DIP (S014)
14-Pin DIP (P014)
TWO ANALOG INPUTS, 14-PIN PACKAGE
ML2283BIP (Obs)
ML2283BCP (Obs)
ML2283CIP (Obs)
ML2283CCP (EOL)
ADC0833CCN
ADC0833BCN
ADC0833BCN
ADC0833CCN
±1/2 LSB
±1 LSB
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
20
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS2280_83-01