Micro Linear ML4622CS Fiber optic data quantizer Datasheet

January 1997
ML4622, ML4624
Fiber Optic Data Quantizer
GENERAL DESCRIPTION
FEATURES
The ML4622 and ML4624 data quantizers are low noise,
wideband, bipolar monolithic ICs designed specifically for
signal recovery applications in fiberoptic receiver systems.
They contain a wideband limiting amplifier which is
capable of accepting an input signal as low as 2mVP-P
with a 55dB dynamic range. This high level of sensitivity
is achieved by using a DC restoration feedback loop
which nulls any offset voltage produced in the limiting
amplifier.
■
■
The output stage is a high speed comparator circuit with
both TTL and ECL outputs. An enable pin is included for
added control.
The Link Detect circuit provides a Link Monitor function
with a user selectable reference voltage. This circuit
monitors the peaks of the input signal and provides a
logic level output indicating when the input falls below
an acceptable level. This output can be used to disable
the quantizer and/or drive an LED, providing a visible link
status.
Data rates up to 40MHz or 80MBd
Can be powered by either +5V providing TTL or raised
ECL level outputs or –5.2V providing ECL levels
■ Low noise design: 25µV RMS over bandwidth
■ Adjustable Link Monitor function with hystersis
■ Wide 55dB input dynamic range
■ Low power design
■ ML4624 is pin compatible with the ML4621
APPLICATIONS
■
■
■
IEEE 802.3 10BASE-FL Receiver
IEEE 802.5 fiber optic token ring, 4 and 16mbps
Fiber Optic Data Communications and
Telecommunications Receivers
ML4622/ML4624 BLOCK DIAGRAM
CF1
CF2
ECL+
ECL–
BIAS
VIN+
ECL
CMP
AMP
VIN–
TTL
CMP
TTL OUT
CMP ENABLE
∫
VCC TTL*
VDC
VCC
GND
VREF
VTHADJ
GND TTL
REF
THRESH
GEN
LINK DETECT
TTL LINK MON
CTIMER
*ML4624 ONLY
1
ML4622, ML4624
PIN CONNECTIONS
ML4622
16-Pin DIP or
SOIC (Narrow)
ML4624
24-Pin Narrow DIP
NC
1
24
VCC
TTL LINK MON
2
23
NC
CMP ENABLE
3
22
NC
ML4624
28-Pin PCC
CMP ENABLE
TTL LINK MON
NC
NC VCC NC NC
TTL LINK MON
1
16
CMP ENABLE
GND
2
15
VTHADJ
VIN–
4
21
CTIMER
VIN–
5
27 26
25
VIN–
3
14
VREF
VIN+
5
20
VREF
VIN+
6
24
CTIMER
CTIMER
VDC
6
19
VTHADJ
NC
7
23
VREF
7
18
GND
VDC
8
22
VTHADJ
TTL OUT
CF2
9
21
GND
CF1
10
20
TTL OUT
NC
11
12
VIN+
4
13
VDC
5
12
VCC
CF2
CF2
6
11
TTL OUT
CF1
8
17
CF1
7
10
ECL+
NC
9
16
VCC TTL
ECL–
NC
10
15
GND TTL
NC
11
14
ECL+
NC
12
13
ECL–
GND TTL
8
9
TOP VIEW
4
3
13
2
1
14 15
NC NC NC NC
28
19
17 18
16
ECL+
ECL–
TOP VIEW
2
GND TTL
NC
VCC TTL
ML4622, ML4624
PIN DESCRIPTION
NAME
TTL LINK MON
CMP ENABLE
VIN–
FUNCTION
TTL Link Monitor output. Signal is
low when the VIN+, VIN– inputs
exceed the minimum threshold,
which is set by a voltage on the
VTH ADJ pin. Signal is high when the
input signal level is below the
threshold. Capable of driving a 10mA
LED indicator. This pin can be tied to
CMP ENABLE.
A low voltage at this TTL input pin
enables both the ECL and the TTL
outputs. A high TTL voltage disables
the comparator output with ECL+
high, ECL– low, and TTL OUT high.
This input pin should be capacitively
coupled to the input source or to
filtered ground. (The input resistance
is approximately 1.6kΩ.)
VIN+
This input pin should be capacitively
coupled to the input source or to
filtered ground. (The input resistance
is approximately 1.6kΩ.)
ECL–
The ECL comparator negative output.
Has internal pull down resistor.
External pull downs are not required
unless driving a large capacitive
load.
ECL+
The ECL comparator positive output.
Has internal pull down resistor.
External pull downs are not required
unless driving a large capacitive
load.
GND TTL
The negative supply for the TTL
comparator stage. If the TTL output is
not necessary, connect GND TTL
to VCC.
NAME
FUNCTION
VCC TTL
The positive supply for the TTL
comparator stage. If the TTL output is
not necessary, connect VCC TTL to
VCC . (ML4624 only)
TTL OUT
TTL data output.
VDC
An external capacitor on this pin
integrates an error signal which nulls
the offset of the input amplifier. If the
DC feedback loop is not being used,
this pin should be connected to VREF.
CF2
A capacitor from this pin to CF1
controls the maximum bandwidth of
the amplifier.
CF1
Connect to CF2 through a capacitor.
GND
Negative supply. Connect to –5.2V
for ECL operation, or to ground for
TTL or raised ECL operation.
V THADJ
This input pin sets the link monitor
threshold.
V REF
A 2.5V reference with respect to
GND.
CTIMER
A capacitor from this pin to VCC
determines the Link Monitor
response time.
VCC
Positive supply. Connect to ground
for negative ECL operation, or to 5V
for TTL or raised ECL operation.
3
ML4622, ML4624
ABSOLUTE MAXIMUM RATINGS
VCC – GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0
VCC TTL – GND TTL . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0
Inputs/Outputs GND . . . . . . . . . . . . . . . . . . . –0.3 to VCC +0.3
Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec.) . . . . . . . . . . . . . . +260°C
ML4622, ML4624 ELECTRICAL CHARACTERISTICS (Note 2 and 3)
Over recommended operating conditions of TA = 0°C to 70°C for commercial temperature range, TA = –40°C to +85°C for
industrial temperature range, VCC = 5V ± 10%, GND = 0V unless otherwise noted (Note 1).
SYMBOL
PARAMETER
ICC1
TYP
MAX
VCC Supply Current
(TTL Output Disabled)
35
45
mA
GND TTL = VCC
ICC2
VCC Supply Current
(TTL Output Enabled)
55
70
mA
GND TTL = GND
VREF
Reference Voltage
2.50
2.60
V
IVREF
VREF Output Source Current
5
mA
AV
Amplifier Gain
VIN
Input Signal Range
VTHADJ
Range
External Voltage at VTHADJ
to set VTH
VOS
Input Offset
3
mV
VDC = VREF (DC loop inactive)
EN
Input Referred Noise
25
µV
50MHz BW
BW
3dB Bandwidth
45
MHz
RIN
Input Resistance
IVTHADJ
Input Bias Current of VTHADJ
tPDTTL
Propagation Delay
15
ns
From VIN+, VIN– to TTL Out
VIN = 10mVP–P
tPDECL
Propagation Delay
11
ns
From VIN+, VIN– to ECL+, ECL–
VIN = 10mVP–P
V
VCC TTL = 5V, IOH = –50µA
V
VCC TTL = 5V, IOL = 2mA
TTL VOH
MIN
2.40
100
1600
mVP–P
0.5
2.6
V
1
1.6
2.5
kΩ
–200
10
+200
µA
2.4
0.55
2.0
TTL VIL
CONDITIONS
V/V
2
TTL VOL
TTL VIH
UNITS
VIN+, VIN–
V
0.8
V
TTL IIH
–50
50
µA
VIH = 2.4V
TTL IIL
–1.6
0
mA
VIH = 0.4V
4
ML4622, ML4624
ML4622, ML4624 ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions of TA = 0°C to 70°C for commercial temperature range, TA = –40°C to +85°C for
industrial temperature range, VCC = 5V ± 10%, GND = 0V unless otherwise noted.
SYMBOL
PARAMETER
VTH
Input Threshold Voltage
ML4622
ML4624
MIN
4
5
Hystersis
VCM
Common mode voltage
on VIN+, VIN–
ECLVOH
Output High Voltage at
ECL+, ECL–
VCC – 1.06
Output Low Voltage at
ECL+, ECL–
VCC – 1.89
ECLVOL
TYP
5
6
MAX
UNITS
CONDITIONS
6
7
mVP–P
mVP–P
VTHADJ = VREF (note 4)
VTHADJ = VREF (note 4)
20
%
1.65
V
VCC – 0.7
VCC – 0.6
(note 5)
With 200Ω load tied to
VCC – 2V
VCC – 1.62
VCC – 1.56
(note 5)
With 200Ω load tied to
VCC – 2V
Note 1: Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
Note 2: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 3: Low Duty Cycle pulse testing is performed at TA.
Note 4: DC Tested — Threshold for switching TTL LINK MON from High (off) to Low (on).
Note 5: Industrial temperature range specification..
5
ML4622, ML4624
FUNCTIONAL DESCRIPTION
AMPLIFIER
The ML4622, ML4624 have an adjustable Bandwidth
limiting amplifier. Maximum sensitivity is achieved
through the use of a DC restoration feedback loop and
AC coupling the input. When AC coupled, the input DC
bias voltage is set by an on-chip network at about 1.7V.
These coupling capacitors, in conjunction with the input
impedance of the amplifier, establish a high pass filter
with a 3dB corner frequency, fL, at
fL =
VOUT+
VOS
VOUT–
Figure 2.
1
2π 1600C
(1)
The above equation applies when a single capacitor is
tied between CF1 and CF2. When using two capacitors of
equal value (Cap1 from CF1 to VCC , Cap2 from CF2 to
VCC ) the value derived for C should be doubled.
Since the amplifier has a differential input, two capacitors
of equal value are required. If the signal driving the input
is single ended, one of the coupling capacitors can be tied
to VCC as shown in figure 1.
Although the input is AC coupled, the offset voltage
within the amplifier will be present at the amplifier’s
output. This is represented by VOS in figure 2. In order to
reduce this error a DC feedback loop is incorporated. This
negative feedback loop nulls the offset voltage, forcing
VOS to be zero. Although the capacitor on VDC is non-
CF1 and CF2 create a low pass filter with the corner
frequency determined by the following equation
1
2π 800(C + 4pF)
fH =
(2)
5pF
+VRF
CF1
ECL+
CF2
ECL–
BIAS
0.1
10Ω
–VRF
VIN–
0.01
6
HFBR
2416
3
ECL
CMP
AMP
2 0.01 VIN+
FIBER OPTIC CABLE
1
4
5
8
TTL
CMP
TTL OUT
CMP ENABLE
∫
7
0.1
VDC
–VRF
VREF
REF
VTHADJ
THRESH
GEN
VCC
TTL*
GND
TTL
TTL LINK MON
LINK DETECT
VCC
CTIMER
GND
0.05
L1
4.7µH
+5V
0.1
+
4.7
+
4.7
L2
4.7µH
Note:
+VRF
0.1
–VRF
If TTL OUT is used, tie GND TTL to unfiltered ground and remove L1. If TTL OUT and ECL outputs are both used, add 3K pulldown resistors at
ECL outputs.
Figure 1. The ML4622, ML4624 Configured for 20MHz Bandwidth
6
*ML4624 ONLY
ML4622, ML4624
critical, the pole it creates can effect the stability of the
feedback loop. To avoid stability problems, the value of
this capacitor should be at least 10 times larger than the
input coupling capacitors.
COMPARATOR
Two types of comparators are employed in the output
section of these Quantizers. The high speed ECL
comparator is used to provide the ECL level outputs and in
turn drives the TTL comparator. The enable pin, CMP
ENABLE, is provided to control the ECL comparator. When
CMP ENABLE is low the comparators function normally.
When it’s high, it forces ECL+ high, ECL– low, and TTL
OUT high. The CMP ENABLE pin can be controlled with
TTL level signals when the Quantizer is powered by 5V
and ground.
LINK DETECT CIRCUIT
The Link Detect circuit monitors the input signal and
provides a status signal indicating when the input falls
below a preset voltage level. When the input falls below
the preset voltage level, the TTL Link Mon output changes
from active (low) to inactive (high). This signal can be fed
to the ML4662 10BASE-FL transceiver or a similar type of
function to indicate a Low Light Condition. This output
can also be used to disable the output data by tying it to
the CMP Enable input.
In many fiber optic systems, including Ethernet and Token
Ring, a bit error rate is given at a minimum power level.
For example, in a 10Base-FL receiver there must be less
than 1 x 10–9 bit errors at a receive power level of
–32.5dBm average. Designers of these systems must
insure that the bit error rate is lower than the specification
at the given minimum power level. One procedure to
determine the sensitivity of a receiver is to start at the
lowest optical power level and gradually increase the
optical power until the BER is met. In this case the Link
Detect circuit must not disable the receiver (i.e. CMP
ENABLE should be tied to Ground). Once the sensitivity of
the receiver is determined, the Link Detector circuit can
be set just above the power level that meets the BER
specification. This way the receiver will shut off before the
BER is exceeded.
The ML4622 and ML4624 quantizers have greater Link
Detect sensitivity, noise immunity, and accuracy than their
predecessor the ML4621.
The threshold generator shifts the reference voltage at
VTH ADJ through a circuit which has a temperature
coefficient matching that of the limiting amplifier. The
relationship between the VTH ADJ and the VTH (the peak to
peak input threshold) is:
VTHADJ = 417 VTH (ML4624)
(3)
VTHADJ = 500 VTH (ML4622)
In most cases, including 10Base-FL, 10Base-FB and
Token-Ring, VTHADJ can be tied directly to VREF. However
if greater sensitivity is required the circuit in figure 3 can
be used to adjust the VTHADJ voltage. Even if VREF is tied
to VTHADJ, it is a good idea to layout a board with these
two resistors available. This will allow potential future
adjustments without board revisions.
The response time of the Link Detect circuit is set
by the CTIMER pin. Starting from the link off state (i.e.,
TTL␣ LINK␣ MON is high), the link can be switched on
if the input exceeds the set threshold for a time given by:
T=
C TIMER × 0.7V
700µA
(4)
To switch the link from on to off, the above time will be
doubled.
VREF
REF
R1
VTHADJ
THRESH
GEN
R2
(–VRF)
Figure 3.
BURST MODE
In some fiber optic links, the idle signal is DC, or of a
frequency that is substantially different from the data. For
these links, a faster response time of the DC loop and the
Link Monitor is required.
The ML4622 and ML4624 has been designed to
accommodate these two requirements. The input coupling
capacitors can be relatively small and still maintain
stability. With smaller input coupling capacitors and VDC
capacitor a faster DC loop response time can be achieved.
The Link Monitor is also enhanced to have a faster
response time.
7
ML4622, ML4624
ORDERING INFORMATION
PART NUMBER
TEMPERATURE
RANGE
ML4622CP
ML4622CS
ML4622IS
ML4624CP
ML4624CQ
0°C to 70°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
PACKAGE
Molded DIP (P16)
Molded SOIC (S16N)
Molded SOIC (S16N)
Molded DIP (P24N)
Molded PCC (Q28)
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described herein may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565,761; 5,594,376. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
8
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4322_24-01
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