Micro Linear ML6431CH Genlocking sync generator with digital audio clock for ntsc, pal & vga Datasheet

December 1998
PRELIMINARY
ML6430/ML6431*
Genlocking Sync Generator with
Digital Audio Clock for NTSC, PAL & VGA
GENERAL DESCRIPTION
FEATURES
The ML6430/ML6431 are multi-standard single-chip
BiCMOS video Genlock ICs for NTSC, PAL and VGA.
They are designed to provide a stable clock from an
analog video signal, and to provide timing pulses for
clamping, decoding, blanking and processing video
signals. The ML6430/ML6431 handle VCR glitches and
variations created by head switching, tape dropouts,
missing sync pulses, freeze frames, high speed playback
and camcorder gyro errors. The ML6430/ML6431 are
designed for high noise immunity, insensitivity to varying
signal amplitudes, overmodulated color carriers, and sync
glitches. Advanced analog and digital clock synthesis
techniques provide multi-standard and non-standard
operation from a single crystal or external asynchronous
clock source. Pin selectable preset modes allow operation
for most video standards in simple stand-alone mode
without the necessity of using the serial bus. For more
demanding applications, a two wire serial control bus is
available for full control of all of the ML6430/ML6431
features.
■
Line locked scalable horizontal pixel clock for an
arbitrary number of pixels per line
■
Standard frequencies of 12.27, 13.5, 14.75MHz, or 4Fsc
■
4´/2´ or 2´/1´ clock outputs (54 and 27MHz, or 27 and
13.5MHz) and VGA clocks
■
Audio clocks: 32, 44.1, or 48kHz, locked to video
■
On-chip sync separator, VCO and pulse generator
■
Low clock jitter: Short Term: <200ps rms locked
■
Line to line: <600ps rms (2.2ns peak-to-peak) locked
■
Fast recovery from VCR head switch, stable for fast
shuttle speeds and pause
■
Single crystal or external frequency source
■
PAL, NTSC or VGA operation
■
2 wire serial control bus, or selectable presets for stand
alone operation
■
RS170A compatible
The ML6430/ML6431 are ideal for clock generation in
MPEG encoders, high performance display timing, and
video editing.
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
CVIN/
HSYNC
4
9
21
29
VCC S
VCC A
VCC B
VCC D
CSYNC
6
26
MUX
SYNC SEPARATOR
7
CVREF
NOSIGNAL
14
SIGNAL DETECT
VSYNC
8
11
XTALIN
÷M
CRYSTAL
OSC.
HRESET
PHASE
DETECTOR
÷N
XTALOUT
32
1
2
DIGITAL PHASE DET.
AND FILTERING
DYNA. STATE MACH.
CONTROLLER
REF
VCO
FRESET
SCLAMP
BCLAMP/BURST
DIGITAL PHASE
MOD.
12
31
LOCKED
DIGITAL PLL
ANALOG PLL
HORIZ. PIXEL
COUNTER
VERT. LINE
COUNTER
1X CLOCK/4X CLOCK
2X CLOCK
VBLANK
P1
SERIAL CONTROL
AND PRESETS
P2/S DATA
P3/S CLK
SLEEP/54MHz
PULSE AND AUDIO
CLOCK GENERATOR
FREERUN
3
GND S
13
GND A
5
GND B
10
FIELD ID
AUDIOCLK/PHERROUT*
*PHERROUT IS
ONLY AVAILABLE IN ML6431
GND D
20
23
22
28
27
19
18
HBLANK
P0
15
25
24
17
16
30
1
ML6430/ML6431
PIN CONFIGURATION
P2/SDATA
HBLANK
CSYNC
BCLAMP/BURST
SCLAMP
VCC D
GND D
P0
P1
ML6430
32-Pin TQFP (H32-7)
32 31 30 29 28 27 26 25
24
1
VBLANK
P3/SCLK
2
23
HRESET
SLEEP/54MHz
3
22
FRESET
VCC S
4
21
VCC B
20
CVIN/HSYNC
6
19
1X CLOCK/4X CLOCK
CVREF
7
18
2X CLOCK
VSYNC
8
FIELD ID
AUDIOCLK
LOCKED
NOSIGNAL
FREERUN
XTALOUT
17
10 11 12 13 14 15 16
XTALIN
9
VCC A
5
GND B
GND A
GND S
TOP VIEW
P2/SDATA
HBLANK
CSYNC
32 31 30 29 28 27 26 25
24
1
VBLANK
23
HRESET
3
22
FRESET
6
19
1X CLOCK/4X CLOCK
CVREF
7
18
2X CLOCK
VSYNC
8
9
17
10 11 12 13 14 15 16
AUDIOCLK/PHERROUT
CVIN/HSYNC
LOCKED
GND B
NOSIGNAL
VCC B
20
FREERUN
21
5
XTALOUT
4
XTALIN
VCC S
GND S
GND A
2
VCC A
P3/SCLK
SLEEP/54MHz
TOP VIEW
2
BCLAMP/BURST
SCLAMP
VCC D
GND D
P0
P1
ML6431
32-Pin TQFP (H32-7)
FIELD ID
ML6430/ML6431
PIN DESCRIPTION
(NOTE: ML6430 and ML6431 pin functions are identical except for pin 16. See below)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
P2/SDATA
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus data input.
13
FREERUN
2
P3/SCLK
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus clock input.
Forces the PLL to run at a selected
standard without syncing to a video
signal. Accuracy is ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source
14
NOSIGNAL Indicates video signal activity has not
been detected at the composite input.
If NOSIGNAL = low, this condition
does not imply that lock has been
established. The NOSIGNAL pin can
be tied to FREERUN to create a local
loop in which the genlock will not try
to lock until a signal is detected at the
input.
15
LOCKED
16
(ML6430) AUDIOCLK
Digital audio clock output.
Programmable for 32kHz, 44.1kHz or
48kHz output.
16
(ML6431) AUDIOCLK/PHERROUT
This is a dual mode pin. Pin is selected
via serial bus (Register 7). AUDIOCLK
is an audio clock signal (see Table 9).
PHERROUT indicates whether
incoming HSYNC is ahead or behind
output HSYNC.
17
FIELD ID
18
2X CLOCK 2X oversampled PIXEL CLOCK &
Output of Digital PLL. Nominal
frequency of 27MHz
19
1X CLOCK/4X CLOCK
1X pixel clock. Nominal frequency
of 13.5MHz or 54MHz ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source. PAL 4X CLOCK
not available (no 4x4.4336MHz clock).
20
GND B
Digital ground for output driver
buffers.
21
VCC B
Digital supply for output driver buffers.
22
F RESET
Frame reset; active low for one half
line at the high to low transition of
field ID. In NTSC mode, FRESET goes
low on the high-to-low transition on
the Field ID pin and at the beginning
of line 1 (see Figure 2). In PAL mode,
FRESET goes low on the high-to-low
transition on the Field ID pin and at
the end of line 310 (see Figure 3).
3
SLEEP/54MHz
Hardware sleep mode: when low,
disables entire chip for ultra-low
power dissipation. Sleep mode can
also be enabled/disabled via serial bus
(Register 8). 54MHz is a clock input.
This can be any 4X clock up to
70MHz used for pulse generation.
4
VCC S
Analog supply for sync separator.
5
GND S
Analog ground for sync separator.
6
CVIN/HSYNC Composite video input; video input in
typical composite video applications,
or Y input for YUV applications, or G
input for RGB applications with sync
on green. For typical VGA or other
high performance display applications, this input may be supplied with
a TTL level HSYNC signal and the
vertical sync input supplied with a TTL
level VSYNC signal.
7
CV REF
Reference voltage for internal sync
slicer. The external capacitor is driven
by a charge pump to follow the sync
tip.
V SYNC
Vertical input for non-composite
sources. This input may be supplied
with a TTL level VSYNC signal. For
composite inputs this pin is tied high
or low.
9
VCC A
Analog supply pin for analog PLL.
10
GND A
Analog ground for analog PLL.
11
XTALIN
Crystal may be parallel tuned 3.58
MHz or 4.43MHz, or may be driven
by an external oscillator at these
frequencies, or at 4x these
frequencies.
8
12
XTALOUT
Crystal drive pin. No connect if using
external oscillator or clock.
Indicates when digital PLL is locked to
incoming video signal.
Field Flag: Odd = 1, Even = 0
3
ML6430/ML6431
PIN DESCRIPTION
(Continued)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
23
H RESET
Horizontal reset; active low for one
half pixel.
28
SCLAMP
24
V BLANK
Vertical blanking, active low
Sync clamp pulse occurs just after
leading edge of sync. Duration is
typically less than 50% of sync pulse
to avoid problems with equalizers in
the vertical interval, active high.
25
H BLANK
Horizontal blanking, active low
29
C SYNC
Composite sync output. May be either
the raw output of sync slicer, or
regenerated signal from internal pulse
generators. If raw slicer output is
selected, then signals disappear when
input signal disappears. If regenerated
output is selected, then signal is
always present regardless of input
conditions. Preset modes produce
regenerated sync.
VCC D
Digital supply pin for digital PLL.
26
30
GND D
Digital ground pin for digital PLL.
31
P0
This is a three-state pin: low means
serial bus is enabled, high or
unconnected (high Z) means presets
are active. Refer to Table 7.
32
P1
This is a three state pin. Refer to
Table 7. If presets are disabled pin
is ignored.
27
4
BCLAMP/BURST
This is a dual mode pin. User may
select either a back porch clamp pulse
or a burst gate pulse via the serial
control bus. Preset is BCLAMP pulse.
ML6430/ML6431
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Range ............................................... 4.5V to 5.5V
Temperature Range ....................................... 0°C to 70°C
Thermal Resistance ............................................. 80°C/W
DC Supply Voltage (VCC A & VCC D) ............. –0.3V to 7V
Analog & Digital Inputs/Outputs ... –0.3V to VCC A + 0.3V
Input current per pin ............................................. ±25mA
Storage Temperature ............................... – 65°C to 150°C
Junction Temperature .............................................. 125°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5 to 5.5V and TA = 0° to 70°C, CIN = 0.1µF, CREF = 0.1µF (Note 1).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
80
120
mA
SUPPLY
Supply Current (Analog and Digital)
Analog Supply Current
VCC A = VCC D = 4.5
35
mA
Digital Supply Current
Max programmed clock rates
45
mA
DIGITAL INPUTS
Low Level Input Voltage
0
0.8
V
High Level Input Voltage
VCC – 0.8
V CC
V
Low Level Input Current
VIN = 0V + 0.1V
1.0
µA
High Level Input Current
VIN = VCC D – 0.1V
1.0
µA
Input Capacitance
2
pF
TTL INPUTS (HSYNC, VSYNC)
VIL
Input Low Voltage
V IH
Input High Voltage
0.8
2.0
V
V
THREE STATE DIGITAL INPUTS
Low Level Input Voltage
0
High Level Input Voltage
VCC – 0.8
0.8
V
V
Low Level Input Current
VIN = 0V
50
150
µA
High Level Input Current
VIN = VCC D
50
150
µA
Input Capacitance
Mid Level Input Voltage with 5V Supply
2
pF
2
3
V
Low Level Output Voltage
0
0.5
V
High Level Output Voltage
VCC – 0.5
DIGITAL OUTPUTS
CLOAD : Output Capacitance
Output Disable Leakage
V
50
pF
10
µA
5
ML6430/ML6431
GENLOCK PERFORMANCE SPECIFICATIONS
Unless otherwise noted, VIN = 1 VPP NTSC test signal for composite inputs, or 100% color bars for component (Note 1).
See Figure 1 for parameter measurement definition
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC SEPARATION
Min Sync Amplitude
135
mV
Max Video Amplitude
3
V
Clamp timing error
NTC7 AC bounce signal (Note 2)
10
ns
Clamp Recovery TIme
NTC7 DC bounce signal (Note 3)
16
µs
CLOCK RECOVERY
Short Term Output Jitter Rejection
Input jitter = 50ns RMS
–15
dB
RMS Residual Output Clock Jitter
Input jitter <1ns RMS
600
ps
Peak to Peak (6s), Line to Line Jitter
Input Jitter < 1ns
2.0
Head Switch Recovery Time to 1ns Error
5µs step H change on or before
line 1
4
Step Frequency Recovery Time to 1ns Error
1% step H frequency change on or
before line 1
12
Missing Sync Sensitivity
(Note 4)
1.0
ns
Sync Glitch Sensitivity
(Note 5)
1.0
ns
4X Clock Duty Cycle
CLOAD = 50pF, fCLK4X < 60MHz
40
60
%
2X Clock Duty Cycle
CLOAD = 50pF, fCLK2X < 30MHz
48
52
%
1X Clock Duty Cycle
CLOAD = 50pF, fCLK1X < 15MHz
48
52
%
Clock Skew — 1X to 2X
CLOAD = 50pF, fCLK1X < 15MHz
6
ns
Pulse Output Rise Time
CLOAD = 50pF
2
10
ns
Pulse Output Fall Time
CLOAD = 50pF
2
10
ns
Pulse Output Setup Time
CLOAD = 50pF
20
ns
Pulse Output Hold Time
CLOAD = 50pF
20
ns
2.2
ns
lines
15
ms
SERIAL BUS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
Low Level Input Voltage
0
0.8
V
High Level Input Voltage
VCC – 0.8
V CC
V
Low Level Input Current
VIN = 0V
1.0
mA
High Level Input Current
VIN = VCC D
1.0
mA
Input Impedance fCLK = 100kHz
1
MW
Input Capacitance (CIN)
2
pF
SYSTEM TIMING
SCLK Frequency (fCLOCK)
100
Input Hysteresis (VHYS)
0.2
Spike Suppression (tSPIKE)
Max length for zero response
Power Setup Time to Valid Data Inputs
VCC Settled to Within 1%
6
V
50
10
kHz
ns
ms
ML6430/ML6431
SERIAL BUS LOGIC
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM TIMING (Continued)
Wait Time From STOP to START
On SDATA (tWAIT)
1.3
µs
Hold Time for START On SDATA (tHD/START)
0.6
µs
Setup Time for START On SDATA (tSU/START)
0.6
µs
Min LOW Time On SCLK (tLOW)
1.3
µs
Min HIGH Time On SCLK (tHI)
0.6
µs
Hold Time On SDATA (tHD/DATA)
5.0
Setup Time On (tSU/DATA)
µs
Fast mode (Note 2)
100
ns
Slow mode (Note 2)
250
ns
Rise Time for SCLK & SDATA (tLH)
30
300
ns
Fall Time for SCLK & SDATA (tHL)
30
300
ns
Setup Time for STOP On SDATA (tSU/STOP)
0.6
µs
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Parameter is Luma dependent.
Note 3: Reclock time after bounce.
Note 4: Net phase error for single isolated missing H pulse.
Note 5: Net phase error for glitch at sync level <50ns.
COMPOSITE
VIDEO IN
PIN 6
REGENERATED
CSYNC
PIN 26
tHSW
tHEQW
EQUALIZERS
SERRATIONS
HBLANK
PIN 25
tHSERRW
tHBLK
tHBLKW
tHSTC
SCLAMP
PIN 28
tHSTCW
BGATE
PIN 27
tHBPC
tHBPGW
BCLAMP
PIN 27
tHBPCW
HRESET
PIN 23
tHRW
NOTE: NOT TO SCALE
Figure 1. Line Rate Waveforms
7
ML6430/ML6431
DEVICE DIFFERENCES
Tables 1 and 2 summarize the differences between the
ML6430 and ML6431. The pinouts of the ML6430 and the
ML6431 are the same with the exception that the ML6431
DEVICE
has a few enhancements, (Center Frequency and Free Run
Mode, see Table 1) and added functionality (see Table 2).
FUNCTIONAL DESCRIPTION
Video Formats,
Timing,
and Pulse
Generation
Clock
Rates
Input
Crystal
NTSC
PAL
CCIR601
Square
Pixel
4xFSC
3.58
MHz
4.43
MHz
ML6430
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ML6431
Yes
Yes*
Yes
Yes*
Yes
Yes
Yes
Free Run
Mode
VGA
Clock
VCR
Lock
Yes. Limited
transition
between free
run modes
1 and 2.
(Figure 4)
Yes. Faster
transition between freerun
modes 1and 2.
(Figure 4a)
Yes. Limited to
640x480
pixel clock.
Yes
Yes. Works
up to 75MHz.
(Table 6)
Yes.
* Readjusted the center frequency for PAL square pixel with NTSC crystal to achieve greater than +/-5% range. See Table 4
Table 1. Summary of Functional Differences between the ML6430 and ML6431.
DEVICE
ML6430
ML6431
MODE
Sleep Mode
Pulse Generator Mode*
Time Base Correction Mode
Sleep Mode
Pulse Generator Mode*
PHERROUT Mode*
REGISTER DIFFERENCES
Register 7,
Bit 2
0
1
0
1
X
PIN OUT DIFFERENCES
Register 7,
Pin 3
Pin 16
Bit 3
0
SLEEP
AUDIOCLK
0
54MHz**
AUDIOCLK
This function not available in the ML6430
0
SLEEP
AUDIOCLK
0
54MHz**
AUDIOCLK
1
Must be set HIGH
PHERROUT
*For these modes the SLEEP mode can only be enable/disabled via serial bus (Register 8).
**The 54MHz clock input (pin 3) can be any 4 x Clock up to 70MHz
Table 2. Summary of Register Differences between the ML6430 and ML6431.
8
ML6430/ML6431
FUNCTIONAL DESCRIPTION
DUAL PLLS
PHERROUT SIGNAL
The Genlock has the following properties:
• A stable, asynchronous crystal controlled oscillator
provides the basic timing signals.
• A precision analog circuit uses the above timing
signals to generate an arbitrarily phased output whose
phase can be altered at pixel rate.
• A digital PLL loop monitors the error signal from a
digital phase detector, and generates a pixel by pixel
phase adjustment of the output.
• An intelligent state machine further enhances
performance by monitoring errors and error history and
adjusting the gains of the loop accordingly.
• A circuit automatically detects a VCR signal and
increases loop gain for proper tracking and minimum
jitter.
The PHERROUT pin indicates, on a line by line basis,
whether the H SYNC pulse of the analog input signal is
leading or trailing the genlock's output H SYNC pulse.
This information is used by the genlock to decide whether
to speed up or slow down the internal clock to achieve
locking of the H SYNC pulses. If PHERROUT = 0, then
the analog sync is ahead; therefore, the internal clock
will speed up in an effort to lock the H SYNC pulses. By
contrast, if PHERROUT = 1, then the analog sync is
behind; therefore, the internal clock will slow down in an
effort to lock the H SYNC pulses. Ultimately, when the
genlock is locked to the incoming analog signal,
PHERROUT will alternate approximately every line
between 0 and 1.
The digital PLL has five operating modes. In normal
operation with a stable input the controller will settle to
state 1. If errors are large and consistent, controller will
move to state 5. If error conditions are corrected,
controller will sequentially decrease the state as the errors
are reduced toward 0. If small but consistent errors persist
while controller is in state 1, then controller may move to
states 2 or 3 to help settle out errors more quickly. None
of these changes will cause a reset of pixel count, or a
discontinuity of output clocks. Operating modes are
described in greater detail below.
1. Normal: Gain is low, instantaneous phase gain is
1/32, giving a net short term jitter gain (output/input
jitter) of about -30db. Full peak to peak jitter (including
lower frequency jitter) from a white source is about 15db.
2. Slow: Gain is increased by 4x, and settling time
reduced by about the same. This mode is used as a
transition mode during normal lock sequence, or as a
modest speed up mode if errors are high.
3. Medium: Gain is increased by 8x, and settling time
reduced by about the same. This mode is used as a
transition mode during normal lock sequence, or as a
speed up mode if errors are consistently high.
4. Fast: Gain is increased by 16x. Adds frequency
adjustments to mode 5 for fast settling during hot
switches or pathological gyro errors in hand held
camcorders.
5. Phase: Only Gain is 16x for phase changes, 0 for
frequency changes. Primarily used to quickly settle
head switch phase errors without affecting loop
frequency.
PHERROUT (PIN 16)
DESCRIPTION
0
1
Speed up output timing
Slow down output timing
Table 3. PHERROUT Signal Description
SYNC SEPARATION
Sync separation is accomplished using peak tracking
analog amplifiers with a precision sync slicer. The closed
tracking loop is equipped with timers to discriminate true
sync pulses from noise glitches or chroma overshoots. The
use of analog sync separation techniques removes a
serious source of jitter present in most digital PLLs.
CRYSTAL SELECTION
The precision crystal source for the ML6430/ML6431 can
be supplied in one of four ways. An industry standard
3.58MHz parallel tuned NTSC color subcarrier crystal or a
4.43MHz parallel tuned PAL color subcarrier crystal may
be used. Alternately, a 14.318MHz NTSC or 17.7MHz
PAL, 4xFs, or a 3.58MHz or 4.43MHz oscillator source
may be used. Regardless of the crystal used, the ML6430/
ML6431 can lock to PAL, NTSC, Beta or MII or YUV in
either 625 or 525 standards. Table 4 provides the clock
rate accuracy for both the NTSC and PAL clock rates for
each crystal selected. Note that the range may vary
between the ML6430 and the ML6431.
LOW POWER SLEEP MODES
Sleep mode may be initiated either from the serial control
bus, or from an external pin. In both cases the entire chip
except the serial bus is shut down. For applications where
PHERROUT is used, the sleep mode can only be enabled/
disabled via serial control.
9
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
STANDARD OF THE ML6430
VIDEO STANDARD
CLOCK RATE
CLOCK RATE
ACCURACY
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
STANDARD OF THE ML6431
VIDEO STANDARD
CLOCK RATE
CLOCK RATE
ACCURACY
3.58MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4.43MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
3.58MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4.43MHz Crystal
NTSC Square Pixel
NTSC 601
NTSC 4fsc
PAL Square Pixel
PAL 601
PAL 4fsc
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
49.09MHz
54.00MHz
57.27MHz
59.00MHz
54.00MHz
35.47MHz
+8.35%/ –5.19%
+6.07%/ –7.18%
+7.15%/ –6.23%
+4.01%/ –9.10%
+6.07%/–7.18%
+9.58%/ –4.14%
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
49.09MHz
54.00MHz
57.27MHz
59.00MHz
54.00MHz
35.47MHz
+8.28%/ –5.23%
+7.81%/ –5.64%
+6.00%/ –7.18%
+7.27%/ –6.13%
+7.81%/–5.64%
+7.05%/ –6.31%
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
49.09MHz
54.00MHz
57.27MHz
59.00MHz
54.00MHz
35.47MHz
+8.35%/ –5.19%
+6.07%/ –7.18%
+7.15%/ –6.23%
+7.47%/ –5.93%
+6.07%/–7.18%
+7.64%/ –5.77%
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
4xClk=
49.09MHz
54.00MHz
57.27MHz
59.00MHz
54.00MHz
35.47MHz
+8.28%/ –5.23%
+7.81%/ –5.64%
+6.00%/ –7.18%
+7.27%/ –6.13%
+7.81%/–5.64%
+7.05%/ –6.31%
Table 4. NTSC/ PAL Clock Rate Range vs. Crystal Input
DISABLING AUTOMATIC VCR SIGNAL DETECTION
PULSE GENERATOR MODE
54MHz Input or Any 4X Clock
DEVICE
DISABLE VCR SIGNAL DETECTION?
ML6430
ML6431
No. Detection function is always on.
Yes. Detection function can be disabled
or enabled via serial bus only. This
feature is enabled by default.
Table 5.
In the ML6430, the VCR detection circuit is always
enabled. This circuit detects the presence of a VCR input
signal at CVIN / HSYNC (pin 6) and automatically adjusts
the gain settings for the digital PLL to optimize locking
performance. This circuit scans for head switching greater
than the thresholds selected by the user threshold bits (via
serial bus) and then increases the phase gain of the digital
PLL to compensate.
In the ML6431, the VCR detection circuit operates the
same as the ML6430 with the additional ability to disable
or enable the VCR detection circuit to optimize for low
jitter performance. This feature is enabled by default.
This feature can be disabled in the ML6431 only by
setting the appropriate values in Register 7, Bit 0 via the
serial bus interface (see Table 11). When the VCR detect
circuit is disabled, the ML6431 is optimized for low jitter
performance.
10
The 54MHz pin (pin 3) is an input that clocks the
horizontal and vertical counters. In this mode, the
ML6430 or ML6431 is used as a pulse generator. The
input signal at can be any 4X clock; for example, 54MHz
(4 x CCIR clock rate of 13.5MHz), 49.09MHz (4 x Square
Pixel clock rate of 12.27MHz), or 57.27 MHz (4 x Fsc
clock rate of 14.31MHz for NTSC color subcarrier). This
input is limited to 70MHz.
As a pulse generator, the sync, clamp, blanking, and
clock signals are derived from the clock input at the
54MHz pin. This mode is activated by setting the
appropriate values in Register 7 via the serial bus. See
Tables 10 or 11.
USING FRESET FOR NTSC vs. PAL MODES
In NTSC mode, FRESET (pin 22) goes low on the high-tolow transition of the FIELD ID pin (pin 17) and the
beginning of line 1 (see Figure 2).
In the PAL mode, FRESET (pin 22)goes low on the low-tohigh transition of the FIELD ID pin and the end of line
310 (see Figure 3).
ML6430/ML6431
FIELD 1
Vertical Blanking Interval
3H
525
2
1
H
3H
Start of
Field 1
3
4
H
H
3H
6
5
8
7
9
12
11
10
14
13
16
15
18
17
20
19
22
21
H
H/2
FIELD 2
Vertical Blanking Interval
262
263
H/2
264
265
267
266
268
271
270
269
273
272
274
276
275
277
279
278
280
281
282
283
284
Start of
Field 2
VBLANK
Pin 24
9 or 16 Lines
FRESET
Pin 22
(Odd Vertical Intervals Only)
½ Line
FIELDID
Pin 17
Low For Odd Fields
FIELDID
Pin 17
High For Even Fields
Figure 2. NTSC Field Rate Waveforms
FIELD BLANKING (25 LINES + LINE BLANKING)
END OF FOURTH FIELD (ODD)
BEGINNING OF FIRST FIELD (EVEN)
WHITE LEVEL
}
622
623
624
625
2
1
2.5 LINES
FIELD SYNC
5 BROAD
PULSES
2.5 LINES
5
EQUALIZING
PULSES
END OF FIRST FIELD (EVEN)
WHITE LEVEL
}
6
5
8
7
9
12
11
10
14
13
23
16
15
2.5 LINES
5
EQUALIZING
PULSES
BEGINNING OF SECOND FIELD (ODD)
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
336
~
BLACK LEVEL
BLANKING LEVEL
SYNC LEVEL
4
3
~
BLACK LEVEL
BLANKING LEVEL
SYNC LEVEL
VBLANK
Pin 24
FRESET
Pin 22
ODDFLD
Pin 17
BROAD PULSE
SEPARATION
4.7µs ± 100ns
7.5 or 16 Lines
½ Line
(Second Field Vertical Interval Only)
High for Second Field, Low for First Field
Figure 3. PAL 625 Field Rate Waveforms
11
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
FREERUN MODE
is not horizontally locked to a video source. In this
mode, a ROM lookup table is used to set the freerun
frequency of the ML6430/ML6431. In this mode the
output frequency is as accurate as the Crystal plus the
accuracy of the look up table. See Figures 4 and 4a
for the NoSignal-Locked-Freerun state machine
diagram.
Both the ML6430 and ML6431 can be used in Freerun
mode. The ML6431 is recommended for applications
requiring a more robust Freerun mode of operations.
Figure 4 and Figure 4a describe the state diagrams for
both the ML6430 and ML6431. Note that the ML6431
includes a faster path to go from FREERUN MODE #1 to
FREERUN MODE #2.
NoSignal: NoSignal will go low if video is present for
one entire field. NoSignal will be high if video is not
present for one entire field.
Freerun mode: FREERUN MODE #1 is entered when
the freerun pin is toggled high while the ML6430/
ML6431 is horizontally locked (i.e. internal horizontal
locked signal is present). In this mode, the digital
frequency value stored in the line-locked PLL is held
and the ML6430/ML6431 will freerun at a frequency
very close to that of the last locked video source.
Freerun mode #1 is best used by physically tying the
NoSignal pin to the freerun pin as shown in Figures 9
or 10. FREERUN MODE #2 is entered when the
freerun pin is toggled high while the ML6430/Ml6431
Locked (ML6430): The ML6430 must be line
(horizontal) locked to an input video source and also
be vertically locked before the locked detect signal
goes high. When a video source is removed, the
locked signal may be high or low. Please note that the
locked pin is the logical AND of the internal
horizontal locked and vertical locked signals. For
example, the internal horizontal locked signal may be
high even though the locked pin is asserted low.
TOGGLE
FREERUN PIN
"HIGH"
IF NO VIDEO
FOR > 1 FRAME
POWER UP
ML6430 W/
FREERUN PIN
"LOW" (TYPICAL)
HORIZONTAL
LOCKED
HORIZONTAL
LOCKED
SIGNAL
PRESENT
NO SIGNAL
PRESENT
2
INPUT VIDEO
WITHIN ±6%
RANGE
IF INPUT VIDEO
FOR > 1 FRAME
3
TOGGLE
FREERUN PIN
"HIGH"
FREERUN PIN
"LOW"
5
INPUT VIDEO
OUTSIDE ±6%
RANGE
IF NO VIDEO
FOR > 1 FRAME
FREERUN PIN
"LOW"
HORIZONTAL
UNLOCKED
HORIZONTAL
UNLOCKED
SIGNAL
PRESENT
NO SIGNAL
PRESENT
1
IF INPUT VIDEO
FOR > 1 FRAME
TOGGLE
FREERUN PIN
"HIGH"
4
TOGGLE
FREERUN PIN
"HIGH"
Figure 4. ML6430 Freerun Mode State Diagram
12
FREERUN
MODE #1
FREERUN
MODE #2
6
POWER UP
ML6430 W/
FREERUN PIN
"HIGH" (TYPICAL)
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
Table 6 first find the resolution and refresh rate required.
Determine which crystal, PAL or NTSC is needed. Change
the crystal to the proper frequency if necessary. Over the
serial-bus, program the registers as indicated in Table 6.
Supply to pin 6 an horizontal sync signal at TTL or CMOS
levels and at the specified frequency. Trigger an
oscilloscope on the falling edge of the horizontal input to
view the outputs. The VGA pixel clock will be found on
pin 18. Other useful signals are noted in table 6. External
logic may be needed to produce usable vertical sync
pulses.
Locked (ML6431): The ML6431 must be line
(horizontal) locked to an input video source for at
least two fields and also be vertically locked before
the locked detect signal goes high. When a video
source is removed, the ML6431 will lose horizontal
lock after two entire fields with no video present.
However, vertical lock may be lost before horizontal
lock. Because the locked pin is the logical AND of
the internal horizontal locked and vertical locked
signals the locked pin may go low before the internal
horizontal locked signal.
AUDIO CLOCKS
VGA CLOCKS
The audio modes can be activated via serial bus (Register
7). When this mode is activated an audio clock
frequency can be selected via serial bus (Register 8). See
Table 9.
For VGA applications the ML6431 is recommended.
Table 6 provides a list of the VGA clocks that can be
generated using the ML6431. To use the information in
TOGGLE
FREERUN PIN
"HIGH"
IF NO VIDEO
FOR > 1 FRAME
POWER UP
ML6431 W/
FREERUN PIN
"LOW" (TYPICAL)
HORIZONTAL
LOCKED
HORIZONTAL
LOCKED
SIGNAL
PRESENT
NO SIGNAL
PRESENT
2
INPUT VIDEO
WITHIN ±6%
RANGE
IF INPUT VIDEO
FOR > 1 FRAME
3
FREERUN PIN
"LOW"
FREERUN
MODE #1
5
IF NO VIDEO
FOR > 2 FRAMES
INPUT VIDEO
OUTSIDE ±6%
RANGE
IF NO VIDEO
FOR > 1 FRAME
FREERUN PIN
"LOW"
HORIZONTAL
UNLOCKED
HORIZONTAL
UNLOCKED
SIGNAL
PRESENT
NO SIGNAL
PRESENT
1
TOGGLE
FREERUN PIN
"HIGH"
IF INPUT VIDEO
FOR > 1 FRAME
TOGGLE
FREERUN PIN
"HIGH"
4
FREERUN
MODE #2
6
POWER UP
ML6431 W/
FREERUN PIN
"HIGH" (TYPICAL)
TOGGLE
FREERUN PIN
"HIGH"
Figure 4a. ML6431 Freerun Mode State Diagram
13
ML6430/ML6431
14
ML6431 Data Register Settings*
Resolution
# Pixels
per Line
Refresh
Rate
Horizontal
Frequency
Pixel
Frequency
Standard
Type
640 x 480
800
60 Hz
31.5 KHz
25.175 MHz
Industry
832
72 Hz
37.9 KHz
31.500 MHz
VESA
840
75 Hz
37.5 KHz
31.500 MHz
VESA
1024
56 Hz
35.1 KHz
36.000 MHz
1056
60 Hz
37.9 KHz
1040
72 Hz
1056
800 x 600
1024 x 768
Original
Standard #
Freq. Std.
PALXtal
Pixel Reg
PherrOut
VGA
External
Xtal Used
Pixel
Clk Output
Horizontal
Pulses
Vertical
Pulses
NTSC Sq Pix =000
1
572
0
1
4.43
2X
“Hsync,Hreset” Vreset
VS901101
NTSC Sq Pix =000
0
640
0
1
4.43
2X
“Hsync,Hreset” Vreset
VDMT75HZ
NTSC Sq Pix =000
0
656
0
1
4.43
2X
“Hsync,Hreset” Vreset**
VESA
VG900601
PAL 4FSC
=101
1
512
1
1
4.43
4X
“Hsync,Hreset” Vreset
40.000 MHz
VESA
VG900602
NTSC Sq Pix =000
1
544
1
1
3.58
4X
“Hsync,Hreset” Vreset**
48.1 KHz
50.000 MHz
VESA
VS900603A
NTSC Sq Pix =000
1
528
1
1
4.43
4X
“Hsync,Hreset” Vreset**
75 Hz
46.9 KHz
49.500 MHz
VESA
VDMT75HZ
NTSC Sq Pix =000
1
544
1
1
4.43
4X
“Hsync,Hreset” Vreset**
1264
43 Hz/Int
35.5 KHz
44.900 MHz
Industry
PAL 4FSC =101
0
752
1
1
4.43
4X
“Hsync,Hreset” Vreset**
1344
60 Hz
48.4 KHz
65.000 MHz
VESA
VG901101A
PAL 601
0
832
1
1
4.43
4X
“Hsync,Hreset” Vreset**
1328
70 Hz
56.5 KHz
75.000 MHz
VESA
VS910801-2
PAL 4FSC =101
0
816
1
1
3.58
= 011
*For Data Register Settings: TTL = High, VGA = On, VCR = Off, Noise Gating = On, Dis Auto Ver Det = 1
** w/ external glue logic
Table 6. VGA Rates Supported
4X & clk
doubler
No
No
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
PRESET PIN CONTROL
PULSE OUTPUTS
The ML6430/ML6431 may be controlled via a set of four
preset mode pins. These pins do not allow access to all
the programmable features of the ML6430/ML6431, but
are intended to provide a simpler interface for most
applications.
Pulse outputs are defined in Table 12. Note that the pulse
widths and start times are chosen to the nearest clock
edge, and indicated errors assume nominal clock
operating frequency.
P3 P2 P1 P0
STD
0
1
0
1
NTSC
1
0
0
1
1
1
0
0
1
1
CLOCK RATE
CRYSTAL
P3 P2 P1 P0
STD
CLOCK RATE
CRYSTAL
Square pixel
3.58MHz
0
Z
0
Z
NTSC
Square pixel
17.72MHz
NTSC
CCIR601
3.58MHz
Z
0
0
Z
NTSC
CCIR601
17.72MHz
1
NTSC
4Fsc
3.58MHz
Z
Z
0
Z
NTSC
4Fsc
17.72MHz
1
1
PAL
Square pixel
3.58MHz
0
Z
1
Z
PAL
Square pixel
17.72MHz
0
1
1
PAL
CCIR601
3.58MHz
Z
0
1
Z
PAL
CCIR601
17.72MHz
1
1
1
1
PAL
4Fsc
3.58MHz
Z
Z
1
Z
PAL
4Fsc
17.72MHz
0
1
0
Z
NTSC
Square pixel
4.43MHz
Z
1
0
1
NTSC
Square pixel, VGA
3.58MHz
1
0
0
Z
NTSC
CCIR601
4.43MHz
1
Z
0
1
NTSC
CCIR601,VGA
3.58MHz
1
1
0
Z
NTSC
4Fsc
4.43MHz
0
0
0
1
NTSC
4Fsc, VGA
3.58MHz
0
1
1
Z
PAL
Square pixel
4.43MHz
Z
1
1
1
PAL
Square pixel, VGA
3.58MHz
1
0
1
Z
PAL
CCIR601
4.43MHz
1
Z
1
1
PAL
CCIR601, VGA
3.58MHz
1
1
1
Z
PAL
4Fsc
4.43MHz
0
0
1
1
PAL
4Fsc, VGA
3.58MHz
0
Z
0
1
NTSC
Square pixel
14.32MHz
Z
1
0
Z
NTSC
Square pixel, VGA
4.43MHz
Z
0
0
1
NTSC
CCIR601
14.32MHz
1
Z
0
Z
NTSC
CCIR601, VGA
4.43MHz
Z
Z
0
1
NTSC
4Fsc
14.32MHz
0
0
0
Z
NTSC
4Fsc, VGA
4.43MHz
0
Z
1
1
PAL
Square pixel
14.32MHz
Z
1
1
Z
PAL
Square pixel, VGA
4.43MHz
Z
0
1
1
PAL
CCIR601
14.32MHz
1
Z
1
Z
PAL
CCIR601, VGA
4.43MHz
Z
Z
1
1
PAL
4Fsc
14.32MHz
0
0
1
Z
PAL
4Fsc, VGA
4.43MHz
X
X
X
0
Serial control mode
Z = Floating input, 0 = Low input, 1 = High input, X = Don’t care
Table 7. Preset Pin Modes
15
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
CONTROL REGISTER INFORMATION
REGISTER
PulsePol[2:0]
Clk4X
Pixel[10:0]
Burst
CSyncRaw
RawClamp
TTL Sync
WideBlank
HDelay[6:0]
Noise Gating
Test 3,1,4
External 54
Clock IN
FAud[1:0]
VCR
SLEEP
Thresh[1:0]
VGA
Div4
Fstd[2:0]
PALXTAL
SETTING
000
0
Determined by PRESET pin
0
0
0
0
0
1000000
0
0, 0, 0
0
01
0
0
11
Determined by PRESET pin
Determined by PRESET pin
Determined by PRESET pin
Determined by PRESET pin
Table 8. Default Control Register Settings for Preset Mode
REGISTER DESCRIPTION
SLEEP: Enables or disables sleep mode. When using
serial bus control, ALL registers must be programmed to
their intended state after power up to ensure correct
operation of the ML6430/ML6431.
CSR: Composite sync register bit controls whether
composite sync output is from the sync separator,
(raw CSYNC) or from the internal pulse generator
(regenerated CSYNC).
Pulse Polarity Control: The active state of output sync
pulses, blanking pulses, or clamp pulses may be
programmed to either 0 or 1 state by use of these bits.
P0: CSYNC pulse output is high active when 1,
low active when 0.
P1: HBLANK, and VBLANK pulse outputs are high
active when 1, low active when 0.
P2: SCLAMP and BCLAMP pulse outputs are high
active when 1, low active when 0.
Burst: Controls the length of Burst Gate so pulse can be
used for either burst gating in encoder applications or
back porch clamping.
16
RawClamp: Controls the source of the SCLAMP (sync
clamp) pulse. Pulse is timed relative to incoming sync
edge, or regenerated sync edge.
PALXTAL: Controls the expected crystal frequency at the
oscillator inputs. 0 = NTSC 3.58MHz, or 1 = PAL 4.43MHz.
Thresh1,Thresh0: Selects the pixel error threshold at
which relock is initiated. Values are:
0,0:
0,1:
1,0:
1,1:
2.5 pixels
2.5 pixels
1.0 pixels
4.0 pixels
Noise Gating: Enables a 3/4 line window to lockout any
unwanted horizontal sync pulses.
VGA: Produces non-interlaced progressive scan outputs.
Div4: Controls the prescaler in the M/N loop. High means
that 4Fs external oscillator signals are expected, low
assumes a PAL or NTSC Fs crystal will be used.
VCR: Controls the gain range and locking maneuvers of
the digital loop. Provides better locking to the
unpredictability of VCR headswitches and jitter.
Blanking Width Control: The number of blanked lines in
the vertical interval is programmable to either 9 or 16.
XTAL: external Crystal Control: 0=NTSC 3.58MHz, or
1=PAL 4.43MHz, for both local crystal and external
oscillator mode.
External 54MHz Clock: This mode permits injecting a
54MHz clock (or other 4X clock) directly into the
horizontal pixel counter via the SLEEP pin. All timing
pulses are synchronous to the 54MHz clock (or other 4X
clock).
Serial Bus Control: To place the Ml6430/ML6431 in serial
mode, take P0 (Preset ) to logical '0' or ground. The serial
control system is written to by the external processor in 8bit bytes. Each of these bytes is partitioned into an
address (upper 4 bits of serial byte) and a data register
(lower 4 bits of serial byte). In Table 10, the Register
heading refers to the 4-bit address, and Data Bit refers to a
particular bit in the 4-bit register (Bit0 is LSB).
Pixel: Program all bits to zero to enable default values for
each standard. Otherwise use the following equation:
P[10:0] = 2 ´ (number of pixels per line) – 1024
Test: All test bits must be programmed to zero.
(1)
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
Audio Clock: The Ml6430/ML6431 outputs a clock at
32kHz, 44.1kHz, or 48kHz. This clock is locked in
frequency to the basic video clock regardless of the
standard being used. With VCR head switches, the phase
correction required to track the timing is removed from
the audio clock by a patented circuit. This prevents the
audio clock from being modulated by step changes in
video timing. See the Table 9 for the audio clock rates
supported and how they are derived internally.
ADDITIONAL CONTROL REGISTERS (ML6431 ONLY)
DisAutoVCR:
Disables the auto VCR detect circuit.
This bit controls the source of AUDIOCLK/PHERROUT.
When this bit is low, AUDIOCLK/PHERROUT provides the
audio clock output. When this bit is high, AUDIOCLK/
PHERROUT provides the 1-bit digital phase error of each
Hsync edge.
Additionally, when both PHERROUT enable and VGA bits
are logic high, the reset point of the pixel counter is
changed from 512 to 256. This changes the equation for
calculating the number of pixels per line verses the Pixel
Counter bits to the following:
P[10:0] = 2 ´ (number of pixels per line) – 512
(2)
Register 7, Bit 0: DisAutoVCR
PHERROUT:
MUX phase error signal onto
AUDIOCLK/PHERROUT pin.
Register 7, Bit 3: PHERROUT enable
VIDEO STANDARD
AUDIO RATE
AUDIO/PIXEL CLOCK RATIO
AUDIO/FRAME RATE RATIO
CCIR601 NTSC
CCIR601 NTSC
CCIR601 NTSC
48kHz
44.1kHz
32kHz
(96000 ÷ 27MHz) ´ 13.5MHz
(88200 ÷ 27MHz) ´ 13.5MHz
(64000 ÷ 27MHz) ´ 13.5MHz
(8008 ÷ 5) ´ 29.97Hz
(147147 ÷ 100) ´ 29.97Hz
(16016 ÷ 15) ´ 29.97Hz
CCIR601 PAL
CCIR601 PAL
CCIR601 PAL
48kHz
44.1kHz
32kHz
(96000 ÷ 27MHz) ´ 13.5MHz
(88200 ÷ 27MHz) ´ 13.5MHz
(64000 ÷ 27MHz) ´ 13.5MHz
(1920) ´ 25Hz
(1764) ´ 25Hz
(1280) ´ 25Hz
NTSC Square Pixel
NTSC Square Pixel
NTSC Square Pixel
48kHz
44.1kHz
32kHz
(105600 ÷ 27MHz) ´ 12.27MHz
(97020 ÷ 27MHz) ´ 12.27MHz
(70400 ÷ 27MHz) ´ 12.27MHz
(8008 ÷ 5) ´ 29.97Hz
(147147 ÷ 100) ´ 29.97Hz
(16016 ÷ 15) ´ 29.97Hz
PAL Square Pixel
PAL Square Pixel
PAL Square Pixel
48kHz
44.1kHz
32kHz
(96000 ÷ 29.5MHz) ´ 14.75MHz
(88200 ÷ 29.5MHz) ´ 14.75MHz
(64000 ÷ 29.5MHz) ´ 14.75MHz
(1920) ´ 25Hz
(1764) ´ 25Hz
(1280) ´ 25Hz
NTSC 4xFSC
NTSC 4xFSC
NTSC 4xFSC
48kHz
44.1kHz
32kHz
(105600 ÷ 31.5MHz) ´ 14.32MHz
(92400 ÷ 30MHz) ´ 14.32MHz
(70400 ÷ 31.5MHz) ´ 14.32MHz
(8008 ÷ 5) ´ 29.97Hz
(147147 ÷ 100) ´ 29.97Hz
(16016 ÷ 15) ´ 29.97Hz
PAL 4xFSC
PAL 4xFSC
PAL 4xFSC
48kHz
44.1kHz
32kHz
(76800 ÷ 28.37MHz) ´ 17.72MHz
(70560 ÷ 28.37MHz) ´ 17.72MHz
(51200 ÷ 28.37MHz) ´ 17.72MHz
(1920) ´ 25Hz
(1764) ´ 25Hz
(1280) ´ 25Hz
Table 9. Audio Clock Generation (ML6430/ML6431)
17
ML6430/ML6431
REGISTER
DATA
BIT
DESCRIPTION
0
0
PulsePol 0
CSYNC Polarity
High Active-Low Active
0 or 1
0
1
PulsePol 1
H/V Blank Polarity
High Active-Low Active
0 or 1
0
2
PulsePol 2
S/B Clamp Polarity
High Active-Low Active
0 or 1
0
3
Clk 4X
Select 4X Clock
Low 1X Clock = 13.5MHz
High 4X Clock = 54MHz
0 or 1
1
0
Pixel0
Pix Counter Load Bit 0
1
1
Pixel1
Pix Counter Load Bit 1
1
2
Pixel2
Pix Counter Load Bit 2
1
3
Pixel3
Pix Counter Load Bit 3
2
0
Pixel4
Pix Counter Load Bit 4
2
1
Pixel5
Pix Counter Load Bit 5
2
2
Pixel6
Pix Counter Load Bit 6
2
3
Pixel7
Pix Counter Load Bit 7
3
0
Pixel8
Pix Counter Load Bit 8
3
1
Pixel9
Pix Counter Load Bit 9
3
2
Pixel10
Pix Counter Load Bit 10
3
3
Burst
Burst Gate Enable
Low = Back Porch Clamp
High = Burst Gate
0 or 1
4
0
CSyncRaw
(or CSYNC Regen)
Low = regenerated CSYNC
High = raw CSYNC
0 or 1
4
1
RawClamp
(or Clamp Regen)
Low = regenerated Clamp
High = raw Clamp
0 or 1
4
2
TTL Sync
TTL horizontal + vertical
Sync Input
Low = sync separator active
High = TTL horiz + vert sync input
0 or 1
4
3
WideBlank
(or Narrow)
Low = narrow blanking
High = wide blanking
0 or 1
5
0
HDelay0
5
1
HDelay1
5
2
HDelay2
5
3
HDelay3
6
0
HDelay4
6
1
HDelay5
6
2
HDelay6
6
3
Noise Gating 3/4 line lockout
H Delay parameter allows
moving the entire constellation
of output pulses relative to the
incoming HSYNC. Exception:
Sync Tip clamp may be
selected for delay or triggered
from incoming sync
depending on application.
VALUE RANGE
Numerical value taken as unsigned
binary. Actual no. of pixels is:
nom = ~011 0000 0000
512 +
P 10:0
2
max = 011 0011 0000
min = 010 1101 0000
Do not vary pixel [10:0] by more than
±6% from nominal.
1024 > no. of pixels > 512 and
fNOM x 1.06 > fNEW > fNOM x 0.94
0000000 to 1111111:
7-bit Horizontal Delay parameter.
Values:
–64p< Hdly < 63p, p = 1/F4XCLK
0000000 means –64p
1111111 means +63p
1000000 means 0p
Low = noise gating on
High = noise gating off
Table 10. ML6430 Register Map
18
BIT CODE
RANGE
0 or 1
ML6430/ML6431
REGISTER
DATA
BIT
7
0
7
7
7
1
2
3
DESCRIPTION
Test 3
Test 1
BIT CODE
RANGE
For test mode only:
No user programmable features
Set to 0
0
For test mode only:
No user programmable features
Set to 0
0
Low = Pin 3 is SLEEP
High = Pin 3 is 54MHz Clock
Ext 54
Clock IN
Test 4
VALUE RANGE
For test mode only:
No user programmable features
Set to 0
00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz
0 or 1
0
8
0
FAud0
AudioClk Freq Bit 0
00 to 10
8
1
FAud1
AudioClk Freq Bit 1
8
2
VCR
Enable VCR Mode
High = Enabled, Low = Disabled
8
3
SLEEP
Power Down Mode
High = Power Down, Low = Normal
9
0
Thresh0
Select ‘Out of Lock’ Threshold
00 = 2.5 Pixels
10 = 1.0 Pixels
9
1
Thresh1
01 = 2.5 Pixels
11 = 4.0 Pixels
9
2
VGA
Enable VGA Mode
High = Enabled, Low = Disabled
0 or 1
9
3
Div4
Enable /4 on M/N Loop
High = Enabled, Low = Disabled
0 or 1
10
0
FStd0
Freq Std Sel Bit 0
000 = NTSC Sq Pix
011 = PAL 601
10
1
FStd1
Freq Std Sel Bit 1
001 = PAL Sq Pix
100 = NTSC 4Fsc
10
2
FStd2
Freq Std Sel Bit 2
010 = NTSC 601
101 = PAL 4Fsc
10
3
PALXTAL
Enable PAL Ref Freq
High = Enabled, Low = Disabled
0 or 1
00 to 11
000 to 101
0 or 1
Table 10. ML6430 Register Map (Continued)
19
ML6430/ML6431
REGISTER
DATA
BIT
DESCRIPTION
0
0
PulsePol 0
CSYNC Polarity
High Active-Low Active
0 or 1
0
1
PulsePol 1
H/V Blank Polarity
High Active-Low Active
0 or 1
0
2
PulsePol 2
S/B Clamp Polarity
High Active-Low Active
0 or 1
0
3
Clk 4X
Select 4X Clock
Low 1X Clock = 13.5MHz
High 4X Clock = 54MHz
0 or 1
1
0
Pixel0
Pix Counter Load Bit 0
1
1
Pixel1
Pix Counter Load Bit 1
1
2
Pixel2
Pix Counter Load Bit 2
1
3
Pixel3
Pix Counter Load Bit 3
2
0
Pixel4
Pix Counter Load Bit 4
2
1
Pixel5
Pix Counter Load Bit 5
2
2
Pixel6
Pix Counter Load Bit 6
2
3
Pixel7
Pix Counter Load Bit 7
3
0
Pixel8
Pix Counter Load Bit 8
3
1
Pixel9
Pix Counter Load Bit 9
3
2
Pixel10
Pix Counter Load Bit 10
3
3
Burst
Burst Gate Enable
Low = Back Porch Clamp
High = Burst Gate
0 or 1
4
0
CSyncRaw
(or CSYNC Regen)
Low = regenerated CSYNC
High = raw CSYNC
0 or 1
4
1
RawClamp
(or Clamp Regen)
Low = regenerated Clamp
High = raw Clamp
0 or 1
4
2
TTL Sync
TTL horizontal + vertical
Sync Input
Low = sync separator active
High = TTL horiz + vert sync input
0 or 1
4
3
WideBlank
(or Narrow)
Low = narrow blanking
High = wide blanking
0 or 1
5
0
HDelay0
5
1
HDelay1
5
2
HDelay2
5
3
HDelay3
6
0
HDelay4
6
1
HDelay5
6
2
HDelay6
6
3
Noise Gating 3/4 line lockout
H Delay parameter allows
moving the entire constellation
of output pulses relative to the
incoming HSYNC. Exception:
Sync Tip clamp may be
selected for delay or triggered
from incoming sync
depending on application.
VALUE RANGE
Numerical value taken as unsigned
binary. Actual no. of pixels is:
512 +
P 10:0
2
nom = ~011 0000 0000
Do not vary pixel [10:0] by more than max = 011 0011 0000
±6% from nominal.
min = 010 1101 0000
1024 > no. of pixels > 512 and
fNOM x 1.06 > fNEW > fNOM x 0.94
If PHERR enable and VGA = 1, the
actual no. of pixels is:
P[10:0]=2x(no. of pixels per line)–512
0000000 to 1111111:
7-bit Horizontal Delay parameter.
Values:
–64p < Hdly < 63p, p = 1/F4XCLK
0000000 means –64p
1111111 means +63p
1000000 means 0p
Low = noise gating on
High = noise gating off
Table 11. ML6431 Register Map
20
BIT CODE
RANGE
0 or 1
ML6430/ML6431
REGISTER
DATA
BIT
7
0
DisAutoVCR
7
1
Test 1
7
7
2
3
DESCRIPTION
VALUE RANGE
0=Auto VCR Detect ON
1=Disable Auto VCR Detect
For test mode only:
No user programmable features. Set to 0
BIT CODE
RANGE
0 or 1
0
Ext 54
Clock IN
Low = Pin 3 is SLEEP
High = Pin 3 is Ext 54MHz Clock
0 or 1
PHERROUT or AUDIOCLK
Low=Pin 16 is Audio CLK, Pin 3 is
SLEEP
High=Pin 16 is PHERROUT, Pin 3
is RESET
0 or 1
8
0
FAud0
AudioClk Freq Bit 0
00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz
00 to 10
8
1
FAud1
AudioClk Freq Bit 1
8
2
VCR
Enable VCR Mode
High = Enabled, Low = Disabled
8
3
SLEEP
Power Down Mode
High = Power Down, Low = Normal
9
0
Thresh0
Select ‘Out of Lock’ Threshold
00 = 2.5 Pixels
10 = 1.0 Pixels
9
1
Thresh1
01 = 2.5 Pixels
11 = 4.0 Pixels
9
2
VGA
Enable VGA Mode
High = Enabled, Low = Disabled
0 or 1
9
3
Div4
Enable /4 on M/N Loop
High = Enabled, Low = Disabled
0 or 1
10
0
FStd0
Freq Std Sel Bit 0
000 = NTSC SqPix
011 = PAL 601
10
1
FStd1
Freq Std Sel Bit 1
001 = PAL Sq Pix
100 = NTSC 4Fsc
10
2
FStd2
Freq Std Sel Bit 2
010 = NTSC 601
10
3
PALXTAL
Enable PAL Ref Freq
High = Enabled, Low = Disabled
00 to 11
000 to 100
0 or 1
Table 11. ML6431 Register Map (Continued)
21
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
SERIAL BUS OPERATION
4. Data Shifted : Clock Cycle 10 through 17
The serial bus control in the ML6430/ML6431 has two
levels of addressing: Device Addressing and Register
Addressing.
5. Data Strobed into Appropriate Register: Clock Cycle 18
Device Addressing: Figure 5 shows the physical
waveforms generated in order to address the ML6430/
ML6431. There are six basic parts of the waveform:
Register Addressing: Figure 6 shows the register map of
the ML6430/6431. There are two basic parts of each
received data byte: Address Nibble and Data Nibble
6. Stop indication: Clock Cycle 19
1. Start Indication: Clock Cycle 0
1. Address Nibble: The upper 4 bits of the data byte
gives the register number in which to place the
data.
2. Device Address Shifted: Clock Cycle 1 through 8
2. Data Nibble: The lower 4 bits of the data byte is
the data to be placed in the currently addressed
register nibble.
3. Device Address Strobed and Decoded: Clock Cycle 9
START
SDATA
tRISE
tFALL
All Other SDATA Transitions Must Occur While SCLK is Low
tSET/START
SCLK
STOP
START: A Falling Edge on the SDATA While SCLK is Held High
STOP: A Rising Edge on the SDATA While SCLK is Held High
Figure 5. Definition of START & STOP on Serial Data Bus
MSB
SDATA
A7
MSB
A6
A1
A0
D7
D6
D1
D0
STOP
SCLK
0
1
2
7
8
9
10
11
16
17
SCLK:
9th pulse strobes address decoder
SDATA: Rising edge with SCLK Hi = STOP
SCLK:
Rising edge enables data transfer
SDATA: Value set low in prep for STOP
SCLK:
18th pulse strobes data shift register
SCLK:
Falling edge disables data transfer
SCLK:
Rising edge enables data transfer
SCLK:
Rising edge enables data transfer
SDATA: Value set to D6, Data MSB-1
SDATA: Value set to A6, Device Address (MSB-1)
SDATA: Value set to A7, Device Address MSB
SCLK:
Falling edge in prep for first address transfer
SDATA; Falling edge with SCLK Hi means start of sequence
SCLK:
Falling edge disables data transfer
SCLK:
Rising edge enables data transfer
SDATA: Value set to D7, Data MSB
Figure 6. Definition of DATA FORMAT on Serial Data Bus
22
18
ML6430/ML6431
SDATA
STROBE
‘1’
‘0’
‘1’
‘1’
‘0’
‘0’
‘1’
‘0’
Ø
R3
DEVICE ADDR = ‘B2’
1
2
3
SCLK:
4
5
R1
R0
D3
6
7
9
8
A
B
D1
D0
Ø
H
I
DATA
C
D
E
F
G
Address decode strobed on 9th clock
SDATA: Final Clock strobes data into register
[Data is ‘don’t care’ during strobe]
SDATA: Second 4 bits are Register Data
SDATA: ‘1011 0010’ shifted on next 8 clocks
SCLK:
D2
REGISTER
SUB-ADDR
SCLK
0
R2
SDATA: First 4 bits are Register Address
Falling edge in prep for device address transfer
Figure 7. Typical Serial Bus Command
SDATA
1
0
1
1
0
0
1
0
0
1
1
1
B
C
D
0
1
0
0
G
H
SCLK
START
1
2
3
4
5
6
7
8
9
A
Register Address
Device Address
E
F
I
STOP
Data
Data Strobed into
Strobe in Address
Appropriate Register
Figure 8. Serial Bus Command to Set Bit #2 in Register 7
23
ML6430/ML6431
APPLICATIONS
The ML6430 and ML6431 can be used for a variety of
applications. The following figures provide a basic setup
for the various applications listed below:
Figure 9: ML6430 or ML6431 in NTSC CCIR Applications
Figure 10: ML6430 or ML6431 in PAL CCIR Applications
Figure 11: ML6431 in VGA Application
Figure 12: ML6430 or ML6431 in Audio Applications
Figure 13: ML6430 or ML6431 in Pulse Generator
Applications
24
ML6430/ML6431
5V
5V for 3.54 MHz XTAL or
open for 4.43 MHz XTAL
1.0µF
CVSYNCH OUT
32
P2/SDATA
5V
P3/SCLK
SLEEP/54MHz
5V
VCC S
0.001µF
GND S
CVIN/HSYNC
1.0µF
1.0µF
CVREF
VSYNC
31
29
28
27
HBLANK
CSYNC
BCLAMP/BURST
SCLAMP
VCC D
GND D
30
26
25
1
24
2
23
3
22
4
21
ML6430/ML6431
5
20
6
19
7
18
8
17
16
9
10
11
12
13
14
15
VBLANK
HRESET
FRESET
VCC B
5V
0.1µF
1nF
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
LOCKED
410
AUDIOCLK/PHERROUT*
3.58MHz
or 4.43MHz 400
NOSIGNAL
FREERUN
XTALOUT
XTALIN
75Ω
GND A
CV in
VCC A
0.1µF
P0
P1
0.1µF
1nF
0.1µF
5V LED
5V LED
5V
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A)
*PHERROUT is only available with the ML6431
Figure 9. ML6430/ML6431 in NTSC CCIR Applications Programmed via Preset Pins
25
ML6430/ML6431
5V
5V for 3.54 MHz XTAL or
open for 4.43 MHz XTAL
1.0µF
CVSYNCH OUT
32
P2/SDATA
5V
P3/SCLK
SLEEP/54MHz
+5V
0.1µF
VCC S
0.001µF
GND S
CVIN/HSYNC
1.0µF
1.0µF
CVREF
VSYNC
31
30
29
28
27
HBLANK
CSYNC
BCLAMP/BURST
SCLAMP
VCC D
GND D
0.1µF
P0
P1
5V
26
25
1
24
2
23
3
22
4
21
ML6431
5
20
6
19
7
18
8
17
16
9
10
11
12
13
14
15
VBLANK
HRESET
FRESET
VCC B
5V
0.1µF
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
LOCKED
410
AUDIOCLK/PHERROUT*
3.58MHz
400
or 4.43MHz
NOSIGNAL
FREERUN
XTALOUT
XTALIN
GND A
75Ω
VCC A
CV in
1nF
0.1µF
5V LED
5V LED
5V
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A)
*PHERROUT is only available with the ML6431
Figure 10. ML6430/ML6431 in PAL CCIR Applications Programmed via Preset Pins
26
1nF
ML6430/ML6431
5V
1.0µF
CVSYNCH OUT
32
GND S
CVIN/HSYNC
HSYNC OR CV
1.0µF
CVREF
HBLANK
CSYNC
BCLAMP/BURST
SCLAMP
VCC D
GND D
24
2
23
3
22
4
21
ML6431
5
20
6
19
7
18
8
17
16
9
VCC A
VSYNC
25
10
11
12
13
3.58MHz
or 4.43MHz 400
14
15
410
VBLANK
HRESET
FRESET
VCC B
5V
0.1µF
1nF
GND B
1X CLOCK/4X CLOCK
2X CLOCK
PIXEL CLOCK
OUTPUT
FIELD ID
AUDIOCLK/PHERROUT*
VCC S
0.001µF
26
LOCKED
0.1µF
27
NOSIGNAL
SLEEP/54MHz
5V
28
FREERUN
P3/SCLK
29
XTALOUT
SCLK
30
GND A
P2/SDATA
31
1
XTALIN
SDATA
P0
P1
0.1µF
1nF
0.1µF
5V LED
5V LED
5V
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A)
*PHERROUT is only available with the ML6431
Figure 11. ML6431 in VGA Applications
27
ML6430/ML6431
5V
1.0µF
CVSYNCH OUT
32
GND S
CVIN/HSYNC
1.0µF
CVREF
VSYNC
1.0µF
HBLANK
CSYNC
BCLAMP/BURST
SCLAMP
VCC D
GND D
24
2
23
3
22
4
21
ML6430/ML6431
5
20
6
19
7
18
8
17
16
9
VCC A
CV in
25
75Ω
10
11
12
13
3.58MHz
or 4.43 MHz 400
14
15
LOCKED
VCC S
0.001µF
26
AUDIOCLK/PHERROUT*
0.1µF
27
NOSIGNAL
SLEEP/54MHz
5V
28
FREERUN
P3/SCLK
29
XTALOUT
SCLK
30
XTALIN
P2/SDATA
31
1
GND A
SDATA
P0
P1
0.1µF
VBLANK
HRESET
FRESET
VCC B
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
AUDIO CLOCK OUT
410
1nF
0.1µF
5V LED
5V LED
5V
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A)
Note 2. See Table 4 for audio clock frequencies and registers
*PHERROUT is only available with the ML6431
Figure 12. ML6430/ML6431 in Audio Applications
28
5V
0.1µF
1nF
ML6430/ML6431
5V
1.0µF
CVSYNCH OUT
32
1.0µF
CVREF
VSYNC
1.0µF
CV in
HBLANK
CSYNC
SCLAMP
BCLAMP/BURST
GND D
2
23
3
22
4
21
ML6430/ML6431
5
20
6
19
7
18
8
17
16
9
VCC A
NO
INPUT NEEDED
25
75Ω
10
11
12
13
3.58MHz
or 4.43 MHz 400
14
15
AUDIOCLK/PHERROUT*
CVIN/HSYNC
26
LOCKED
GND S
27
24
FREERUN
VCC S
0.001µF
28
NOSIGNAL
0.1µF
29
XTALOUT
SLEEP/54MHz
5V
30
XTALIN
P3/SCLK
31
1
GND A
P2/SDATA
P0
P1
See Table 7
for Available
Standards
VCC D
0.1µF
VBLANK
HRESET
FRESET
VCC B
5V
0.1µF
1nF
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
AUDIO CLOCK OUT
410
1nF
0.1µF
5V LED
5V LED
5V
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A)
Note 2. See Table 4 for audio clock frequencies and registers
*PHERROUT is only available with the ML6431
Figure 13. ML6430/ML6431 in Pulse Generator Applications
29
ML6430/ML6431
NTSC AT SQUARE PIXEL RATE
SYMBOL
NAME:
DESCRIPTION
PAL AT SQUARE PIXEL RATE
CCIR 601STD
TYP
UNITS
SYMBOL
NAME:
DESCRIPTION
CCIR 601STD
TYP
UNITS
N HA
Clocks per H:
Active
640
648
cycles
N HA
Clocks per H:
Active
768
767
cycles
NH
Clocks per H:
Whole Line
780
780
cycles
NH
Clocks per H:
Whole Line
944
944
cycles
NVA
H per Frame:
Active
486
493,507
lines
NVA
H per Frame:
Active
609, 616
lines
NV
H per Frame:
Whole Line
525
525
lines
NV
H per Frame:
Whole Line
625
lines
NVBLKW Lines of Blanking:
Wide
16
15
lines
NVBLKW Lines of Blanking:
Wide
15
lines
NVBLKN
Lines of Blanking:
Narrow
9
9
lines
NVBLKN Lines of Blanking:
Narrow
9
lines
tH
H Line Time
63.55
63.55
µs
tH
H Line Time
64.0
64.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHSW
H Sync Width
4.7
4.73
µs
tHSW
H Sync Width
4.7
4.68
µs
tHRW
H Reset Width
41
µs
tHRW
H Reset Width
34
µs
tHEQW
Equalizer Sync
Width
2.28
µs
tHEQW
Equalizer Sync
Width
2.35
2.31
µs
27.05
µs
tHSERRW Serration Sync
Width
27.3
27.32
µs
2.35
tHSERRW Serration Sync
Width
625
tHSTC
Sync Tip Clamp
Pulse
300
122
ns
t HSTC
Sync Tip Clamp
Pulse
300
102
ns
tHSTCW
Sync Tip Clamp
Width
1.5
1.47
µs
t HSTCW
Sync Tip Clamp
Width
1.5
1.49
µs
tHBPC
BurstPulse
300
326
ns
t HBPC
BurstPulse
300
339
ns
tHBPGW
BurstWidth
2.51
2.44
µs
t HBPGW BurstWidth
2.43
2.44
µs
tHBPCW
B Clamp Width
4.0
3.91
µs
t HBPCW B Clamp Width
4.0
4.0
µs
tHBLK
H Blanking Pulse
–1.5
–1.39
µs
tHBLK
H Blanking Pulse
–1.5
–1.49
µs
tHBLKW
H Blanking Pulse
Width
10.9
10.76
µs
tHBLKW
H Blanking Pulse
Width
12.0
12.0
µs
Table 12. Pulse Output Timing
30
ML6430/ML6431
NTSC AT 4 X FS RATE
SYMBOL
NAME:
DESCRIPTION
PAL AT 4 X FS RATE
CCIR 601STD
TYP
UNITS
SYMBOL
NAME:
DESCRIPTION
CCIR 601STD
TYP
UNITS
N HA
Clocks per H:
Active
768
752
cycles
N HA
Clocks per H:
Active
922
922
cycles
NH
Clocks per H:
Whole Line
910
910
cycles
NH
Clocks per H:
Whole Line
1135.0064
1135
cycles
NVA
H per Frame:
Active
486
493,507
lines
NVA
H per Frame:
Active
609, 616
lines
NV
H per Frame:
Whole Line
525
525
lines
NV
H per Frame:
Whole Line
625
lines
NVBLKW Lines of Blanking:
Wide
16
15
lines
NVBLKW Lines of Blanking:
Wide
15
lines
NVBLKN
Lines of Blanking:
Narrow
9
9
lines
NVBLKN
Lines of Blanking:
Narrow
9
lines
tH
H Line Time
63.55
63.55
µs
tH
H Line Time
64.0
64.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHSW
H Sync Width
4.7
4.68
µs
tHSW
H Sync Width
4.7
4.74
µs
tHRW
H Reset Width
35
µs
tHRW
H Reset Width
28
µs
tHEQW
Equalizer Sync
Width
2.35
2.30
µs
tHEQW
Equalizer Sync
Width
2.35
2.25
µs
tHSERRW
Serration Sync
Width
27.05
27.02
µs
tHSERRW Serration Sync
Width
27.3
27.29
µs
tHSTC
Sync Tip Clamp
Pulse
300
105
ns
tHSTC
Sync Tip Clamp
Pulse
300
169
ns
tHSTCW
Sync Tip Clamp
Width
1.5
1.47
µs
tHSTCW
Sync Tip Clamp
Width
1.5
1.58
µs
tHBPC
BurstPulse
300
349
ns
tHBPC
BurstPulse
300
225
ns
tHBPGW
BurstWidth
2.51
2.51
µs
tHBPGW
BurstWidth
2.43
2.48
µs
tHBPCW
B Clamp Width
4.0
3.98
µs
tHBPCW
B Clamp Width
4.0
4.06
µs
tHBLK
H Blanking Pulse
–1.5
–1.54
µs
tHBLK
H Blanking Pulse
–1.5
–1.52
µs
tHBLKW
H Blanking Pulse
Width
10.9
11.03
µs
tHBLKW
H Blanking Pulse
Width
12.0
12.12
µs
625
Table 12. Pulse Output Timing (Continued)
31
ML6430/ML6431
NTSC AT CCIR601 RATE
SYMBOL
NAME:
DESCRIPTION
PAL AT CCIR601 RATE
CCIR 601STD
TYP
UNITS
SYMBOL
NAME:
DESCRIPTION
CCIR 601STD
TYP
UNITS
N HA
Clocks per H:
Active
720
709
cycles
N HA
Clocks per H:
Active
720
702
cycles
NH
Clocks per H:
Whole Line
858
858
cycles
NH
Clocks per H:
Whole Line
864
864
cycles
NVA
H per Frame:
Active
486
493, 507
lines
NVA
H per Frame:
Active
609, 616
lines
NV
H per Frame:
Whole Line
525
525
lines
NV
H per Frame:
Whole Line
625
lines
NVBLKW Lines of Blanking:
Wide
16
15
lines
NVBLKW Lines of Blanking:
Wide
15
lines
NVBLKN Lines of Blanking:
Narrow
9
9
lines
NVBLKN
Lines of Blanking:
Narrow
9
lines
625
tH
H Line Time
63.55
63.55
µs
tH
H Line Time
64.0
64.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHS
H Sync Time
0.0
0.0
µs
tHSW
H Sync Width
4.7
4.67
µs
tHSW
H Sync Width
4.7
4.67
µs
tHRW
H Reset Width
37
µs
tHRW
H Reset Width
37
µs
tHEQW
Equalizer Sync
Width
2.35
2.37
µs
tHEQW
Equalizer Sync
Width
2.35
2.30
µs
tHSERRW Serration Sync
Width
27.05
27.04
µs
tHSERRW Serration Sync
Width
27.30
27.33
µs
t HSTC
Sync Tip Clamp
Pulse
300
111
ns
tHSTC
Sync Tip Clamp
Pulse
300
111
ns
t HSTCW
Sync Tip Clamp
Width
1.5
1.48
µs
tHSTCW
Sync Tip Clamp
Width
1.5
1.48
µs
t HBPC
BurstPulse
300
370
ns
tHBPC
BurstPulse
300
370
ns
tHBPGW BurstWidth
2.51
2.44
µs
tHBPGW
BurstWidth
2.43
2.44
µs
t HBPCW B Clamp Width
4.0
4.10
µs
tHBPCW
B Clamp Width
4.0
4.0
µs
tHBLK
H Blanking Pulse
–1.5
–1.55
µs
tHBLK
H Blanking Pulse
–1.5
–1.48
µs
tHBLKW
H Blanking Pulse
Width
10.9
11.03
µs
tHBLKW
H Blanking Pulse
Width
12.0
12.0
µs
Table 12. Pulse Output Timing (Continued)
32
ML6430/ML6431
PHYSICAL DIMENSIONS
inches (millimeters)
Package: H32-7
32-Pin (7 x 7 x 1mm) TQFP
0.354 BSC
(9.00 BSC)
0.276 BSC
(7.00 BSC)
0º - 8º
0.003 - 0.008
(0.09 - 0.20)
25
1
PIN 1 ID
0.276 BSC
(7.00 BSC)
0.354 BSC
(9.00 BSC)
0.018 - 0.030
(0.45 - 0.75)
17
9
0.032 BSC
(0.8 BSC)
0.048 MAX
(1.20 MAX)
0.012 - 0.018
(0.29 - 0.45)
SEATING PLANE
0.037 - 0.041
(0.95 - 1.05)
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML6430CH
0°C to 70°C
32-Pin TQFP (H32-7)
ML6431CH (EOL)
0°C to 70°C
32-Pin TQFP (H32-7)
© Micro Linear 2000.
property of their respective owners.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
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Fax: 408/432-0295
www.microlinear.com
DS6430_31-01
33
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