OKI ML9090A-01GA Lcd driver with key scanner and ram Datasheet

FEDL9090A-01
1Semiconductor
ML9090A-01, -02
This version:
May 2001
LCD Driver with Key Scanner and RAM
GENERAL DESCRIPTION
The ML9090A-01 and ML9090A-02 are LCD drivers that contain internal RAM and a key scan function. They are
best suited for car audio displays.
Since 1-bit data of the display data RAM corresponds to the light-on or light-off of 1-dot of the LCD panel (a bit
map system), a flexible display is possible.
A single chip can implement a graphic display system of a maximum of 80 × 18 dots (80 × 10 dots for the
ML9090A-01, 80 × 18 dots for the ML9090A-02).
Since containing voltage multipliers, the ML9090A-01 and ML9090A-02 require no power supply circuit to drive
the LCD.
Since the internal 5 × 5 scan circuit has eliminated the needs of key scanning by the CPU, the ports of the CPU can
be efficiently used.
FEATURES
•
•
•
•
•
•
•
•
•
•
Logic voltage: 2.7 to 5.5 V
LCD drive voltage: 6 to 16 V (positive voltage)
80 segment outputs, 10 common outputs for ML9090A-01 and 18 common outputs for ML9090A-02
Built-in bit-mapped RAM (ML9090A-01: 80 × 10 = 800 bits, ML9090A-02: 80 × 18 = 1440 bits)
4-pin serial interface with CPU: CS, CP, DI/O, KREQ
Built-in LCD drive bias resistors
Built-in voltage doubler or tripler circuit
Built-in 5 × 5 key scanner
Port A output
: 1 pin, output current: –15 mA: (may be used for LED driving)
Port B output
: 8 pins
Output current (available for the ML9090A-01 only)
–2 mA : 5 pins
–15 mA : 3 pins
• Temperature range: –40 to +85°C
• Package: 128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: ML9090A-01GA)
(Product name: ML9090A-02GA)
Comparison between the ML9090A-01 and the ML9090A-02
Item
ML9090A-01
ML9090A-02
Number of common outputs
10 Max.
18 Max.
8 × 80
16 × 80
Number of dots on the LCD screen
(selectable by program)
9 × 80
17 × 80
10 × 80
18 × 80
Number of port A outputs
1
1
Number of port B outputs
8
—
1/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
BLOCK DIAGRAM (1/2)
ML9090A-01
COM1
VOLTAGE
DOUBLER/
TRIPLER
COM10 PB0
10-OUT
COMMON
DRIVER
PB7 SEG1
SEG80
8-PORT
80-OUT SEGMENT DRIVER
DRIVER
SHIFT
REGISTER
CS
CP
DI/O
DISPLAY DATA RAM
80 × 10 BITS
I/O
BUFFER
CONTROL
REGISTER
INPUT OUTPUT
INTERFACE
CIRCUIT
DISPLAY LINE COUNTER
DIVIDING
V3A
Y ADDRESS DECODER
VOLTAGE
V3B
Y ADDRESS COUNTER
LCD BIAS
Y ADDRESS REGISER
V2
DATA LATCH
LINE ADDRESS DECODER
VIN
VC1
VC2
VS1
VS2
DT
X ADDRESS DECODER
X ADDRESS COUNTER
TIMING
GENERATOR
X ADDRESS REGISTER
OSC1
OSC2
OSCILLATION
CIRCUIT
1 PORT
DRIVER
5 × 5 KEY SCANNER
RESET
TEST
PA0
VDD
VSS
C0 C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
BLOCK DIAGRAM (2/2)
ML9090A-02
COM1
VIN
VC1
VC2
VS1
VS2
DT
VOLTAGE
DOUBLER/
TRIPLER
COM18
SEG1
SEG80
18-OUT
COMMON DRIVER
80-OUT SEGMENT DRIVER
SHIFT REGISTER
DATA LATCH
CP
DI/O
DISPLAY LINE COUNTER
LINE ADDRESS DECODER
DISPLAY DATA RAM
80 × 18 BITS
I/O
BUFFER
CONTROL
REGISTER
CS
INPUT OUTPUT
INTERFACE
V3A
Y ADDRESS DECODER
Y ADDRESS REGISER
V3B
LCD BIAS
VOLTAGE
DIVIDING
CIRCUIT
Y ADDRESS COUNTER
V2
X ADDRESS DECODER
X ADDRESS COUNTER
TIMING
GENERATOR
X ADDRESS REGISTER
OSC1
OSC2
OSCILLATION
CIRCUIT
1 PORT
DRIVER
5×5
KEY SCANNER
RESET
TEST
PA0
VDD
VSS
C0 C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
PIN CONFIGURATION (TOP VIEW) 1/2
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
78
26
77
27
76
28
75
29
74
30
73
31
72
32
71
33
70
34
69
35
68
36
67
37
66
38
65
VDD
OSC2
OSC1
DT
V2
V3B
V3A
VIN
VC1
VC2
VS1
VS2
VSS
TEST
RESET
KREQ
DI/O
CS
CP
C0
C1
C2
C3
C4
R0
R1
R2
R3
R4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
64
79
25
63
80
24
62
81
23
61
82
22
60
83
21
59
84
20
58
85
19
57
86
18
56
87
17
55
88
16
54
89
15
53
90
14
52
91
13
51
92
12
50
93
11
49
94
10
48
95
9
47
96
8
46
97
7
45
98
6
44
99
5
43
100
4
42
3
41
101
40
102
2
39
1
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
127
128
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
ML9090A-01
128-pin plastic QFP
4/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
PIN CONFIGURATION (TOP VIEW) 2/2
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
78
26
77
27
76
28
75
29
74
30
73
31
72
32
71
33
70
34
69
35
68
36
67
37
66
38
65
VDD
OSC2
OSC1
DT
V2
V3B
V3A
VIN
VC1
VC2
VS1
VS2
VSS
TEST
RESET
KREQ
DI/O
CS
CP
C0
C1
C2
C3
C4
R0
R1
R2
R3
R4
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
64
79
25
63
80
24
62
81
23
61
82
22
60
83
21
59
84
20
58
85
19
57
86
18
56
87
17
55
88
16
54
89
15
53
90
14
52
91
13
51
92
12
50
93
11
49
94
10
48
95
9
47
96
8
46
97
7
45
98
6
44
99
5
43
100
4
42
3
41
101
40
102
2
39
1
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
127
128
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
PA0
ML9090A-02
128-pin plastic QFP
5/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
Function
CPU interface
Pin
Symbol
Type
85
CS
I
Chip select signal input pin
CP
I
Shift clock signal input pin. This pin is
connected to an internal Schmitt circuit
84
86
DI/O
I/O
Serial data signal I/O pin
87
KREQ
O
Key request signal output pin
100
OSC1
I
101
OSC2
O
Connect external resistors.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Oscillation
88
RESET
I
Initial settings can be established by
pulling the reset input to a “L” level. This
pin is connected to an internal Schmitt
circuit.
99
DT
I
Input pin for selecting the voltage doubler
or voltage tripler.
89
TEST
I
Test input pin. This pin is connected to the
VSS pin.
83 to 79
C0 to C4
I
Input pins that detect status of key
switches
78 to 74
R0 to R4
O
Key switch scan signal output pins
Control signals
Key scan signals
Port outputs
LCD driver outputs
Power supply
Description
103
PA0
O
Port A output
111 to 104
PB0 to PB7
O
Port B outputs (for ML9090A-01)
73 to 122
SEG1 to
SEG80
O
Outputs for LCD segment drivers
121 to 112
COM1 to
COM10
O
Outputs for LCD common drivers
(for ML9090A-01)
121 to 104
COM1 to
COM18
O
Outputs for LCD common drivers
(for ML9090A-02)
102
VDD
—
Logic power supply pin
90
VSS
—
GND pin
95
VIN
—
Voltage multiplier reference voltage power
supply pin
94, 93
VC1, VC2
—
Capacitor connection pins for voltage
multiplier
92
VS1
—
Voltage multiplier output pin
91
VS2
—
Voltage multiplier output pin
98, 96, 97
V2, V3A, V3B
—
LCD bias pins
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Pin Functional Descriptions
• CS
Chip select input pin. An “L” level selects the chip, and an “H” level does not select the chip. During the “L” level,
internal registers can be accessed.
• CP
Clock input pin for serial interface data I/O. An internal Schmitt circuit is connected to this pin. Data input to the
DI/O pin is synchronized to the rising edge of the clock. Output from the DI/O pin is synchronized to the falling
edge of the clock.
• DI/O
Serial interface data I/O pin. This pin is in the output state only during the interval beginning when key scan data
read or RAM read commands are written until the CS signal rises. At all other times this pin is in the input state.
(When reset, the input state is set.) In other words, this pin goes into the output state only when the key scan
register or the display data RAM is read. The relation between data level of this pin and operation is listed below.
Data level
LCD display
Port
Key status
“H”
Light ON
“H”
ON
“L”
Light OFF
“L”
OFF
• KREQ
Key scan read READY signal output pin. Two scan cycles after a key switch is switched ON, this pin goes to an
“H” level. When all key switches are OFF, this pin returns to an “L” level.
This signal can be used as a flag. To use it as a flag, start the key-scan reading when the KREQ signal changes to
an “H” level from an “L” level. If the key-scan reading starts when the KREQ signal changes to an “L” level from
an “H” level, scanned data may be unstable. To avoid this, repeat the key-scan reading three times.
When the key-scan reading starts when this pin goes to an “L” level, data when a key switch is off is read.
• OSC1
Input pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56kΩ ±2% to this pin
and the OSC2 pin. If an external master oscillation clock is to be input, input the master oscillation clock to this
pin.
OSC1
R = 56 kΩ
(VDD = 2.7 to 5.5 V)
R
OSC2
• OSC2
Output pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56kΩ ±2% to this pin
and the OSC1 pin. If an external master oscillation clock is to be input, leave this pin unconnected (open).
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
• RESET
Reset signal input pin. The initial state can be set by pulling this pin to an “L” level. Refer to the “Output, I/O and
Register States in Response to Reset Input” page for the initial states of each register and display.
An internal pull-up resistor is connected to this pin. An external capacitor is connected for power-on-reset
operation.
• TEST
Test signal input pin. This pin is used for testing by Oki. Connect this pin to VSS. When a different connection is
made, proper operation cannot be guaranteed.
• R0 to R4
Key switch scan signal output pins. During the scan operation, “L” level signals are output in the order of R0,
R1, ...R4. (Refer to the page entitled “Key scan” for details.)
• C0 to C4
Input pins that detect the key switch status. Internal pull-up resistors are connected to these pins. Assemble a key
matrix between these pins and the R0 to R4 pins.
• PA0
General-purpose port A output pin. Because this pin can output a current of –15 mA, it is best suited as an LED
driver. If this pin is used as an LED driver, insert an external current limiting resistor in series with the LED. If this
pin is not used, leave it unconnected (open).
• PB0 to PB7
General-purpose port B output pins. Each of the PB5 to PB7 pins has the same driving capability as the PA0 pin,
namely the ability to output a current of –15 mA. These pins are only applicable to the ML9090A-01. Leave
unused pins unconnected (open).
• SEG1 to SEG80
Segment signal output pins for LCD driving. Leave unused pins unconnected (open).
• COM1 to COM18
Common signal output pins for LCD driving. Leave unused pins unconnected (open). COM11 to COM18 are
provided for the ML9090A-02 and PB0 to PB7 for the ML9090A-01.
• VDD
Logic power supply connection pin.
• VSS
Power supply GND connection pin.
• DT
This pin selects the voltage multiplier circuit. If this pin is connected to the VSS pin, the voltage doubler circuit is
selected. If this pin is connected to the VDD pin, the voltage tripler circuit is selected. Do not change the value of the
setting after power is turned on.
• VC1, VC2
Capacitor connection pins for the voltage multiplier. Connect a 4.7 µF capacitor between the VC1 and VC2 pins. If
an electrolytic capacitor is used, connect the (+) side to pin VC2.
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
• VS1
Voltage doubler voltage output pin. This pin outputs the doubled voltage that has been input to VIN. To increase
stability of the power supply, connect a 4.7 µF capacitor between this pin and VSS. When using the doubled voltage,
connect this pin and VS2.
• VS2
Voltage multiplier voltage output pin. Voltage multiplied by the factor specified by the DT pin setting is output
from this pin. When the voltage tripler is used, to increase stability of the power supply, connect a 4.7 µF capacitor
between this pin and VSS. When using the voltage doubler, connect this pin and VS1.
• VIN
Voltage multiplier voltage input pin. The doubled or tripled voltage input to this pin is output from VS1 or VS2.
• V2, V3A, V3B
LCD bias pins for segment drivers. These pins are connected to internal bias dividing resistors. When using the
ML9090A-01 (at 1/4 bias), connect V2 and V3A pins, and leave V3B unconnected (open). When using the
ML9090A-02 (at 1/5 bias), connect V3A and V3B pins, and leave V2 unconnected (open).
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Symbol
Condition
Rating
Unit
VDD
Ta = 25°C
–0.3 to +7.0
V
VDD
V
VC1, VC2, VS1, VS2,
V2,V3A, V3B
V
VIN
Bias Voltage
VBI
Ta = 25°C
Voltage Multiplier
ReferenceVoltage
VIN
Input Voltage
VI
Output Current
IO
Ta = 25°C
Power Dissipation
PD
Ta = 85°C
Storage Temperature
Tstg
—
–0.3 to +18.0
Ta = 25°C
*1
–0.3 to +9.0
Ta = 25°C
*2
–0.3 to +6.0
Applicable Pins
Ta = 25°C
–0.3 to VDD +0.3
V
CS, CP, DI/O,OSC1,
RESET, DT,TEST, C0
to C4
Ta = 25°C
–20
mA
PA0, PB5 to PB7
–3
mA
PB0 to PB4
190
mW
—
–55 to +150
°C
—
VSS is the reference voltage potential for all pins.
*1:
*2:
When the voltage doubler is used.
When the voltage tripler is used.
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
Unit
Applicable Pins
Power Supply Voltage
Parameter
VDD
—
2.7 to 5.5
V
VDD
Bias Voltage
VS2
—
6.0 to 16.0
V
VS2
Voltage Multiplier
ReferenceVoltage
VIN
*1
3.55 to 8.00
*2
2.84 to 5.33
V
VIN
Operating Frequency
fop
R = 56kΩ ±2%
480 to 1200
kHz
OSC1
Operating Temperature
Top
—
–40 to +85
°C
—
VSS is the reference voltage potential for all pins.
*1:
*2:
When the voltage doubler is used.
When the voltage tripler is used.
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
ELECTRICAL CHARACTERISTICS
OSC Circuit Operating Conditions
Parameter
Oscillation Resistance
*1:
Symbol
Condition
Rating
Unit
Applicable Pins
R
VDD = 2.7 V to 5.5 V
56 *1
kΩ
OSC1, OSC2
Use a resistor with an accuracy of ±2 %
OSC1
R
OSC2
11/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = –40 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Applicable Pins
“H” Input Voltage 1
VIH1
—
0.85VDD
—
—
V
OSC1
“H” Input Voltage 2
VIH2
—
0.85VDD
—
—
V
RESET
“H” Input Voltage 3
VIH3
—
0.85VDD
—
—
V
CP
“H” Input Voltage 4
VIH4
—
0.8VDD
—
—
V
CS, DI/O,C0 to C4
“L” Input Voltage 1
VIL1
—
—
—
0.15VDD
V
OSC1
“L” Input Voltage 2
VIL2
—
—
—
0.15VDD
V
RESET
“L” Input Voltage 3
VIL3
—
—
—
0.15VDD
V
CP
“L” Input Voltage 4
VIL4
—
—
—
0.2VDD
V
CS, DI/O,C0 to C4
“H” Input Current 1
IIH1
VI = VDD
—
—
10
µA
RESET
“H” Input Current 2
IIH2
VI = VDD
—
—
10
µA
C0 to C4
“H” Input Current 3
IIH3
VI = VDD
—
—
10
µA
DI/O
“H” Input Current 4
IIH4
VI = VDD
—
—
1
µA
OSC1, CS, CP,DT,
TEST
“L” Input Current 1
IIL1
VDD = 5 V, VI = 0 V
–0.02
–0.05
–0.1
mA
RESET
“L” Input Current 2
IIL2
VDD = 5 V, VI = 0 V
–0.18
–0.45
–0.9
mA
C0 to C4
“L” Input Current 3
IIL3
VI = 0 V
—
—
–10
µA
“L” Input Current 4
IIL4
VI = 0 V
—
—
–1
µA
“L” Input Current 5
IIL5
VDD = 3 V, VI = 0 V
–4
–10
–25
µA
DI/O
OSC1, CS, CP,DT,
TEST
RESET
IIL6
VDD = 3 V, VI = 0 V
–0.04
–0.1
–0.2
mA
C0 to C4
“H” Output Voltage 1
VOH1
IO = –0.4 mA
VDD – 0.4
—
—
V
DI/O, KREQ
“H” Output Voltage 2
VOH2
IO = –40 µA
0.9VDD
—
—
V
OSC2
“H” Output Voltage 3
VOH3
IO = –15 mA
VDD – 1.7
—
—
V
PA0, PB5 to PB7
“H” Output Voltage 4
VOH4
IO = –2 mA
VDD – 1.2
—
—
V
PB0 to PB4
“H” Output Voltage 5
VOH5
IO = –50 µA
VDD – 2.0
—
—
V
R0 to R4
“L” Output Voltage 1
VOL1
IO = 0.4 mA
—
—
0.4
V
DI/O, KREQ
“L” Output Voltage 2
VOL2
IO = 40 µA
—
—
0.1VDD
V
OSC2
“L” Output Voltage 3
VOL3
IO = 1 mA
—
—
0.4
V
PA0, PB0 to PB7
“L” Output Voltage 4
VOL4
IO = 1.8 mA
—
—
0.7
V
R0 to R4
VOS0
IO = –10 µA
VS2 – 0.6
—
—
V
Segment Output
VOS1
IO = ±10 µA
2/4VS2 – 0.6
—
2/4VS2 + 0.6
V
Voltage 1(1/4 bias)
VOS2
IO = ±10 µA
2/4VS2 – 0.6
—
2/4VS2 + 0.6
V
VOS3
IO = +10 µA
—
—
VSS + 0.6
V
“L” Input Current 6
SEG1 to SEG80
12/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = –40 to +85°C)
Parameter
Common Output
Voltage 1
(1/4 bias)
Segment Output
Voltage 2
(1/5 bias)
Common Output
Voltage 2
(1/5 bias)
Symbol
Condition
Min.
Typ.
Max.
Unit
VOC0
IO = –10 µA
VS2 – 0.3
—
—
V
VOC1
IO = ±10 µA
3/4VS2 – 0.3
—
3/4VS2 + 0.3
V
VOC2
IO = ±10 µA
1/4VS2 – 0.3
—
1/4VS2 + 0.3
V
VOC3
IO = +10 µA
—
—
VSS + 0.3
V
VOS0
IO = –10 µA
VS2 – 0.6
—
—
V
VOS1
IO = ±10 µA
3/5VS2 – 0.6
—
3/5VS2 + 0.6
V
VOS2
IO = ±10 µA
2/5VS2 – 0.6
—
2/5VS2 + 0.6
V
COM1 to COM18
SEG1 to SEG80
VOS3
IO = +10 µA
—
—
VSS+0.6
V
VOC0
IO = –10 µA
VS2 – 0.3
—
—
V
VOC1
IO = ±10 µA
4/5VS2 – 0.3
—
4/5VS2 + 0.3
V
VOC2
IO = ±10 µA
1/5VS2 – 0.3
—
1/5VS2 + 0.3
V
VOC3
IO = +10 µA
—
—
VSS + 0.3
V
VIN × 1.83
–0.5
15
VIN × 2
V
VS2
VIN × 2.46
–1.0
13
VIN × 3
V
VS2
—
—
0.95
mA
VDD
—
—
0.7
mA
VDD
—
—
2
mA
VIN
6.3
9
13
kΩ
VS2 – V2, V2 – V3B,
V3A – VSS
External clock =
740 KHz
Voltage Multiplier
Voltage 1
Applicable Pins
VDB
VIN = 3.55 to 8.0 V
1/4 bias
COM1 to COM18
*6
*1
External clock =
740 KHz
Voltage Multiplier
Voltage 2
VTR
VIN = 2.84 to 5.33 V
1/4 bias
*7
*2
Supply Current 1
IDD1
Supply Current 2
IDD2
Supply Current 3
IVIN
LCD Driving Bias
Resistance
LBR
*1:
*2:
*3:
*4:
*6:
*7:
R = 56KΩ
*3
External clock =
740 KHz
*4
R = 56KΩ
Refer to Measuring Circuits 1
Refer to Measuring Circuits 2
Refer to Measuring Circuits 3
Refer to Measuring Circuits 4
VIN = 8 V, Ta = 25°C
VIN = 5.33 V, Ta = 25°C
*3
*5
*5
LBR LBR
VS2
LBR LBR
LBR
V2
V3B
V3A
VSS
13/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Measuring Circuits
Measuring Circuit 1
Voltage multiplier voltage 1
When voltage doubler is used.
1/4 bias
Measuring Circuit 2
Voltage multiplier voltage 2
When voltage tripler is used.
1/4 bias
OPEN
SEG1–SEG80
VDD
VIN
–
4.7µF
±30% +
4.7µF ±30%
+
VDD
VIN
VC1
VC2
4.7µF –
±30% +
4.7µF ±30%
VSS
VS1
PAO
VS2
100µA
OSC2
+
OPEN
OPEN
DT
4.7µF±30%
VDD
V3B
TEST
V3A
RESET
CS
*1
CP
COM11–COM18/
DI/O PB0–PB7 C0–C4
+
VTR
VC1
VC2
VSS
VS1
VS2
VDD
DT
V2
OPEN V3B
V3A
CS
*1
CP COM11–COM18/
DI/O PB0–PB7 C0–C4
VDD
f = 740 kHz
VDD
R0–R4
5.5 V
IVIN
A
5.33 V–
4.7µF
±30% +
IDD2
OPEN
VDD
µ
±30% +
VSS
PAO
OSC2
OSC1
VDD
TEST
RESET
f = 740 kHz
VDD
R0–R4
DT
TEST
V2
V3B
V3A
RESET
CS
*1
CP COM11–COM18/
DI/O PB0–PB7 C0–C4 R0–R4
OPEN
VIN
VC1
VSS
VC2
4.7 µF±30%
VS1
+
R = 56 kΩ 4.7 µF+
±30%
±2%
VDD
SEG1–SEG80 COM1–COM10
VS2
VDD
DT
OPEN V2
V3B
V3A
VDD
CS
CP
DI/O
PAO
OPEN
OSC2
OPEN
OSC1
TEST
RESET
f = 740 kHz
VDD
*1
COM11–COM18/
PB0–PB7 C0–C4
OPEN
*1:
OPEN
OPEN
VDD
5.33 V
–
4.7 F
4.7 µF±30%
VS2
+
VDD
OPEN
5.5 V
VIN
VC1
4.7 µF±30%
VS1
+
OSC2
Measuring Circuit 4
Supply current 2
When voltage tripler is used
A
SEG1–SEG80 COM1–COM10
VC2
OPEN
OPEN
Measuring Circuit 3
Supply current 1
When voltage tripler is used
A
PAO
OSC1
100µA
OPEN
IDD1
COM1–COM10
V
OSC1
V2
OPEN
VDDSEG1–SEG80
VIN
VIN
VDB
V
OPEN
VDD
COM1–COM10
R0–R4
OPEN
PB0 - PB7 for ML9090A-01, and COM11 - COM18 for ML9090A-02
14/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Switching Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = –40 to +85°C)
Parameter
Symbol
Condition
Min
Max
Unit
CP Clock Cycle Time
tSYS
—
1000
—
ns
CP “H” Pulse Width
tWH
—
400
—
ns
CP “L” Pulse Width
tWL
—
400
—
ns
CS “H” Pulse Width
tWCH
—
200
—
ns
CP Clock Rise/fall Time
tr, tf
—
—
100
ns
CS Setup Time
tCSU
—
60
—
ns
CS Hold Time
tCHD
—
290
—
ns
DI/O Setup Time
tDSU
—
100
—
ns
DI/O Hold Time
tDHD
—
15
—
ns
DI/O Output Delay Time
tDOD
CL = 50 pF
—
200
ns
DI/O Output OFF Delay Time
tDOFF
CL = 50 pF
—
200
ns
RESET Pulse Width
tWRE
—
2
—
µs
External Clock Cycle Time
tSES
—
833
—
ns
External Clock “H” Pulse Width
tWEH
—
316
—
ns
tWEL
—
316
—
ns
trE, tfE
—
—
100
ns
External Clock “L” Pulse Width
External Clock Rise/fall Time
Key Scan Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = –40 to +85°C)
Parameter
Symbol
Register
setting
KT
Key Scan Cycle
Tscn
Key Scan Invalid Time
Tnop
Oscillation frequency
Dividing ratio
Unit
480 kHz
740 kHz
1200 kHz
0
1/3780
7.9
5.1
3.1
1
1/7560
15.8
10.2
6.2
0
1/4800
10.0
6.5
4.0
1
1/9600
20.0
13.0
8.0
ms
Frame Frequency Characteristics
(VDD = 2.7 to 5.5 V, VS2 = 6 to 16 V, Ta = –40 to +85°C)
Model
Parameter
Symbol
ML9090A-01
Frame
Frequency
ML9090A-02
FRM
Display duty
Dividing ratio
1/8
1/9
Oscillation frequency
480 kHz
740 kHz
1200 kHz
1/6144
78.1
120.4
195.3
1/6912
69.4
107
173.7
1/10
1/7680
62.5
96.3
156.3
1/16
1/6144
78.1
120.4
195.3
1/17
1/6528
73.5
113.3
183.9
1/18
1/6912
69.4
107
173.7
Unit
Hz
15/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Clock synchronous serial interface timing diagrams
Clock synchronous serial interface input timing
tWCH
– VIH4
– VIL4
CS
tCSU
tSYS
tr tWH tf
tCHD
tWL
– VIH3
– VIL3
CP
tDHD
tDSU
– VIH4
– VIL4
DI/O
Clock synchronous serial interface input/output timing
tWCH
– VIH4
– VIL4
CS
tCSU
tr tWH tf
CP
tWL
8th Clock
1st Clock
VIH4
VIL4
9th Clock
– VIH3
– VIL3
tDOFF
tDOD
tDHD
tDSU
DI/O
tCHD
tSYS
VIH4
VIL4
Hiz
VOH1
VOL1
VOH1
VOL1
Reset timing
tWRE
RESET
– VIL2
External clock
trE tWEH tfE tWEL
– VIH1
– VIL1
OSC1
tSES
16/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Key scan timing
Tscn
Tnop
– VDD
Rn
– VSS
Key switch ON
Scanning starts
Key switch OFF
Scanning stops
Key switch ON
Scanning starts
Frame frequency
– VS2
– V1
COM1
– V4
1/FRM
– VSS
1/FRM
17/41
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
X address register set
Y address register set
Port register A set
Port register B set
Control register 1 set
Control register 2 set
RS
R/W
ST0 to ST2
S0 to S4
D0 to D7
X0 to X3
Y0 to Y4
PTA
PTB0 to PTB7
INC
1
1
1
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
D5
D6
—
—
—
—
—
—
D6
D7
D7
—
—
—
D5
D5
—
Y4
—
D4
D4
S4
D4
—
Y3
X3
D3
D3
S3
D3
—
Y2
X2
D2
D2
S2
D2
—
Y1
X1
D1
D1
S1
D1
Sets the Y address (Y0 to Y4) of the display data RAM.
Sets the X address (X0 to X3) of the display data RAM.
Reads display data (D0 to D7) from the display data RAM
after setting the X address or Y address.
Writes display data (D0 to D7) in the display data RAM
after setting the X address or Y address.
Reads scan read count display bits (ST0 to ST2) and key
scan data (S0 to S4) of the key scan register.
1
0
T3
T2
T4
—
—
—
INC WLS KT SHL
Controls the output of the general-purpose port B (PTB0
—
DISP
T1 to T4
—
1Semiconductor
SHL
1: 6 bits,
0: 8 bits
1: 10 ms,
0: 5 ms
(1/8, 1/9, 1/10) (ML9090A–01)
(1/16, 1/17, 1/18) (ML9090A–02)
: Common driver shift direction select bit
1: COM10 → COM1, 0: COM1 → COM10 (ML9090A-01)
1: COM18 → COM1, 0: COM1 → COM18 (ML9090A-02)
: Display ON/OFF select bit
1: Display ON, 0: Display OFF
: Write “0” to use for test mode
: Don't Care
: Word length select bit
: Key scan cycle select bit
: Display duty select bit
DISP Sets test mode (T1 to T4) and display ON/OFF (DISP).
Sets the address increment X or Y direction (INC), display
data word length (WLS), key scan time (KT), common
DTY1 DTY0 driver shift direction (SHL), and display duty (DTY0,
DTY1).
WLS
KT
DTY0, DTY1
T1
—
Descriptions
PTA Controls the output of the general-purpose port A (PTA).
Y0
X0
D0
D0
S0
D0
1 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 to PTB7).
0
1
0
1
1
0 ST2 ST1 ST0
D6
Instruction code
: Register select bit
1: RAM
0: Register
: Read/write select bit
1: Read
0: Write
: Key scan read count display bits
: Key scan data
: Write or read data of the display data RAM
: X address of the display data RAM
: Y address of the display data RAM
: Port A data
: Port B data (ML9090A-01 only)
: Display data RAM address increment 1 : X direction, 0: Y direction
1
Display data RAM
read
1
1
0
Display data RAM
write
1
RS R/W Register No.
D7
D5 D4 D3 D2 D1 D0
1
Fixed bit
D7 D6
Start byte
Key scan register
read
Instruction
Instruction Code List
FEDL9090A-01
ML9090A-01, -02
18/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Clock Synchronous Serial Transfer Example (WRITE)
Transfer start
Transfer complete
CS
1
2
3
4
5
6
7
8
RS R/W D3
D2
D1
D0
9 10 11 12 13 14 15 16
CP
DI/O
“1” “1”
D7
D6
Register bits
D5
D3
D4
D2 D1
D0
1st byte
Start byte
Instruction
Clock Synchronous Serial Continuous Data Transfer Example (WRITE)
Transfer start
Transfer complete
CS
*1
1
2
7
8
9
10 15 16 17 18 23 24 41 42 47 48
CP
DI/O
Start byte
*1:
Instruction 1
Instruction 2
Instruction 5
Write data in 8 bits. If the CS signal falls when data input operation in 8 bits is not complete, the
last 8-bit data write is invalid.
(The previously written data is valid)
Clock Synchronous Serial Continuous Data Transfer Example (READ)
Transfer start
Transfer complete
CS
*2
1
2
8
9 10 11 15 16 17 18 23 24 41 42 47 48
CP
DI/O
Start byte
Input state
*2:
READ DATA1 READ DATA2
READ DATA5
Output state
A reading state appears only when the R/W bit is “1”. The read data is valid only when the register
is set to key scan read mode and display data read mode. Otherwise, the read data is invalid.
19/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Output pin, I/O Pin and Register States When Reset is Input
Pin and register states while the RESET input is pulled to a “L” level are listed below.
Output pin, I/O pin
State
DI/O
Input state
KREQ
“L” (VSS)
OSC2
Oscillating state
R0 to R4
“L” (VSS)
PBA
High impedance
PB0 to PB7 (for ML9090A-01)
High impedance
SEG1 to SEG80
“L” (VSS)
COM1 to COM10 (for ML9090A-01)
“L” (VSS)
COM1 to COM18 (for ML9090A-02)
“L” (VSS)
Register
State
Key scan register
Reset to “0”
Display data register
Display data is retained
X address register
Reset to “0”
Y address register
Reset to “0”
Port A register
Reset to “0”
Port B register
Reset to “0”
Control register 1
No change from value prior to reset input
Control register 2
Display OFF
Power-On Reset
The capacitance of an external capacitor that is connected to the RESET pin must be CRST [µF] ≥ 12.5 × TR [s],
where TR is rise time until power supply voltage to be supplied to the ML9090A-01/02 reaches 0.8 VDD (V) and
CRST is the capacitance of an external capacitor connected to the RESET pin.
(If TR = 10 [ms], CRST ≥ 0.125 [µF])
The pulse width when an external reset signal is input should be more than TR.
Set an instruction 10 µs after the reset signal is released.
Thereafter, this IC is accessible.
TR
0.9 VDD
VDD
0.1 VDD
Power supply voltage
0.85 VDD
Accessible time
RESET
10 µs or more
20/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Serial Interface Operation
1. Start byte
A register that transfers instruction codes (including display data or key scan data) is selected by a content of the
start byte (see below).
D7
D6
D5
D4
“1”
“1”
RS
R/W
D3
D2
D1
D0
Register number
(1) D7, D6 (fixed at “1”)
When selecting the start byte register, always write a “1” to bits D7 and D6.
(2) D4 (R/W) (Read mode, Write mode select bit)
1: Read mode is selected
0: Write mode is selected
(3) D5, D3 to D0 (Register number)
The correspondence between each content of the start byte and each register or the display data RAM is listed in
the table below.
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
0
0
0
Key scan register
Register name
1
1
1
1/0
0
0
0
1
Display data RAM
1
1
0
0
0
0
1
0
X address register
1
1
0
0
0
0
1
1
Y address register
1
1
0
0
0
1
0
0
Port A register
1
1
0
0
0
1
0
1
Port B register
1
1
0
0
1
0
0
0
Control register1
1
1
0
0
1
0
0
1
Control register 2
21/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Register Descriptions
• Key scan register (KR)
D7
D6
D5
D4
D3
D2
D1
D0
ST2
ST1
ST0
S4
S3
S2
S1
S0
(1) D7 to D5 (ST2 to ST0) (Scan read counter)
When reading 25-bit key scan data, these bits indicate the number of times scan data has been read. Every time key
scan data is read, these bits (ST2 to ST0) are automatically incremented over the range of “000” to “100”. After
counting to “100”, this key scan data read counter is reset to “000”.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
(2) D4 to D0 (S4 to S0) (Key scan read data bits)
These bits are read as 25-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into
5 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to
ST0. S4 to S0 key scan data corresponds to each SWN0 of the key matrix shown in figure 1. The relation between
the key scan data, key matrix signal and each SWN0 of the key matrix is shown below.
If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
ST2
ST1
ST0
S4
S3
S2
S1
S0
0
0
0
SW04
SW03
SW02
SW01
SW00
R0
0
0
1
SW14
SW13
SW12
SW11
SW10
R1
0
1
0
SW24
SW23
SW22
SW21
SW20
R2
0
1
1
SW34
SW33
SW32
SW31
SW30
R3
1
0
0
SW44
SW43
SW42
SW41
SW40
R4
(Note)
SW00 to SW44 swithes are shown in Figure1.
22/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
ML9090A-01, -02
C0
C1
C2
C3
C4
R0
SW00
SW01
SW02
SW03
SW04
SW10
SW11
SW12
SW13
SW14
SW20
SW21
SW22
SW23
SW24
R1
R2
R3
SW30
SW31
SW32
SW33
SW34
SW40
SW41
SW42
SW43
SW44
R4
Figure 1
(Note)
To recognize simultaneous depression of three or more key switches, add a diode in series to
each key.
Cm
Rn
Rn + 1
23/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Key Scan
The key scanning starts when a key switch is pressed on and ends after all key switches are detected to be off. The
KREQ signal changes from the low level “L” to the high level “H” two cycles after key scanning started.
This signal can be used as a flag. To use it as a flag, start key-scan reading when the KREQ signal changes from
“L” to “H”.
In some cases, scanned data may be unstable if key scan reading starts when the level of the KREQ signal changes
from “H” to “L”. To avoid this, repeat the key-scan reading three times.
All key switch inputs are inhibited for about 1.26 cycle after all key switches are detected to be off while the KREQ
signal is at the “H” level.
The KREQ signal is reset when all key switches are detected to be off or when a low-level signal is applied to the
RESET pin.
R0
R1
R2
R3
Key switch input
is invalid.
R4
Key switch ON
Scanning starts
Key data reading
starts.
Key switch OFF
Scanning stops.
Key switch ON
Scanning starts.
KREQ
Note 1:
When three or more key switches are pressed at the same time, the ML9090A-01/02 may
recognize that an unpressed key switch is pressed. Therefore, to recognize simultaneous
depression of three or more key switches, add a diode in series to each key. (See Figure 1.)
To ignore simultaneous depression of three or more key switches, a program may be required
to ignore all key data which contain three or more consecutive “1” values.
24/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
• Display data RAM (DRAM)
D7
D6
D5
D4
D3
D2
D1
D0
8-bit DATA
—
6-bit DATA
The display data register writes and reads display data to and from the liquid crystal display RAM. The contents of
this register are written to or read from the address set by the X address register and Y address register. The bit
length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected, writing to
D7 and D6 is invalid, and if read, their values will always be “0”. D7 is the MSB (D5 in the case of 6-bit data) and
D0 is the LSB.
The X address and Y address should be set immediately before writing or reading display data. However, only
one-time settings of X address and Y address are required immediately before successive writings or readings.
Either X address or Y address may be set first.
Even if the RESET pin is pulled to a “L” level, the contents of this register will not change.
• X address register (XAD)
D7
D6
D5
D4
D3
D2
—
D1
D0
XAD
The X address register sets the X address for the liquid crystal display RAM.
The address setting range is 0 to 9 (00H to 09H) when 8-bit data is selected by the WLS bit. This register starts
counting up from the set value each time RAM is read or written.
When the register count returns to 0 from the maximum value 9, the Y address is automatically incremented.
Thereafter, the Y address is counted in a loop fashion from 0 to 9.
The address setting range is 0 to 13 when 6-bit data is selected.
This register starts counting up from the set value. When the register count returns to 0 from 13, theY address is
automatically incremented.
Thereafter, the Y address loops from 0 to 13.
Proper operation is not guaranteed if values outside this range are set.
Writing to bits D7 through D4 is invalid. If the RESET pin is pulled to a “L” level, these bits are reset to “0”.
• Y address register (YAD)
D7
D6
D5
—
—
D4
D3
D2
D1
D0
YAD (ML9090A-01)
YAD (ML9090A-02)
The YAD register sets a Y address of RAM for the liquid crystal display.
The Y address setting range varies according to the setting of the DTY bits (bits D1 and D0) of the control register
1 (to be described later).
This register starts counting up from the set value each time RAM is read or weitten. When the register count
returns to 0 from the maximum value (7 to 17), the X address is also incremented automatically.
The Y address is counted in a loop fashion as shown below.
25/41
FEDL9090A-01
1Semiconductor
Model
ML9090A-01
ML9090A-02
ML9090A-01, -02
Duty
Y register setting range and loop range
Invalid addres setting range
1/8
0 to 7 (00H to 07H)
8 to 15 (08H to FH)
1/9
0 to 8 (00H to 08H)
9 to 15 (09H to FH)
1/10
0 to 9 (00H to 09H)
10 to 15 (AH to FH)
1/16
0 to 15 (00H to 0FH)
16 to 31 (10H to 1FH)
1/17
0 to 16 (00H to 10H)
17 to 31 (11H to 1FH)
1/18
0 to 17 (00H to 11H)
18 to 31 (12H to 1FH)
When an invalid Y address is set, counting of invalid Y addresses varies according to the selected duty although its
operation is not assured. In case the duty is 1/8 or 1/16, the register counts up to a maximum invalid Y address
value (15 for the ML9090A-01 or 31 for the ML9090A-02) and back to 0. At the same time, the X address is also
incremented.
In case the duty is 1/9 or 1/17, the register counts back to 0 at address “Y address setting plus 1” after an invalid Y
address is set. At the same time, the X address is also incremented.
In case the duty is 1/10 or 1/18, the register counts back to 0 at address “Y address setting plus 1” and at address “Y
address setting plus 1” after an invalid Y address is set. At the same time, the X address is also incremented. After
this, the Y address count loops in a range corresponding to the selected duty.
Both read and write operations on bits D7 to D4 of the ML9090A-01 are invalid.
Both read and write operations on bits D7 to D5 of the ML9090A-02 are invalid.
This register is reset to “0” when the RESET pin is made low.
• Port register A (PTA)
D7
D6
D5
D4
D3
D2
D1
—
D0
PTA
The port register A sets (to “1”) and resets (to “0”) general-purpose port A data. The setting of the PTA bit (D0 bit)
corresponds to the PA0 output pin. If the RESET pin is pulled to a “L” level, this register is reset to “0” and the
PA0 pin goes to high impedance. After the RESET pin is pulled to a “H” level, if port data is set in this register, the
PA0 pin is released from its high impedance state and outputs the corresponding port data.
• Port register B (PTB)
D7
D6
D5
D4
D3
D2
D1
D0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
The port register sets (to “1”) and resets (to “0”) general-purpose port B data. The settings of the PTB0 to PTB7
bits (D0 to D7 bits) correspond to the PTB0 to PTB7 output pins. If the RESET pin is pulled to a “L” level, this
register is reset to “0” and pins PTB0 through PTB7 go to high impedance. After the RESET pin is pulled to a “H”
level, if port data is set in this register, pins PTB0 through PTB7 are released from their high impedance states and
output the corresponding port data.
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
• Control register 1 (FCR1)
D7
D6
D5
D4
D3
D2
D1
D0
INC
WLS
KT
SHL
—
—
DTY1
DTY0
(1) D7 (INC) Address increment direction
1: X direction address increment
0: Y direction address increment
This bit sets the address increment direction of the display RAM. The display RAM address is automatically
incremented by 1 every time data is written to the display data register. Writing a “1” to this bit sets “X address
increment”, and writing a “0” sets “Y address increment”. For further details regarding address incrementing, refer
to the page entitled “X, Y Address Counter Auto Increment”, Even if the RESET pin is pulled to a “L” level, the
value of this bit will not change.
(2) D6 (WLS) (Word Length Select)
1: 6-bit word length select
0: 8-bit word length select
This bit selects the word length of data to be written to and read from the display RAM. If “1” is written to this bit,
data will be read from and written to the display RAM in 6-bit units. If “0” is written to this bit, data will be read
from and written to the display RAM in 8-bit units. Even if the RESET pin is pulled to a “L” level, the value of this
bit will not change.
(3) D5 (KT) (Key scan time) Key scan time select bit
1: 10 ms
0: 5 ms
This bit selects the key scan cycle time. In the case of a 740 kHz oscillating frequency, writing a “1” to this bit sets
the key scan cycle time at 10 ms, writing a “0” sets the key scan cycle time at 5 ms. Even if the RESET pin is
pulled to a “L” level, the value of this bit will not change.
(4) D4 (SHL) (Common driver shift direction select bit)
This bit selects the shift direction of common drivers.
The relationship between this bit and shift directions are shown below.
Even if the RESET Pin is set to “L”, this bit remains unchanged.
Model
SHL
Duty
1/8
1
ML9090A-01
0
1
ML9090A-02
0
Shift direction
COM8
→
COM1
1/9
COM9
→
COM1
1/10
COM10
→
COM1
1/8
COM1
→
COM8
1/9
COM1
→
COM9
1/10
COM1
→
COM10
1/16
COM16
→
COM1
1/17
COM17
→
COM1
1/18
COM18
→
COM1
1/16
COM1
→
COM16
1/17
COM1
→
COM17
1/18
COM1
→
COM18
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
(5) D1, D0 (DTY1, DTY0) (Display duty select bit)
This bit selects the display duty. The correspondence between each bit and display duty is shown in the chart below.
Even if the RESET pin is pulled to a “L” Level, the values of these bits will not change.
Model
ML9090A-01
ML9090A-02
Code
DTY1
DTY0
Display duty
0
0
0
1/8
1
0
1
1/9
2
1
0
1/10
3
1
1
1/10
0
0
0
1/16
1
0
1
1/17
2
1
0
1/18
3
1
1
1/18
• Control register 2 (FCR2)
D7
D6
—
D5
D4
D3
D2
D1
D0
T4
T3
T2
T1
—
DISP
(1) D2 to D5 (T1 to T4) (Test mode select bit)
These bits are used to test the IC. “0” must be written to these bits.
(2) D0 (DISP) (Display ON/OFF mode bit)
1: Display ON mode
0: Display OFF mode
This bit selects whether the display is ON or OFF. Writing a “1” to this bit selects the display ON mode. Writing a
“0” to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even if
this bit is set to “0”, the display RAM contents will not change. If the RESET pin is pulled to a “L” level, this
register is reset to “0”.
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FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Display Screen and Memory Address Allocation
The ML9090A-01/02 contains display data RAM (80 bits by 18 bits) of a bitmap type.
The allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in
Figure 2: 0 to 9 for selection of 8 bits per word or 0 to 13 for selection of 6 bits per word.
The X address 13 in the 6-bits/word mode has two display memory bits. The two bits (D5 and D4) starting from bit
D5 of the display data register are written in memory and the other bits (D3 to D0) are ignored.
Address Allocation in the 8-bits/word mode
Address Allocation in the 6-bits/word mode
0
1
(X address)
2
9
0
(Y address)
(Y address)
(X address)
0
1 (D7)
(D0)
1
2
13
0
(D5)
(D4)
1 (D5)
(D0)
(8 bits)
(2 bits)
(6 bits)
17
17
Figure 2 Display Memory Addresses
(COM1)
Y0
(COM2)
Y1
(COM18)
Y17
(SEG1)
(SEG2)
(SEG3)
(SEG4)
(SEG5)
(SEG6)
(SEG7)
(SEG8)
(SEG80)
X2
X3
X4
X5
X6
X7
X79
X address
X1
Common
output
X0
X address
Segment
output
In the 8-bits/word mode, data to be displayed is written in display memory with the D7 data of the display data
register at address (Xn, Yn) and the D0 data at address (Xn + 7, Yn). Similarly, In the 6-bits/word mode, data to be
displayed is written in display memory with the D5 data of the display data register at address (Xn, Yn) and the D0
data at address (Xn + 5, Yn). See Figure 3.
Data “1” in display memory represents turning on the corresponding display segment and data “0” in display
memory represents turning off the corresponding display segment.
1
0
1
0
1
0
1
0
1
(D7)
(D5)
(D0) For 8 bits per word
(D0) For 6 bits per word
RAM for 80 dots by 18 dots display
Figure 3 Display Screen Bit Allocation and Memory Addresses
29/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
X•Y address Counter Auto Increment
The liquid crystal display RAM for the ML9090A-01/02 has an X-address counter and a Y-address counter. Each
address counter has an Auto Increment function.
When display data is read or written, this function increments either of these X- and Y-address counters (which is
selected by the INC bit (D7 bit) of the control register 1).
INC bit = “0” selects the Y-address counter.
INC bit = “1” selects the X-address counter.
The address counting cycle of the X address counter varies according to the selected word length (8 bits or 6 bits) :
X address range of 0 to 9 in the 8-bits/word mode or X address range of 0 to 13 in the 6-bits/word mode.
When the X address count returns to 0 from a maximum value (9 in the 8-bits/word mode or 13 in the 6-bits/word
mode), the Y address is also incremented automatically.
The relationship between display duties and Y address count ranges is shown below.
When the Y-address counter returns to 0 from a maximum value, the X address is also incremented automatically.
Model
ML9090A-01
ML9090A-02
Y-address count range (cycle)
Maximum Y address count
1/8
0 to 7
7
1/9
0 to 8
8
1/10
0 to 9
9
1/16
0 to 5
15
1/17
0 to 16
16
1/18
0 to 17
17
If an invalid address (outside the address count range) is given to the X- or Y- address counter,
its counting will not be assured.
Example of incrementing the X-address
(8 bits per word and 1/18 duty)
Example of incrementing the Y-address
(8 bits per word and 1/18 duty)
0
0
1
X address
2
9
1
Y address
1
X address
1
0
9
0
Y address
Note:
Duty
2
17
17
30/41
FEDL9090A-01
*Please view this page at 150% magnification.
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (1)
1/8 duty (1/4 bias) (ML9090A-01)
8 1
2
3 4
5
6
7
8
1 2
3
4
5
6 7
8
1
2
Common
line No.
3
VS2
V1
C0M1
V2, V3A, V3B
V4
VSS
VS2
V1
C0M2
V2, V3A, V3B
V4
VSS
VS2
V1
C0M8
V2, V3A, V3B
V4
VSS
A non-selectable waveform is output from COM9 and COM10 outputs.
8 1
2 3
4
5
6
7 8
1
2 3
4
5 6
7
8 1
Common
line No.
2 3
VS2
V1
V2, V3A, V3B
SEGn
V4
VSS
: Light ON
: Light OFF
31/41
*Please view this page at 150% magnification.
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (2)
1/9 duty (1/4 bias) (ML9090A-01)
9
1 2
3 4 5
6
7 8
9
1 2
3
4 5
6
7 8
9
Common
line No.
1
VS2
V1
C0M1
V2, V3A, V3B
V4
VSS
VS2
V1
V2, V3A, V3B
C0M2
V4
VSS
VS2
V1
C0M9
V2, V3A, V3B
V4
VSS
A non-selectable waveform is output from the COM10 output.
9 1 2
3
4 5
6 7 8
9
1 2
3
4 5
6
7 8
9
Common
line No.
1
VS2
V1
SEGn
V2, V3A, V3B
V4
VSS
: Light ON
: Light OFF
32/41
FEDL9090A-01
*Please view this page at 150% magnification.
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (3)
1/10 duty (1/4 bias) (ML9090A-01)
10 1
2
3
4
5 6
7
8 9 10 1 2
3
4
5 6 7
Common
line No.
8 9 10
VS2
V1
V2, V3A, V3B
C0M1
V4
VSS
VS2
V1
V2, V3A, V3B
C0M2
V4
VSS
VS2
V1
C0M10
V2, V3A, V3B
V4
VSS
10 1
2
3
4 5
6
7 8
9 10 1
2
3 4
5
6 7
8
Common
line No.
9 10
VS2
V1
V2, V3A, V3B
SEGn
V4
VSS
: Light ON
: Light OFF
33/41
FEDL9090A-01
*Please view this page at 150% magnification.
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (4)
1/16 duty (1/5 bias) (ML9090A-02)
Common
line No.
15 16 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
VS2
V1
C0M1
V2
V3A, V3B
V4
VSS
VS2
V1
C0M2
V2
V3A, V3B
V4
VSS
VS2
V1
C0M16
V2
V3A, V3B
V4
VSS
A non-selectable waveform is output from COM17 and COM18 outputs.
Common
line No.
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 1 2 3 4 5
VS2
V1
SEGn
V2
V3A, V3B
V4
VSS
: Light ON
: Light OFF
34/41
FEDL9090A-01
*Please view this page at 150% magnification.
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (5)
1/17 duty (1/5 bias) (ML9090A-02)
Common
line No.
16 17 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 1 2 3 4 5 6 7 8 9 1011 1213 14 1516 17 1 2 3 4 5
VS2
V1
C0M1
V2
V3A, V3B
V4
VSS
VS2
V1
V2
V3A, V3B
V4
VSS
C0M2
VS2
V1
V2
V3A, V3B
C0M17
V4
VSS
A non-selectable waveform is output form the COM18 output.
Common
line No.
16 17 1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 1 2 3 4 5
VS2
V1
SEGn
V2
V3A, V3B
V4
VSS
: Light ON
: Light OFF
35/41
FEDL9090A-01
*Please view this page at 150% magnification.
1Semiconductor
ML9090A-01, -02
Liquid Crystal Driving Waveform Example (6)
1/18 duty (1/5 bias) (ML9090A-02)
1718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5
VS2
V1
V2
V3A, V3B
V4
VSS
C0M1
VS2
V1
V2
V3A, V3B
V4
VSS
C0M2
VS2
V1
V2
V3A, V3B
V4
VSS
C0M18
17 18 1 2 3 4 5 6 7 8 9 1011121314 15161718 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5
SEGn
Common
line No.
Common
line No.
VS2
V1
V2
V3A, V3B
V4
VSS
: Light ON
: Light OFF
36/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Power-On Flowchart
Start
VDD turned on
VIN turned on
Reset signal is input
External reset or power-on reset
Control register 1 setting
INC, WLS, KT, SHL, DTY1, DTY0 settings
Display Data RAM settings
Port register A, port register B, display data
RAM settings according to specifications.
No
Is input of initial
screen data
complete ?
Yes
Set DISP of control register
2 to “1”
Start displaying initial screen
Setting complete
Power-Off Flowchart
LCD driving state
VIN turned off
VDD turned off
[Cautions]
• When the power supply is ON or OFF, the following power supply sequence should be used.
At the time of power supply ON:
Logic power supply ON → multiplied reference supply voltage (VIN) ON
At the time of power supply OFF:
Multiplied reference supply voltage (VIN) OFF → logic power supply OFF or both OFF
• The lines between output pins, and between output pins and other pins (input pins, I/O pins or power supply
pins), should not be short circuited.
37/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
APPLICATION CIRCUIT
Application Example 1 (1/10 duty, 1/4 bias, voltage doubler)
LCD panel
80 × 10 dots
graphic
VCC
Temperature
compensating
and
stabilizing
circuits
COM1–COM10
4.7 µF
+
VIN
VDD
VC1
DT
VSS
VC2
VS1
+
4.7 µF
VDD = 5 V
SEG1–SEG80
PA0
VS2
OSC1
ML9090A-01
V2
OPEN
56 kΩ
OSC2
TEST
V3B
RESET
V3A
CPU
PORT
OR
SERIAL PORT
CS
R4
CP
R3
DI/O
R2
R1
KREQ
PB0–PB7
General-purpose
ports
1 µF
C0 C1 C2 C3 C4
R0
5×5
Key
Matrix
38/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
Application Example 2 (1/18 duty, 1/5 bias, voltage tripler)
LCD panel
80 × 18 dots
graphic
VCC
Temperature
compensating
and
stabilizing
circuits
4.7 µF
4.7 µF
COM1–COM18
4.7 µF
SEG1–SEG80
VIN
VDD
VC1
DT
+
VC2
+
VS1
VSS
PA0
+
OPEN
VS2
OSC1
ML9090A-02
V2
56 kΩ
OSC2
TEST
V3B
RESET
V3A
CPU
PORT
OR
SERIAL PORT
VDD = 5 V
CS
R4
CP
R3
DI/O
R2
1 µF
R1
KREQ
C0 C1 C2 C3 C4
R0
5×5
Key
Matrix
39/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.19 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
40/41
FEDL9090A-01
1Semiconductor
ML9090A-01, -02
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
41/41
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