Fairchild MM74C08N Quad 2-input and gate Datasheet

Revised January 2004
MM74C08
Quad 2-Input AND Gate
General Description
Features
The MM74C08 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin, these
gates provide basic functions used in the implementation of
digital integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to VCC and GND.
■ Wide supply voltage range:
3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 VCC (typ.)
■ Low power TTL compatibility:
Fan out of 2 driving 74L
■ Low power consumption: 10 nW/package (typ.)
Ordering Code:
Order Number
MM74CD8N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Truth Table
Inputs
Outputs
A
B
L
L
Y
L
L
H
L
H
L
L
H
H
H
H = HIGH Level
L = LOW Level
Top View
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DS005878
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MM74C08 Quad 2-Input AND Gate
October 1987
MM74C08
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
−0.3V to VCC + 0.3V
Operating Temperature Range
−55°C to +125°C
Storage Temperature Range
−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line
700 mW
Small Outline
500 mW
Operating VCC Range
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
3.0V to 15V
Absolute Maximum VCC
18V
Lead Temperature
260°C
(Soldering, 10 seconds)
DC Electrical Characteristics
Min/Max limits apply across the guaranteed temperature range, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
VCC = 5.0V
3.5
VCC = 10V
8.0
V
VCC = 5.0V
1.5
VCC = 10V
2.0
VCC = 5.0V, IO = −10 µA
4.5
VCC = 10V, IO = −10 µA
9.0
V
VCC = 5.0V, IO = 10 µA
0.5
VCC = 10V, IO = 10 µA
1.0
IIN(1)
Logical “1” Input Current
VCC = 15V, VIN = 15V
IIN(0)
Logical “0” Input Current
VCC = 15V, VIN = 0V
ICC
Supply Current
VCC = 15V
0.005
−1.0
V
1.0
−0.005
0.01
V
µA
µA
15
µA
0.8
V
CMOS/LPTTL INTERFACE
VIN(1)
Logical “1” Input Voltage
74C, VCC = 4.75V
VIN(0)
Logical “0” Input Voltage
74C, VCC = 4.75V
VOUT(1)
Logical “1” Output Voltage
74C, VCC = 4.75V, IO = −360 µA
VOUT(0)
Logical “0” Output Voltage
74C, VCC = 4.75V, IO = 360 µA
VCC − 1.5
V
2.4
V
0.4
V
OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)
ISOURCE
Output Source Current
VCC = 5.0V, VOUT = 0V
−1.75
−3.3
mA
VCC = 10V, VOUT = 0V
−8.0
15
mA
VCC = 5.0V, VOUT = VCC
1.75
3.6
mA
VCC = 10V, VOUT = V CC
8.0
16
mA
(P-Channel)
ISOURCE
Output Source Current
(P-Channel)
ISINK
Output Sink Current
(N-Channel)
ISINK
Output Sink Current
(N-Channel)
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(Note 2)
(MM74C08) TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Typ
Max
Propagation Delay Time to
VCC = 5.0V
80
140
Logical “1” or “0”
VCC = 10V
40
70
CIN
Input Capacitance
(Note 3)
5.0
pF
CPD
Power Dissipation Capacitance
(Note 4) Per Gate
14
pF
tpd0, tpd1
Parameter
Conditions
Min
Units
ns
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
AN-90.
Typical Performance Characteristics
Propagation Delay Time vs
Load Capacitance
MMM74C08
AC Test Circuit
Note: Delays measured with input t r, tf = 20 ns
Switching Time Waveforms
3
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MM74C08
AC Electrical Characteristics
MM74C08 Quad 2-Input AND Gate
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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