Revised January 1999 MM74C175 Quad D-Type Flip-Flop General Description The MM74C175 consists of four positive-edge triggered Dtype flip-flops implemented with monolithic CMOS technology. Both are true and complemented outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Information at the D-type inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical “0” and Q's to logical “1”. All inputs are protected from static discharge by diode clamps to VCC and GND. Features ■ Wide supply voltage range: 3V to 15V ■ Guaranteed noise margin: ■ High noise immunity: 1.0V 0.45 VCC (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L Ordering Code: Order Number Package Number Package Description MM74C175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Truth Table Each Flip-Flop Pin Assignments for DIP and SOIC Inputs Outputs Clear Clock D Q Q L X X L H H ↑ H H L H ↑ L L H H H X NC NC H L X NC NC H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transition from LOW-to-HIGH level NC = No Change Top View © 1999 Fairchild Semiconductor Corporation DS005900.prf www.fairchildsemi.com MM74C175 Quad D-Type Flip-Flop October 1987 MM74C175 Block Diagrams Typical One of Four www.fairchildsemi.com 2 Absolute Maximum VCC −0.3V to VCC +0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C 700 mW Small Outline 500 mW Operating VCC Range 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 18V Lead Temperature 3V to 15V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V, IO = −10 µA 4.5 V VCC = 10V, IO = −10 µA 9.0 V VCC = 5V, IO = 10 µA 0.5 V VCC = 10V, IO = 10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.05 µA 300 µA 0.8 V 0.4 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage 74C, VCC = 4.75V VIN(0) Logical “0” Input Voltage 74C, VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage 74C, VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage 74C, VCC = 4.75V, IO = 360 µA V 2.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5V, TA = 25°C, (P-Channel) VOUT = 0V Output Source Current VCC = 10V, TA = 25°C, (P-Channel) VOUT = 0V Output Sink Current VCC = 5V, TA = 25°C, (N-Channel) VOUT = VCC Output Sink Current VCC = 10V, TA = 25°C, (N-Channel) VOUT = VCC 3 −1.75 −3.3 mA −8.0 −15 mA 1.75 3.6 mA 8.0 16 mA www.fairchildsemi.com MM74C175 Absolute Maximum Ratings(Note 1) MM74C175 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd Typ Max Propagation Delay Time to Parameter VCC = 5V Conditions Min 190 300 Units ns a Logical “0” or Logical “1” from VCC = 10V 75 110 ns Propagation Delay Time to a VCC = 5V 180 300 ns Logical “0” from Clear to Q VCC = 10V 70 110 ns Propagation Delay Time to a VCC = 5V 230 400 ns Logical “1” from Clear to Q VCC = 10V 90 150 ns Clock to Q or Q tpd tpd tS tH tW tW tr Time Prior to Clock Pulse that VCC = 5V 100 45 ns Data Must be Present VCC = 10V 40 16 ns Time After Clock Pulse that VCC = 5V 0 −11 ns Data Must be Held VCC = 10V 0 −4 ns Minimum Clock Pulse Width VCC = 5.0V 130 250 ns VCC = 10V 45 100 ns VCC = 5.0V 120 250 ns VCC = 10V 45 100 ns Minimum Clear Pulse Width Maximum Clock Rise Time tf Maximum Clock Fall Time fMAX Maximum Clock Frequency CIN Input Capacitance CPD Power Dissipation Capacitance VCC = 5V 15 450 µs VCC = 10V 5.0 125 µs VCC = 5V 15 50 µs VCC = 10V 5.0 50 µs VCC = 5V 2.0 3.5 MHz VCC = 10V 5.0 10 MHz Clear Input (Note 3) 10 pF Any Other Input 5.0 pF Per Package (Note 4) 130 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Switching Time Waveforms CMOS to CMOS www.fairchildsemi.com 4 MM74C175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 5 www.fairchildsemi.com MM74C175 Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.