Fairchild MM74HC154WM 4-to-16 line decoder Datasheet

Revised July 2003
MM74HC154
4-to-16 Line Decoder
General Description
The MM74HC154 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses high
noise immunity, and low power consumption of CMOS with
speeds similar to low power Schottky TTL circuits.
The MM74HC154 have 4 binary select inputs (A, B, C, and
D). If the device is enabled these inputs determine which
one of the 16 normally HIGH outputs will go LOW. Two
active LOW enables (G1 and G2) are provided to ease
cascading of decoders with little or no external logic.
Each output can drive 10 low power Schottky TTL equivalent loads, and is functionally and pin equivalent to the
74LS154. All inputs are protected from damage due to
static discharge by diodes to VCC and ground.
Features
■ Typical propagation delay: 21 ns
■ Power supply quiescent current: 80 µA
■ Wide power supply voltage range: 2–6V
■ Low input current: 1 µA maximum
Ordering Code:
Order Number
Package Number
MM74HC154WM
M24B
MM74HC154MTC
MTC24
MM74HC154N
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
Pin Assignments for DIP, SOIC and TSSOP
G1 G2
Top View
Low
D
C
B
A
Output
(Note 1)
L
L
L
L
L
L
0
L
L
L
L
L
H
1
L
L
L
L
H
L
2
L
L
L
L
H
H
3
L
L
L
H
L
L
4
L
L
L
H
L
H
5
L
L
L
H
H
L
6
L
L
L
H
H
H
7
L
L
H
L
L
L
8
L
L
H
L
L
H
9
L
L
H
L
H
L
10
L
L
H
L
H
H
11
L
L
H
H
L
L
12
L
L
H
H
L
H
13
L
L
H
H
H
L
14
L
L
H
H
H
H
15
L
H
X
X
X
X
—
H
L
X
X
X
X
—
H
H
X
X
X
X
—
Note 1: All others HIGH
© 2003 Fairchild Semiconductor Corporation
DS005122
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MM74HC154 4-to-16 Line Decoder
September 1983
MM74HC154
Logic Diagram
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2
Recommended Operating
Conditions
(Note 3)
Supply Voltage (VCC)
−0.5 to +7.0V
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
Power Dissipation (PD)
600 mW
S.O. Package only
500 mW
VIL
VOH
−40 +85
°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Note 4: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics
VIH
V
Note 3: Unless otherwise specified all voltages are referenced to ground.
(Soldering 10 seconds)
Parameter
V
VCC
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
Symbol
6
0
Input Rise or Fall Times
−65°C to +150°C
(Note 4)
2
DC Input or Output Voltage (VIN, VOUT)
Operating Temperature Range (TA)
±50 mA
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Min Max Units
Supply Voltage (VCC)
(Note 5)
VCC
Conditions
TA = 25°C
Typ
TA = −40 to 85°C
Guaranteed Limits
Minimum HIGH
2.0V
1.5
1.5
Level Input
4.5V
3.15
3.15
Voltage
6.0V
4.2
4.2
Maximum LOW
2.0V
0.5
0.5
Level Input
4.5V
1.35
1.35
Voltage
6.0V
1.8
1.8
Minimum HIGH
VIN = VIH or VIL
Level Output
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
4.5V
4.5
4.4
4.4
6.0V
6.0
5.9
5.9
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
Voltage
Units
V
V
V
VIN = VIH or VIL
VOL
Maximum LOW
VIN = VIH or VIL
Level Output
|IOUT| ≤ 20 µA
V
2.0V
0
0.1
0.1
4.5V
0
0.1
0.1
6.0V
0
0.1
0.1
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
VIN = VCC or GND
6.0V
±0.1
±1.0
µA
Maximum
VIN = VCC or GND
6.0V
8.0
80
µA
Quiescent
IOUT = 0 µA
Voltage
V
VIN = VIH or VIL
IIN
Maximum
V
Input Current
ICC
Supply Current
Note 5: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC154
Absolute Maximum Ratings(Note 2)
MM74HC154
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
tPHL, tPLH
Conditions
Maximum Propagation Delay, G1 , G2 or A, B, C, D
Typ
Guaranteed Limit
Units
21
32
ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
VCC
TA = −40 to 85°C
Parameter
tPHL, tPLH
Maximum Propagation
2.0V
63
160
190
Delay, G1 or G2
4.5V
24
36
42
or A, B, C, D
6.0V
20
30
35
Maximum Output
2.0V
25
75
95
Rise and Fall Time
4.5V
7
15
19
6.0V
6
13
16
tTLH, tTHL
CPD
Conditions
TA = 25°C
Symbol
Power Dissipation
Guaranteed Limits
90
Capacitance (Note 6)
CIN
Typ
Maximum Input
5
Capacitance
4
ns
ns
pF
10
10
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD V CC f + ICC.
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Units
pF
MM74HC154
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
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MM74HC154
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
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6
MM74HC154 4-to-16 Line Decoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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