Fairchild MM74HC164 8-bit serial-in/parallel-out shift register Datasheet

Revised January 2005
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
Features
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
■ Typical operating frequency: 50 MHz
This 8-bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock
pulse. A high level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meeting the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock
and accomplished by a low level at the CLEAR input.
■ Typical propagation delay: 19 ns (clock to Q)
■ Wide operating supply voltage range: 2V to 6V
■ Low input current: 1 µA maximum
■ Low quiescent supply current: 80 µA maximum
(74HC Series)
■ Fanout of 10 LS-TTL loads
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Ordering Code:
Order Number
Package
Package Description
Number
MM74HC164M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC164MX_NL
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC164MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC164MTCX_NL
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC164N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS005315
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MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
September 1983
MM74HC164
Connection Diagram
Top View
Truth Table
Inputs
Clear Clock
Outputs
A
B
QA
QB
...
QH
L
X
X
X
L
L
L
H
L
X
X
QAO
QBO
QHO
H
↑
H
H
H
QAn
QGn
H
↑
L
X
L
QAn
QGn
H
↑
X
L
L
QAn
QGn
H = HIGH Level (steady state), L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW-to-HIGH level.
QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent ↑ transition of the
clock; indicated a one-bit shift.
Logic Diagram
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2
Recommended Operating
Conditions
(Note 2)
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
Storage Temperature Range (TSTG)
Max
Units
2
6
V
0
VCC
V
−40
+85
°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
±50 mA
DC VCC or GND Current, per pin (ICC)
Min
Supply Voltage (VCC)
Input Rise or Fall Times
−65°C to +150°C
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
(Soldering 10 seconds)
Conditions
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
(Note 4)
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Minimum HIGH Level
2.0V
1.5
1.5
1.5
Input Voltage
4.5V
3.15
3.15
3.15
6.0V
4.2
4.2
4.2
Maximum LOW Level
2.0V
0.5
0.5
0.5
Input Voltage
4.5V
1.35
1.35
1.35
6.0V
1.8
1.8
1.8
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
4.5V
4.5
4.4
4.4
4.4
6.0V
6.0
5.9
5.9
5.9
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
Units
V
V
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
4.5V
0
0.1
0.1
0.1
6.0V
0
0.1
0.1
0.1
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
0.4
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum Quiescent
VIN = VCC or GND
6.0V
8.0
80
160
µA
Supply Current
IOUT = 0 µA
V
VIN = VIH or VIL
IIN
Maximum Input
Current
ICC
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC164
Absolute Maximum Ratings(Note 1)
MM74HC164
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
fMAX
Maximum Operating Frequency
tPHL, tPLH
Maximum Propagation Delay
Conditions
Guaranteed
Typ
Units
Limit
30
MHz
19
30
ns
23
35
ns
−2
0
ns
12
20
ns
1
5
ns
10
16
ns
Clock to Output
tPHL
Maximum Propagation Delay
Clear to Output
tREM
Minimum Removal Time,
Clear to Clock
tS
Minimum Setup Time
Data to Clock
tH
Minimum Hold Time
Clock to Data
tW
Minimum Pulse Width
Clear or Clock
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
fMAX
Parameter
Conditions
Maximum Operating Frequency
tPHL, tPLH Maximum Propagation Delay
tREM
tS
tH
tW
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
2.0V
5
4
3
4.5V
27
21
18
6.0V
31
24
20
254
115
175
218
4.5V
13
35
44
51
6.0V
20
30
38
44
Maximum Propagation Delay
2.0V
140
205
256
297
Clear to Output
4.5V
28
41
51
59
6.0V
24
35
44
51
Minimum Removal Time
2.0V
−7
0
0
0
Clear to Clock
4.5V
−3
0
0
0
6.0V
−2
0
0
0
Minimum Setup Time
2.0V
25
100
125
150
Data to Clock
4.5V
14
20
25
30
6.0V
12
17
21
25
Minimum Hold Time
2.0V
−2
5
5
5
Clock to Data
4.5V
0
5
5
5
6.0V
1
5
5
5
Minimum Pulse Width
2.0V
22
80
100
120
Clear or Clock
4.5V
11
16
20
24
6.0V
10
14
18
20
110
tTHL, tTLH Maximum Output
2.0V
75
95
4.5V
15
19
22
6.0V
13
16
19
Maximum Input
2.0V
1000
1000
1000
Rise and Fall Time
4.5V
500
500
500
6.0V
400
400
400
Rise and Fall Time
tr, tf
TA = 25°C
Typ
2.0V
Clock to Output
tPHL
VCC
CPD
Power Dissipation Capacitance
(Note 5)
CIN
Maximum Input Capacitance
(per package)
5.0V
150
5
4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
10
10
10
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
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Units
pF
MM74HC164
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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MM74HC164
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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