Fairchild MM74HC259MTC 8-bit addressable latch/3-to-8 line decoder Datasheet

Revised February 1999
MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
The MM74HC259 device utilizes advanced silicon-gate
CMOS technology to implement an 8-bit addressable latch,
designed for general purpose storage applications in digital
systems.
The MM74HC259 has a single data input (D), 8 latch outputs (Q1–Q8), 3 address inputs (A, B, and C), a common
enable input (G), and a common CLEAR input. To operate
this device as an addressable latch, data is held on the D
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transitions from LOW-to-HIGH. All unaddressed latches will
remain unaffected. With enable in the HIGH state the
device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous
data into the latches, the enable should be held HIGH
(inactive) while the address lines are changing.
If enable is held HIGH and CLEAR is taken LOW all eight
latches are cleared to a LOW state. If enable is LOW all
latches except the addressed latch will be cleared. The
addressed latch will instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
■ Typical propagation delay: 18 ns
■ Wide supply range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC Series)
Ordering Code:
Order Number
Package Number Package Description
MM74HC259M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC259SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC259MTC
MM74HC259N
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Latch Selection Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Latch
B
A
Addressed
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
H = HIGH level, L = LOW level
D = the level at the data input
Qi0 the level of Qi (i = 0, 1 .. .7, as appropriate)
before the indicated steady-state input
conditions were established.
Top View
© 1999 Fairchild Semiconductor Corporation
Select Inputs
C
DS005006.prf
www.fairchildsemi.com
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
September 1983
MM74HC259
Truth Table
Inputs
Clear
G
Outputs of
Each
Addressed
Other
Latch
Output
Addressable Latch
H
L
D
Qi0
H
H
Qi0
Qi0
Memory
L
L
D
L
8-Line Decoder
L
H
L
L
Clear
Logic Diagram
www.fairchildsemi.com
Function
2
Recommended Operating
Conditions
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC+1.5V
DC Output Voltage (VOUT)
−0.5 to VCC+0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
DC VCC or GND Current, per pin (ICC)
±50 mA
Storage Temperature Range (TSTG)
Min
Max
Supply Voltage (VCC)
2
6
V
DC Input or Output Voltage
0
VCC
V
−40
+85
°C
(VIN, VOUT)
Operating Temperature Range (TA)
Input Rise or Fall Times
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Symbol
VIH
VIL
VOH
Parameter
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
DC Electrical Characteristics
Conditions
Units
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C
(Note 4)
TA= 25°C
VCC
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
V
VIN = VIH or VIL
IIN
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
0.4
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum Quiescent
VIN = VCC or GND
6.0V
8.0
80
160
µA
Supply Current
IOUT = 0 µA
Maximum Input
Current
ICC
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
www.fairchildsemi.com
MM74HC259
Absolute Maximum Ratings(Note 1)
(Note 2)
MM74HC259
AC Electrical Characteristics
(VCC = 5.0V, TA = 25°C, tr = tf = 6 ns, CL = 15 pF unless otherwise specified.)
Symbol
tPHL, tPLH
Parameter
Conditions
Typ
Maximum Propagation Delay
Guaranteed
Limit
Units
18
32
ns
20
38
ns
20
35
ns
17
27
ns
ns
Data to Output
tPHL, tPLH
Maximum Propagation Delay
Select to Output
tPHL, tPLH
Maximum Propagation Delay
Enable to Output
tPHL
Maximum Propagation Delay
Clear to Output
tW
Minimum Enable Pulse Width
10
16
tW
Minimum Clear Pulse Width
10
16
ns
tr, tf
Maximum Input Rise and Fall Time
500
ns
ts
Minimum Setup Time Select or
15
20
ns
−2
0
ns
Data to Enable
tH
Minimum Hold Time Data or
Address to Enable
AC Electrical Characteristics
tr = tf = 6 ns, CL = 50 pF, VCC = 2.0V – 6.0V
Symbol
Parameter
Conditions
tPHL, tPLH Maximum Propagation Delay
Data to Output
tPHL, tPLH Maximum Propagation Delay
Select to Output
TA = 25°C
VCC
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
2.0V
60
180
225
250
ns
4.5V
19
37
46
52
ns
6.0V
17
32
40
45
ns
2.0V
72
220
275
310
ns
4.5V
21
43
54
60
ns
ns
6.0V
18
37
46
52
tPHL, tPLH Maximum Propagation Delay
2.0V
65
200
250
280
ns
Enable to Output
4.5V
27
40
50
58
ns
tPHL
tW
ts
6.0V
23
35
44
50
ns
Maximum Propagation Delay
2.0V
50
150
190
210
ns
Clear to Output
4.5V
18
31
39
44
ns
6.0V
16
26
32
37
ns
Minimum Pulse Width
2.0V
80
100
120
ns
Clear or Enable
4.5V
16
20
24
ns
ns
6.0V
14
18
20
Minimum Setup Time Address
2.0V
100
125
150
ns
or Data to Enable
4.5V
20
25
28
ns
15
19
25
ns
Minimum Hold Time Address
2.0V
−10
0
0
0
ns
or Data to Enable
4.5V
−2
0
0
0
ns
6.0V
−2
0
0
0
ns
2.0V
30
75
95
110
ns
4.5V
8
15
19
22
ns
6.0V
7
13
16
19
ns
5
10
10
10
pF
6.0V
tH
tTLH, tTHL Maximum Output Rise
and Fall Time
CIN
Input Capacitance
CPD
Power Dissipation
(per package)
80
Capacitance (Note 5)
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPDs V CCsf + ICC.
www.fairchildsemi.com
4
pF
MM74HC259
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
www.fairchildsemi.com
MM74HC259
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
www.fairchildsemi.com
6
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
www.fairchildsemi.com
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Similar pages