Fairchild MM74HC32 Quad 2-input or gate Datasheet

Revised February 1999
MM74HC32
Quad 2-Input OR Gate
General Description
The MM74HC32 OR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
■ Typical propagation delay: 10 ns
■ Wide power supply range: 2–6V
■ Low quiescent current: 20 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
Package Number
MM74HC32M
MM74HC32SJ
MM74HC32MTC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14
MM74HC32N
Package Description
M14A
N14A
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
Y=A+B
(1 of 4)
© 1999 Fairchild Semiconductor Corporation
DS005132.prf
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MM74HC32 Quad 2-Input OR Gate
September 1983
MM74HC32
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
−0.5 to + 7.0V
Supply Voltage (VCC)
−1.5 to VCC + 1.5V Supply Voltage (V )
CC
−0.5 to VCC + 0.5V DC Input or Output Voltage
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
±20 mA
(VIN, VOUT )
±25 mA Operating Temperature Range (T )
A
±50 mA Input Rise or Fall Times
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IOUT)
DC VCC or GND Current, per pin
(ICC)
Storage Temperature Range (TSTG)
−65°C to +150°C
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Symbol
VIH
VIL
VOH
Parameter
6
Units
V
0
VCC
V
−40
+85
°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
DC Electrical Characteristics
Max
2
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Min
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
(Note 4)
VCC
Conditions
TA = 25°C
Typ
TA = −40 to 85°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
V
6.0V
4.2
4.2
V
Maximum LOW Level
2.0V
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
V
6.0V
1.8
1.8
V
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT | ≤ 20 µA
2.0V
2.0
1.9
1.9
V
4.5V
4.5
4.4
4.4
V
6.0V
6.0
5.9
5.9
V
| IOUT | ≤ 4.0 mA
4.5V
4.7
3.98
3.84
V
| IOUT | ≤ 5.2 mA
6.0V
5.2
5.48
5.34
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIL
Output Voltage
|IOUT | ≤ 20 µA
2.0V
0
0.1
0.1
V
4.5V
0
0.1
0.1
V
6.0V
0
0.1
0.1
V
| IOUT | ≤ 4.0 mA
4.5V
0.2
0.26
0.33
V
| IOUT | ≤ 5.2 mA
6.0V
0.2
0.26
0.33
V
VIN = VCC or GND
6.0V
±0.1
±1.0
µA
Maximum Quiescent
VIN = VCC or GND
6.0V
2.0
20
µA
Supply Current
IOUT = 0 µA
VIN = VIL
IIN
Maximum Input
Current
ICC
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
tPHL, tPLH
Parameter
Conditions
Guaranteed
Typ
Maximum Propagation
Limit
10
18
Units
ns
Delay
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA = 25°C
Typ
tPHL, tPLH
tTLH, tTHL
Units
Maximum Propagation
2.0V
30
100
125
ns
Delay
4.5V
12
20
25
ns
ns
6.0V
9
17
21
Maximum Output Rise
2.0V
30
75
95
ns
and Fall Time
4.5V
8
15
19
ns
7
13
16
6.0V
CPD
TA = −40 to 85°C
Guaranteed Limits
Power Dissipation
(per gate)
50
ns
pF
Capacitance (Note 5)
CIN
Maximum Input
5
10
10
pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
3
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MM74HC32
AC Electrical Characteristics
MM74HC32
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
MM74HC32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5
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MM74HC32 Quad 2-Input OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
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device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
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