Fairchild MM74HC373MTC 3-state octal d-type latch Datasheet

Revised February 1999
MM74HC373
3-STATE Octal D-Type Latch
General Description
The MM74HC373 high speed octal D-type latches utilize
advanced silicon-gate CMOS technology. They possess
the high noise immunity and low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally
suited for interfacing with bus lines in a bus organized system.
When the LATCH ENABLE input is HIGH, the Q outputs
will follow the D inputs. When the LATCH ENABLE goes
LOW, data at the D inputs will be retained at the outputs
until LATCH ENABLE returns HIGH again. When a high
logic level is applied to the OUTPUT CONTROL input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range: 2 to 6 volts
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74 Series)
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
Package Number
MM74HC373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC373SJ
MM74HC373MTC
MM74HC373N
MTC20
N20A
Package Description
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Output
Latch
Control
Enable
Data
373
Output
L
H
H
L
H
L
H
L
L
L
X
Q0
H
X
X
Z
H = HIGH Level
L = LOW Level
Q0 = Level of output before steady-state input conditions were established.
Z = High Impedance
Top View
© 1999 Fairchild Semiconductor Corporation
DS005335.prf
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MM74HC373 3-STATE Octal D-Type Latch
September 1983
MM74HC373
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±35 mA
(VIN,VOUT )
Operating Temperature Range (TA)
600 mW
500 mW
V
0
VCC
V
−40
+85
°C
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Units
6
(tr, tf) VCC = 2.0V
Power Dissipation (PD)
S.O. Package only
Max
2
Input Rise or Fall Times
−65°C to +150°C
(Note 3)
Min
DC Input or Output Voltage
±70 mA
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Supply Voltage (VCC)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
V
6.0V
4.2
4.2
4.2
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| ≤ 6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| ≤ 7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
|IOUT| ≤ 6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|IOUT| ≤ 7.8 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum 3-STATE
VIN = VIH or VIL, OC = VIH
6.0V
±0.5
±5
±10
µA
Output Leakage
VOUT = VCC or GND
6.0V
8.0
80
160
µA
VIN = VIH or VIL
IIN
Maximum Input
Current
IOZ
Current
ICC
Maximum Quiescent
VIN = VCC or GND
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC373
AC Electrical Characteristics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
Symbol
Parameter
Conditions
Guaranteed
Typ
Limit
Units
tPHL, tPLH
Maximum Propagation Delay, Data to Q CL = 45 pF
18
25
tPHL, tPLH
Maximum Propagation Delay, LE to Q
CL = 45 pF
21
30
ns
tPZH, tPZL
Maximum Output Enable Time
RL = 1 kΩ
20
28
ns
tPHZ, tPLZ
Maximum Output Disable Time
18
25
ns
ns
CL = 45 pF
RL = 1 kΩ
CL = 5 pF
tS
Minimum Set Up Time
5
ns
tH
Minimum Hold Time
10
ns
tW
Minimum Pulse Width
16
ns
9
AC Electrical Characteristics
VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
tPHL, tPLH Maximum Propagation
Delay, Data to Q
tPHL, tPLH Maximum Propagation
Delay, LE to Q
tPZH, tPZL Maximum Output
Enable Time
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
CL = 50 pF
2.0V
50
150
188
225
CL = 150 pF
2.0V
80
200
250
300
ns
CL = 50 pF
4.5V
22
30
37
45
ns
ns
CL = 150 pF
4.5V
30
40
50
60
ns
CL = 50 pF
6.0V
19
26
31
39
ns
CL = 150 pF
6.0V
26
35
44
53
ns
CL = 50 pF
2.0V
63
175
220
263
ns
CL = 150 pF
2.0V
110
225
280
338
ns
CL = 50 pF
4.5V
25
35
44
52
ns
CL = 150 pF
4.5V
35
45
56
68
ns
CL = 50 pF
6.0V
21
30
37
45
ns
CL = 150 pF
6.0V
28
39
49
59
ns
CL = 50 pF
2.0V
50
150
188
225
ns
CL = 150 pF
2.0V
80
200
250
300
ns
CL = 50 pF
4.5V
21
30
37
45
ns
RL = 1 kΩ
CL = 150 pF
4.5V
30
40
50
60
ns
CL = 50 pF
6.0V
19
26
31
39
ns
CL = 150 pF
6.0V
26
35
44
53
ns
tPHZ, tPLZ Maximum Output Disable
RL = 1 kΩ
2.0V
50
150
188
225
ns
Disable Time
CL = 50 pF
tS
tH
tW
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
tTHL, tTLH Maximum Output Rise
CL = 50 pF
and Fall Time
CPD
CIN
4.5V
21
30
37
45
ns
6.0V
19
26
31
39
ns
2.0V
50
60
75
ns
4.5V
9
13
15
ns
6.0V
9
11
13
ns
2.0V
5
5
5
ns
4.5V
5
5
5
ns
6.0V
5
5
5
ns
80
100
120
ns
2.0V
30
4.5V
10
16
20
24
ns
6.0V
9
14
18
20
ns
2.0V
25
60
75
90
ns
4.5V
7
12
15
18
ns
6.0V
6
10
13
15
ns
Power Dissipation
(per latch)
Capacitance (Note 5)
OC = VCC
30
OC = GND
50
Maximum Input Capacitance
5
3
pF
pF
10
10
10
pF
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MM74HC373
AC Electrical Characteristics
Symbol
COUT
Parameter
(Continued)
Conditions
VCC
Maximum Output
TA = 25°C
Typ
15
TA = −40 to 85°C TA = −55 to 125°C
20
20
20
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
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4
Units
Guaranteed Limits
pF
MM74HC373
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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MM74HC373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
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device or system, or to affect its safety or effectiveness.
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instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC373 3-STATE Octal D-Type Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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