Fairchild MM74HC86MTCX Quad 2-input exclusive or gate Datasheet

MM74HC86
Quad 2-Input Exclusive OR Gate
Description
Features





Typical Propagation Delay: 9ns
Wide Operating Voltage Range: 2–6V
Low Input Current: 1mA Maximum
Low Quiescent Current: 20mA Max. (74 Series)
Output Drive Capability: 10 LS-TTL Loads
The MM74HC86 exclusive OR gate utilizes advanced
silicon-gate CMOS technology to achieve operating
speeds similar to equivalent LS-TTL gates, while
maintaining the low power consumption and high noise
immunity characteristic of standard CMOS integrated
circuits. These gates are fully buffered and have a
fanout of 10 LS-TTL loads. The 74HC logic family is
functionally as well as pin-out compatible with the
standard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps
to VCC and ground.
Table 1.
MM74HC86 — Quad 2-Input Exclusive OR Gate
May 2012
Truth Table
Inputs
A
Outputs
B
Y(1)
L
L
L
L
H
H
H
L
H
H
H
L
Note:
1.
Figure 1.
Y  A  B  A B  AB
Pin Assignments (Top View)
Ordering Information
Part Number
Operating
Temperature Range
MM74HC86M
MM74HC86MX
MM74HC86MTC
-40 to +85°C
MM74HC86MTCX
Package
Packing Method
Tube
14-Lead, Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150" Narrow
Tape & Reel
14-Lead, Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153, 4.4mm Wide
Tape & Reel
Tube
Note:
2. Pb-Free package per JEDEC J-STD-020B.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
Absolute maximum ratings are stress ratings only. Unless otherwise specified, all voltages are referenced to ground.
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply Voltage
-0.5
7.0
V
VIN
DC Input Voltage
-1.5
VCC +1.5
V
DC Output Voltage
-0.5
VOUT
IIK, IOK
VCC +0.5
V
Clamp Diode Current
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC VCC or GND Current, per Pin
±50
mA
TSTG
TL
PD
Storage Temperature Range
-65
Lead Temperature (Soldering, 10 Seconds)
(3, 4)
Power Dissipation
+150
°C
260
°C
600
mW
Note:
3. Power dissipation temperature derating — plastic “N” package: -12 mW/°C from 65°C to 85°C.
4. S.O. package only 500mW.
MM74HC86 — Quad 2-Input Exclusive OR Gate
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
VIN, VOUT
TA
tR, tF
Parameter
Conditions
Min.
Max.
Unit
Supply Voltage
2
6
V
DC Input or Output Voltage
0
VCC
V
-40
+85
°C
Operating Temperature Range
Input Rise or Fall Times
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
VCC = 2.0V
1000
VCC = 4.5V
500
VCC = 6.0V
400
ns
www.fairchildsemi.com
2
Symbol
Parameter
Condition
VCC (V)
Typ.
VIH
VIL
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
VIN = VIH or VIL,
|IOUT| ≤ 20µA
VOH
Minimum HIGH Level
Output Voltage
Maximum LOW Level
Output Voltage
Guaranteed Limit
2.0
1.5
1.5
1.5
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
2.0
0.5
0.5
0.5
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
2.0
2.0
1.9
1.9
1.9
4.5
4.5
4.4
4.4
4.4
6.0
6.0
5.9
5.9
5.9
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.5
4.2
3.98
3.84
3.70
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
6.0
5.7
5.48
5.34
5.20
2.0
0
0.1
0.1
0.1
4.5
0
0.1
0.1
0.1
6.0
0
0.1
0.1
0.1
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.5
0.2
0.26
0.33
0.40
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
6.0
0.2
0.26
0.33
0.40
VIN = VIH or VIL,
|IOUT| ≤ 20µA
VOL
TA=-40 to TA=-55 to
+85°C
+125°C Units
TA=25°C
V
V
V
MM74HC86 — Quad 2-Input Exclusive OR Gate
DC Electrical Characteristics(5)
V
IIN
Maximum Input Current
VIN = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND,
IOUT = 0mA
6.0
2.0
20
40
mA
Note:
5. For a power supply of 5V ±10%, the worst-case output voltages (VOH and VOL) occur for HC at 4.5V. Thus, the
4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and
4.5V, respectively. (The VIH values at 5V and 5.5V are 3.5V and 3.85V, respectively.) The worst-case leakage
current (IIN, ICC, and IOZ) occurs for CMOS at the higher voltage, so the 6.0V values should be used.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
3
Symbol
Parameter
tPHL, tPLH Maximum Propagation Delay
Conditions
CL = 15pF,
tR = tF = 6ns
tPHL, tPLH Maximum Propagation Delay
tTLH, tTHL
Maximum Output Rise and
Fall Time
CL = 50pF,
tR = tF = 6ns
TA=-40 to TA=-55 to
+85°C
+125°C Unit
TA=25°C
VCC
s
Typ.
Guaranteed Limit
5.0
12
20
2.0
60
120
151
179
4.5
12
24
30
36
6.0
10
20
26
30
2.0
30
75
95
110
4.5
8
15
19
22
6.0
7
13
16
19
CPD
Power Dissipation
Capacitance (per Gate)(6)
25
CIN
Maximum Input Capacitance
5
ns
ns
ns
MM74HC86 — Quad 2-Input Exclusive OR Gate
AC Electrical Characteristics
pF
10
10
10
pF
Note:
2
6. CPD determines the no-load dynamic power consumption, PD = CPD VCC f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
4
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1
PIN ONE
INDICATOR
1.70
7
0.51
0.35
1.27
0.25
(0.33)
1.75 MAX
1.50
1.25
1.27
LAND PATTERN RECOMMENDATION
M
C B A
MM74HC86 — Quad 2-Input Exclusive OR Gate
Physical Dimensions
SEE DETAIL A
0.25
0.10
C
0.25
0.19
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50
0.25 X 45°
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 2.
14-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
5
MM74HC86 — Quad 2-Input Exclusive OR Gate
Physical Dimensions
0.65
0.43 TYP
1.65
6.10
0.45
12.00°TOP
& BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 3.
1.00
R0.09min
14-Lead, Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
6
MM74HC86 — Quad 2-Input Exclusive OR Gate
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
7
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