Fairchild MM74HCT08MX NL Quad 2-input and gate Datasheet

Revised January 2005
MM74HCT08
Quad 2-Input AND Gate
General Description
Features
The MM74HCT08 is a logic function fabricated by using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power and
wide power supply range. This device is input and output
characteristic and pinout compatible with standard 74LS
logic families. All inputs are protected from static discharge
damage by internal diodes to VCC and ground.
■ TTL, LS pin-out and threshold compatible
■ Fast switching: tPLH, tPHL = 12 ns (typ)
■ Low power: 10 µW at DC
■ High fan-out, 10 LS-TTL loads
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Ordering Code:
Order Number
Package
Package Description
Number
MM74HCT08M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HCT08MX_NL
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT08SJ
MM74HCT08MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT08MTCX_NL
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HCT08N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Diagram
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
© 2005 Fairchild Semiconductor Corporation
DS005754
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MM74HCT08 Quad 2-Input AND Gate
December 1983
MM74HCT08
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
Storage Temperature Range (TSTG)
600 mW
500 mW
V
0
VCC
V
−40
+85
°C
500
ns
Input Rise or Fall Times
(tr, tf)
Power Dissipation (PD)
S.O. Package only
Units
5.5
(VIN, VOUT)
Operating Temperature Range (TA)
−65°C to +150°C
(Note 3)
Max
4.5
DC Input or Output Voltage
±50 mA
DC VCC or GND Current, per pin (ICC)
Min
Supply Voltage (VCC)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package −12
mW/°C from 65°C to 85°C.
Lead Temperature (TL)
260°C
(Soldering 10 seconds)
DC Electrical Characteristics
VCC = 5V ± 10% (unless otherwise specified)
Symbol
VIH
Parameter
TA = 25°C
Conditions
Typ
Minimum HIGH Level
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
2.0
2.0
2.0
V
0.8
0.8
0.8
V
Input Voltage
VIL
Maximum LOW Level
Input Voltage
VOH
VOL
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| = 20 µA
VCC
VCC− 0.1
VCC− 0.1
VCC− 0.1
V
|IOUT| = 4.0 mA, VCC = 4.5V
4.2
3.98
3.84
3.7
V
|IOUT| = 4.8 mA, VCC = 5.5V
5.2
4.98
4.84
4.7
V
Maximum LOW Level
Voltage
IIN
VIN = VIH
|IOUT| = 20 µA
0
0.1
0.1
0.1
V
|IOUT| = 4.0 mA, VCC = 4.5V
0.2
0.26
0.33
0.4
V
|IOUT| = 4.8 mA, VCC = 5.5V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND, VIH or VIL
±0.1
±1.0
±1.0
µA
Maximum Quiescent
VIN = VCC or GND
2.0
20
40
µA
Supply Current
IOUT = 0 µA
1.2
1.4
1.5
mA
Maximum Input
Current
ICC
VIN = 2.4V or 0.5V (Note 4)
Note 4: This is measured per input with all other inputs held at VCC or ground.
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VCC = 5.0V, tr = tf = 6 ns, CL = 15 pF, TA = 25°C
Symbol
tPLH, tPHL
Parameter
Conditions
Maximum Propagation Delay
Typ
Guaranteed
Limit
Units
9
15
ns
AC Electrical Characteristics
VCC = 5.0V ± 10%, tr = tf = 6 ns, CL = 50 pF
Symbol
Parameter
TA = 25°C
Conditions
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
tPLH, tPHL Maximum Propagation Delay
11
18
23
27
tTHL, tTLH Maximum Output Rise & Fall Time
7
15
19
22
CPD
Power Dissipation Capacitance
CIN
Input Capacitance
(Note 5)
38
5
Units
ns
ns
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption. PD = CPD VCC2 f + ICC VCC and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
3
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MM74HCT08
AC Electrical Characteristics
MM74HCT08
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
MM74HCT08
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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MM74HCT08
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
MM74HCT08 Quad 2-Input AND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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