MP C50 MPC508A MPC509A 8 MP C50 9 SBFS019A – JANUARY 1988 — REVISED OCTOBER 2003 Single-Ended 8-Channel/Differential 4-Channel CMOS ANALOG MULTIPLEXERS FEATURES FUNCTIONAL DIAGRAMS ● ANALOG OVERVOLTAGE PROTECTION: 70VPP ● NO CHANNEL INTERACTION DURING OVERVOLTAGE ● BREAK-BEFORE-MAKE SWITCHING ● ANALOG SIGNAL RANGE: ±15V ● STANDBY POWER: 7.5mW typ ● TRUE SECOND SOURCE 1kΩ In 1 Out 1kΩ In 2 Decoder/ Driver 1kΩ In 8 Overvoltage Clamp and Signal Isolation DESCRIPTION The MPC508A is an 8-channel single-ended analog multiplexer and the MPC509A is a 4-channel differential multiplexer. The MPC508A and MPC509A multiplexers have input overvoltage protection. Analog input voltages may exceed either power supply voltage without damaging the device or disturbing the signal path of other channels. The protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand 70VPP signal levels and standard ESD tests. Signal sources are protected from short circuits should multiplexer power loss occur; each input presents a 1kΩ resistance under this condition. Digital inputs can also sustain continuous faults up to 4V greater than either supply voltage. 5V Ref Level Shift (1) (1) NOTE: (1) Digital Input Protection. MPC508A (1) A0 A1 A2 (1) EN 1kΩ In 1A Out A 1kΩ In 4A 1kΩ In 1B Out B 1kΩ Decoder/ Driver In 4B These features make the MPC508A and MPC509A ideal for use in systems where the analog signals originate from external equipment or separately powered sources. The MPC508A and MPC509A are fabricated with BurrBrown’s dielectrically isolated CMOS technology. The multiplexers are available in plastic DIP and plastic SOIC packages. Temperature range is –40°C to +85°C. Overvoltage Clamp and Signal Isolation NOTE: (1) Digital Input Protection. MPC509A 5V Ref Level Shift (1) (1) (1) A0 A1 EN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1998-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTRICAL CHARACTERISTICS Supplies = +15V, –15V; VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +0.8V, unless otherwise specified. MPC508A/509A PARAMETER ANALOG CHANNEL CHARACTERISTICS VS, Analog Signal Range RON, On Resistance(1) IS (OFF), Off Input Leakage Current ID (OFF), Off Output Leakage Current MPC508A MPC509A ID (OFF) with Input Overvoltage Applied(2) ID (ON), On Channel Leakage Current MPC508A MPC509A IDIFF Differential Off Output Leakage Current (MPC509A Only) DIGITAL INPUT CHARACTERISTICS VAL, Input Low Threshold Drive VAH, Input High Threshold(3) IA, Input Leakage Current (High or Low)(4) SWITCHING CHARACTERISTICS tA, Access Time tOPEN, Break-Before-Make Delay tON (EN), Enable Delay (ON) tOFF (EN), Enable Delay (OFF) Settling Time (0.1%) (0.01%) "OFF Isolation"(5) CS (OFF), Channel Input Capacitance CD (OFF), Channel Output Capacitance: MPC508A MPC509A CA, Digital Input Capacitance CDS (OFF), Input to Output Capacitance POWER REQUIREMENTS PD, Power Dissipation I+, Current Pin 1(6) I–, Current Pin 27(6) TEMP MIN Full +25°C Full +25°C Full +25°C Full Full +25°C +25°C Full Full –15 TYP 1.3 1.5 0.5 MAX UNITS +15 1.5 1.8 10 10 V kΩ kΩ nA nA nA nA nA µA nA nA nA 10 nA 0.8 V V µA 10 0.2 5 5 2.0 2 Full Full Full Full 4.0 1.0 +25°C Full +25°C +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C 25°C +25°C µs µs ns ns ns ns ns µs µs dB pF pF pF pF pF 0.5 0.6 25 80 200 500 250 500 50 Full Full Full 1.2 3.5 68 5 25 12 5 0.1 7.5 0.7 5 mW mA µA 1.5 20 NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended. (4) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (5) VEN = 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 4 due to proximity of the output pins. (6) VEN, VA = 0V or 4.0V. 2 MPC508A, MPC509A www.ti.com SBFS019A PIN CONFIGURATIONS Top View Top View A0 1 16 A1 A0 1 16 A1 En 2 15 A2 En 2 15 –VSUPPLY 3 14 Ground –VSUPPLY 3 14 +VSUPPLY In 1 4 13 In 1A 4 13 In 1B In 2 5 12 In 5 In 2A 5 12 In 2B In 3 6 11 In 6 In 3A 6 11 In 3B In 4 7 10 In 7 In 4A 7 10 In 4B Out 8 9 In 8 Out A 8 9 +VSUPPLY MPC508A (Plastic) Ground Out B MPC509 A (Plastic) TRUTH TABLES MPC508A MPC509A A2 A1 A0 EN "ON" CHANNEL X L L L L H H H H X L L H H L L H H X L H L H L H L H L H H H H H H H H None 1 2 3 4 5 6 7 8 ABSOLUTE MAXIMUM RATINGS(1) "ON" CHANNEL A1 A0 EN PAIR X L L H H X L H L H L H H H H None 1 2 3 4 PACKAGE/ORDERING INFORMATION Voltage between supply pins ............................................................... 44V V+ to ground ........................................................................................ 22V V– to ground ........................................................................................ 25V Digital input overvoltage VEN, VA: VSUPPLY (+) ................................................... +4V VSUPPLY (–) ................................................... –4V or 20mA, whichever occurs first. Analog input overvoltage VS: VSUPPLY (+) ................................................ +20V VSUPPLY (–) ................................................ –20V Continuous current, S or D ............................................................... 20mA Peak current, S or D (pulsed at 1ms, 10% duty cycle max) ............................................ 40mA Power dissipation(2) .......................................................................... 1.28W Operating temperature range ........................................... –40°C to +85°C Storage temperature range ............................................. –65°C to +150°C For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. NOTE: (1) Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. (2) Derate 1.28mW/°C above TA = +70°C. MPC508A, MPC509A SBFS019A www.ti.com 3 TYPICAL PERFORMANCE CURVES Typical at +25°C unless otherwise noted. SETTLING TIME vs SOURCE RESISTANCE FOR 20V STEP CHANGE CROSSTALK vs SIGNAL FREQUENCY 1k Crosstalk (% of Off Channel Signal) 1 Settling Time (µs) 100 To ±0.01% 10 To ±0.1% 1 0.1 0.01 0.1 Rs = 100kΩ Rs = 10kΩ 0.01 Rs = 1kΩ Rs = 100Ω 0.001 0.0001 0.1 10 1 100 1 10 1k 100 10k Signal Frequency (Hz) Source Resistance (kΩ) COMBINED CMR vs FREQUENCY MPC509A AND INA110 Common-Mode Rejection (dB) 120 G = 500 100 G = 100 80 G = 10 60 40 20 0 1 10 100 1k 10k Frequency (Hz) 4 MPC508A, MPC509A www.ti.com SBFS019A Differential Multiplexer Static Accuracy DISCUSSION OF PERFORMANCE DC CHARACTERISTICS The static or dc transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current and the multiplexer leakage current. Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for singleended multiplexers are: Source resistance loading error; Multiplexer ON resistance error; and, dc offset error caused by both load bias current and multiplexer leakage current. Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low-level signals with full-scale ranges of 10mV to 100mV. The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differential impedance mismatch, and commonmode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. The effects of these errors can be minimized by following the general guidelines described in this section, especially for low-level multiplexing applications. Refer to Figure 2. Resistive Loading Errors Load (Output Device) Characteristics The source and load impedances will determine the input resistive loading errors. To minimize these errors: • Use devices with very low bias current. Generally, FET input amplifiers should be used for low-level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine the input offset. • The system dc common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode, should be 1010Ω or higher. • • Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedances of 108Ω, or greater, will keep resistive loading errors to 0.002% or less for 1000Ω source impedances. A 106Ω load impedance will increase source loading error to 0.2% or more. Use sources with impedances as low as possible. 1000Ω source resistance will present less than 0.001% loading error and 10kΩ source resistance will increase source loading error to 0.01% with a 108 load impedance. VM Source and Multiplexer Resistive Loading Error ∈(RS + RON ) = IBIAS RON RS1 Input resistive loading errors are determined by the following relationship (see Figure 1). RS + RON × 100% RS + RON + RL ROFF RS8 VS1 Measured Voltage IL ZL VS8 where RS = source resistance RL = load resistance RON = multiplexer ON resistance FIGURE 1. MPC508A DC Accuracy Equivalent Circuit. RS1 Input Offset Voltage RON1A IBIAS A Cd/2 Bias current generates an input OFFSET voltage as a result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA will generate an offset voltage of 20µV if a 1kΩ source is used. In general, for the MPC508A, the OFFSET voltage at the output is determined by: Rd/2 IL VS1 RCM1 RCM RS1B RON1B IBIAS B ZL CCM Cd/2 Rd/2 RS4A ROFF4A VOFFSET = (IB + IL) (RON + RS) ILB where IB = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance RS = source resistance VS8 RS48 ROFF4B RCM4 FIGURE 2. MPC509A DC Accuracy Equivalent Circuit. MPC508A, MPC509A SBFS019A www.ti.com 5 Source Characteristics • • • The source impedance unbalance will produce offset, common-mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. RSA Node A CSA RCMS Source CSB Keep source impedances as low as possible to minimize resistive loading errors. CCMS Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. RSB CdA RdA ZCM MPC509A Load Channel RdB Node B CdB If the MPC509A is used for multiplexing high-level signals of ±1V to ±10V full-scale ranges, the foregoing precautions should still be taken, but the parameters are not as critical as for low-level signal applications. DYNAMIC CHARACTERISTICS Settling Time The gate-to-source and gate-to-drain capacitance of the CMOS FET switches, the RC time constants of the source and the load determine the settling time of the multiplexer. Governed by the charge transfer relation i = C (dV/dt), the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-to-drain and gate-to-source junction capacitances as shown in Figures 3 and 4. Using this relationship, one can see that the amplitude of the switching transients, seen at the source and load, decrease proportionally as the capacitance of the load and source increase. The trade-off for reduced switching transient amplitude is increased settling time. In effect, the amplitude of the transients seen at the source and load are: dVL = (i/C) dt where i = C (dV/dt) of the CMOS FET switches C = load or source capacitance The source must then redistribute this charge, and the effect of source resistance on settling time is shown in the Typical Performance Curves. This graph shows the settling time for a 20V step change on the input. The settling time for smaller step changes on the input will be less than that shown in the curve. MPC508A Channel Source Load Node A RS CS CL RL FIGURE 4. Settling and Common-Mode-Effects— MPC509A Switching Time This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. Crosstalk Crosstalk is the amount of signal feedthrough from the three (MPC509A) or seven (MPC508A) OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel, OFF resistance and junction capacitances in series with the RON and RS impedances of the ON channel. Crosstalk is measured with a 20Vp-p 1kHz sine wave applied to all OFF channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. Common-Mode Rejection (MPC509A Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. For the MPC509A, protection is provided for common-mode signals of ±20V above the power supply voltages with no damage to the analog switches. The CMR of the MPC509A and Burr-Brown’s INA110 instrumentation amplifier is 110dB at DC to 10Hz (G = 100) with a 6dB/octave roll off to 70dB at 1000Hz. This measurement of CMR is shown in the Typical Performance Curves and is made with a Burr-Brown model INA110 instrumentation amplifier connected for gains of 10, 100, and 500. FIGURE 3. Settling Time Effects—MPC508A 6 MPC508A, MPC509A www.ti.com SBFS019A Factors which will degrade multiplexer and system DC CMR are: • • Amplifier bias current and differential impedance mismatch Load impedance mismatch • Multiplexer impedance and leakage current mismatch • Load and source common-mode impedance AC CMR roll off is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer-to-amplifier wiring must be minimized. Use twisted-shielded-pair signal lines wherever possible. SWITCHING WAVEFORMS Typical at +25°C, unless otherwise noted. BREAK-BEFORE-MAKE DELAY (tOPEN) VAM 4.0V Address Drive VA (VA) 0V 50Ω Output 50% A2 A1 A0 MPC508A(1) In 1 In 2 Thru In 7 1 On In 8 Output 0.5V/Div VOUT En 50% VA Input 2V/Div +5V +4.0V GND Out 12.5pF 1kΩ tOPEN 100ns/Div NOTE: (1) Similar connection for MPC509A. ENABLE DELAY (tON (EN), tOFF (EN)) Enable Drive MPC508A(1) In 1 A2 A1 In 2 Thru In 8 A0 VAM 4.0V 50% 0V Output 90% 90% tON(EN) VA En GND Enable Drive 2V/Div +10V Out 12.5pF 1kΩ 50Ω tOFF(EN) NOTE: (1) Similar connection for MPC509A. MPC508A, MPC509A SBFS019A www.ti.com Output 2V/Div 100ns/Div 7 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS Unless otherwise specified: TA = +25, VS = ±15V, VAM = +4V, VAL = 0.8V. ON RESISTANCE vs ANALOG INPUT SIGNAL, SUPPLY VOLTAGE 100µA RON = V2/100µA V2 In Out VIN NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE ON RESISTANCE vs ANALOG INPUT VOLTAGE 1.6 1.4 1.3 Normalized On Resistance (Referred to Value at ±15V) On Resistance (kΩ) 1.2 1.1 TA = +25°C 1.0 TA = –55°C 0.9 ±125°C > TA > –55°C VIN = +5V 1.5 TA = +125°C 0.8 1.4 1.3 1.2 1.1 1.0 0.9 0.7 0.8 0.6 –10 –8 –6 –4 –2 0 2 4 6 8 ±5 10 ±6 ±7 ±8 ±9 ±10 ±11 ±12 ±13 ±14 ±15 Supply Voltage (V) Analog Input (V) SUPPLY CURRENT vs TOGGLE FREQUENCY +15V/+10V 8 MPC508A(1) A2 En VA A1 A0 50Ω Supply Current (mA) A +ISUPPLY ±10V/±5V In 2 Thru In 7 ±10V/±5V In 8 En GND –V Out +4V ±10V/±5V 10MΩ 6 4 VS = ±15V 2 VS = ±10V 14pF A –ISUPPLY 0 100 1k 10k 100k 1M 10M –15V/–10V Toggle Frequency (Hz) NOTE: (1) Similar connection for MPC509A. 8 MPC508A, MPC509A www.ti.com SBFS019A PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) LEAKAGE CURRENT vs TEMPERATURE En +0.8V Out Out ±10V ID (Off) A0 ± A ± 10V A En A1 ID (On) ±10V 10V +4.0V Leakage Current 100nA Out IS (Off) A ±10V En Off Output Current ID (Off) 10nA On Leakage Current ID (On) 1nA Off Input Leakage Current IS (Off) +0.8V 10V ± 100pA 10pA 25 NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V. (Two measurements per device for ID (Off): +10V/–10V and –10V/+10V). 50 75 100 125 Temperature (°C) ANALOG INPUT OVERVOLTAGE CHARACTERISTICS 7 21 A A +VIN 18 6 15 5 Analog Input Current (IIN) 12 4 3 9 6 2 Output Off Leakage Current IO (Off) 3 0 +12 +15 +18 +21 +24 +27 +30 +33 1 Output Off Leakage Current (nA) IO (Off) IIN Analog Input Current (mA) Positive Input Overvoltage 0 +36 Analog Input Overvoltage (V) 21 A −V IN A 4 15 Analog Input Current (IIN) 12 2 9 6 Output Off Leakage Current IO (Off) 3 Output Off Leakage Current (µA) IO (Off) IIN Analog Input Current (mA) Negative Input Overvoltage 18 0 0 −12 −15 −18 −21 −24 −27 −30 −33 −36 Analog Input Overvoltage (V) MPC508A, MPC509A SBFS019A www.ti.com 9 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) ACCESS TIME vs LOGIC LEVEL (High) 1000 +15V A2 VA A1 A0 50Ω +4V 900 +V In 1 In 2 Thru In 7 MPC 508A(1) In 8 En GND –10V +10V Access Time (ns) VREF Probe –V Out 10MΩ –15V 14pF 800 700 600 500 400 300 3 4 5 6 NOTE: (1) Similar connection for MPC509A. 7 8 9 10 11 12 13 14 15 Logic Level High (V) ACCESS TIME WAVEFORM VAM 4.0V Address Drive (VA) 50% VA Input 2V/Div 0V 10V Output A 90% Output A 5V/Div 10V tA 200ns/Div ON-CHANNEL CURRENT vs VOLTAGE ±14 –55°C Switch Current (mA) ±12 A ±VIN +25°C +125°C ±10 ±8 ±6 ±4 ±2 0 0 ±2 ±4 ±6 ±8 ±10 ±12 ±14 ±16 VIN –Voltage Across Switch (V) 10 MPC508A, MPC509A www.ti.com SBFS019A If the +15V and/or –15V supply voltage is absent or shorted to ground, the MPC509A and MPC508A multiplexers will not be damaged; however, some signal feedthrough to the output will occur. Total package power dissipation must not be exceeded. For best settling speed, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull-up resistors are recommended To preserve common-mode rejection of the MPC509A, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. CHANNEL EXPANSION 8 Analog Inputs (CH1 to 8) The ENABLE input, pin 2, is included for expansion of the number of channels on a single node as illustrated in Figure 5. With ENABLE line at a logic 1, the channel is selected by the 2-bit (MPC509A) or 3-bit (MPC508A) Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to +VSUPPLY. In 1 In 2 In 3 8 Out MPC508A En In 8 2 Multiplexer Output +V A0 A1 A2 In 1 Out Direct MPC508A En 8 Analog Inputs (CH57 to 64) INSTALLATION AND OPERATING INSTRUCTIONS In 1 In 2 In 3 In 8 A0 A1 A2 Buffered OPA602 1/4 OPA404 Out 8 MPC508A In 8 +V En 2 +V A0 A1 A2 Settling Time to ±0.01% is 20µs with RS = 100Ω 4LSBs 4MSBs 6-Bit Channel Address Generator FIGURE 6. Channel Expansion Up to 64 Channels Using 8 x 8 Two-Tiered Expansion. Differential Multiplexer (MPC509A) Single or multitiered configurations can be used to expand multiplexer channel capacity up to 32 channels using a 32 x 1 or 16 channels using a 4 x 4 configuration. Single-Ended Multiplexer (MPC508A) In 1 In 2 MPC Out In 3 508A 8 Group 1 Ch1-8 Group 1 In 8 2 Enable A2 A1 A0 20 21 22 8 Analog Inputs 23 24 Multiplexer Output Buffered OPA602 1/4 OPA404 To In 1 A2 A1 A0 Group In 2 Group 4 2 3 In 3 Enable MPC 508A Out 8 In 8 Group 4 Settling Time to 0.01% for RS < 100Ω Ch25-42 —Two MPC508A units in parallels: 10µs —Four MPC509 A units in parallels: 12µs FIGURE 5. 32-Channel, Single-Tier Expansion. Single-Node Expansion The 32 x 1 configuration is simply eight (MPC509A) units tied to a single node. Programming is accomplished with a 5-bit counter, using the 2LSBs of the counter to control Channel Address inputs A0 and A1 and the 3MSBs of the counter to drive a 1-of-8 decoder. The 1-of-8 decoder then is used to drive the ENABLE inputs (pin 2) of the MPC509A multiplexers. Two-Tier Expansion Direct 5-Bit To Binary Group Counter 2 1 of 4 Decoder 8 Analog Inputs Up to 32 channels (four multiplexers) can be connected to a single node, or up to 64 channels using nine MPC508A multiplexers on a two-tiered structure as shown in Figures 5 and 6. Using a 4 x 4 two-tier structure for expansion to 16 channels, the programming is simplified. A 4-bit counter output does not require a 1-of-8 decoder. The 2LSBs of the counter drive the A0 and A1 inputs of the four first-tier multiplexers and the 2MSBs of the counter are applied to the A0 and A1 inputs of the second-tier multiplexer. Single vs Multitiered Channel Expansion In addition to reducing programming complexity, two-tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one channel group is failed (4 or 8) in the multitiered configuration. MPC508A, MPC509A SBFS019A www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) MPC508AP ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type MPC508AP MPC508APG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type MPC508AP MPC508AU ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC508AU MPC508AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC508AU MPC508AU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC508AU MPC508AUG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC508AU MPC509AP ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type MPC509AP MPC509APG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type MPC509AP MPC509AU ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MPC509AU MPC509AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC509AU MPC509AU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC509AU MPC509AUG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 MPC509AU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MPC508AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 MPC509AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MPC508AU/1K SOIC DW 16 1000 367.0 367.0 38.0 MPC509AU/1K SOIC DW 16 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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