MOTOROLA MPC950 Low voltage pll clock driver Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MPC950/951 are 3.3V compatible, PLL based clock driver
devices targeted for high performance clock tree designs. With output
frequencies of up to 180MHz and output skews of 375ps the MPC950 is
ideal for the most demanding clock tree designs. The devices employ a
fully differential PLL design to minimize cycle–to–cycle and long term
jitter. This parameter is of significant importance when the clock driver is
providing the reference clock for PLL’s on board today’s microprocessors
and ASiC’s. The devices offer 9 low skew outputs, the outputs are
configurable to support the clocking needs of the various high
performance microprocessors.
LOW VOLTAGE
PLL CLOCK DRIVER
• Fully Integrated PLL
• Oscillator or Crystal Reference Input
• Output Frequency up to 180MHz
• Outputs Disable in High Impedance
• Compatible with PowerPC, Intel and High Performance RISC
Microprocessors
• TQFP Packaging
• Output Frequency Configurable
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
• ±100ps Typical Cycle–to–Cycle Jitter
Two selectable feedback division ratios are available on the MPC950
to provide input reference clock flexibility. The FBSEL pin will choose
between a divide by 8 or a divide by 16 of the VCO frequency to be
compared with the input reference to the MPC950. The internal VCO is
running at either 2x or 4x the high speed output, depending on
configuration, so that the input reference will be either one half, one fourth
or one eighth the high speed output.
The MPC951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential PECL reference input and
an external feedback input. These features allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition,
the external feedback allows for a wider variety of input–to–output frequency relationships. The MPC951 REF_SEL pin allows for
the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an
LVCMOS source.
The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL
pin allows the user to select between a crystal input to an on–board oscillator for the reference or to chose a TTL level oscillator
input directly. The on–board crystal oscillator requires no external components beyond a series resonant crystal.
Both the MPC950 and MPC951 are fully 3.3V compatible and require no external loop filter components. All inputs accept
LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω
transmission lines. Select inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the
PECL_CLK inputs are not used, they can be left open. For series terminated 50Ω lines, each of the MPC950/951 outputs can
drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to
provide the optimum combination of board density and performance.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
2/97
 Motorola, Inc. 1997
1
REV 4
MPC950 MPC951
MPC950 LOGIC DIAGRAM
fsela
PLL_En
Tclk
Ref_Sel
xtal1
xtal2
VCO
200–480MHz
PHASE
DETECTOR
xtal
OSC
LPF
÷2/÷4
Qa
÷4/÷8
Qb
÷8/÷16
FBsel
(Pull Down)
fselb
Qc0
÷4/÷8
Qc1
fselc
MR/OE
÷4/÷8
POWER–ON RESET
Qd0
Qd1
fseld
Qd2
Qd3
GNDO
Qd1
VCCO
Qd0
GNDO
Qc1
VCCO
Qc0
Qd4
FUNCTION TABLES
Ref_Sel
24
23
22
21
20
19
18
17
GNDO
25
16
Qd2
Qb
26
15
VCCO
VCCO
27
14
Qd3
Qa
28
13
GNDO
GNDO
29
12
Qd4
TCLK
30
11
VCCO
PLL_En
31
10
MR/OE
Ref_Sel
32
9
2
3
4
5
PLL_En
1
0
FBsel
MPC950
1
1
0
6
7
xtal2
1
0
MR/OE
1
0
1
0
xtal1
GNDI
fseld
fselc
fselb
fsela
FBsel
VCCA
TCLK
XTAL_OSC
Function
PLL Enabled
PLL Bypass
Function
÷8
÷16
Function
Outputs Disabled
Outputs Enabled
8
fseln
MOTOROLA
Function
2
Function
Qa = ÷4; Qb:d = ÷8
Qa = ÷2; Qb:d = ÷4
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
MPC951 LOGIC DIAGRAM
fsela
PLL_En
Tclk
Ref_Sel
PECL_CLK
PECL_CLK
(Pull Up)
VCO
200–550MHz
PHASE
DETECTOR
LPF
Ext_FB
÷2/÷4
Qa
÷4/÷8
Qb
(Pull Down)
fselb
Qc0
÷4/÷8
Qc1
fselc
MR/OE
÷4/÷8
POWER–ON RESET
Qd0
Qd1
fseld
Qd2
Qd3
Qc0
VCCO
Qc1
GNDO
Qd0
VCCO
Qd1
GNDO
Qd4
24
23
22
21
20
19
18
17
FUNCTION TABLES
Ref_Sel
GNDO
25
16
Qd2
Qb
26
15
VCCO
VCCO
27
14
Qd3
Qa
28
13
GNDO
GNDO
29
12
Qd4
TCLK
30
11
VCCO
MR/OE
PLL_En
31
10
MR/OE
1
0
Ref_Sel
32
MPC951
9
1
2
3
4
5
6
7
PECL_CLK
8
1
0
PLL_En
1
0
fseln
TIMING SOLUTIONS
BR1333 — Rev 6
TCLK
PECL_CLK
Function
PLL Enabled
PLL Bypass
Function
Outputs Disabled
Outputs Enabled
Function
Qa = ÷4; Qb:d = ÷8
Qa = ÷2; Qb:d = ÷4
PECL_CLK
GNDI
fseld
fselc
fselb
fsela
Ext_FB
VCCA
1
0
Function
3
MOTOROLA
MPC950 MPC951
FUNCTION TABLE – MPC950/951
INPUTS
fsela
fselb
OUTPUTS
fselc
fseld
TOTALS
Qa(1)
Qb(1)
Qc(2)
Qd(5)
Total 2x
Total x
Total x/2
2x
2x
2x
2x
2x
2x
2x
2x
x
x
x
x
x
x
x
x
x
x
x
x
x/2
x/2
x/2
x/2
x
x
x
x
x/2
x/2
x/2
x/2
x
x
x/2
x/2
x
x
x/2
x/2
x
x
x/2
x/2
x
x
x/2
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
x
x/2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
8
3
6
1
7
2
3
0
9
4
7
2
8
3
6
1
0
5
2
7
1
6
5
8
0
5
2
7
1
6
3
8
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
NOTE: x = fVCO/4; 200MHz < fVCO < 480MHz.
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
125
°C
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
3.6
V
0.8
V
300
1000
mV
VCC–2.0
VCC–0.6
mV
VIH
Input HIGH Voltage
LVCMOS Inputs
2.0
VIL
Input LOW Voltage
LVCMOS Inputs
VPP
Peak–to–Peak Input Voltage
PECL_CLK
VCMR
Common Mode Range
PECL_CLK
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
Cpd
Power Dissipation Capacitance
25
ICC
Maximum Quiescent Supply Current
90
2.4
Condition
Note 1.
V
IOH = –40mA, Note 2.
0.5
V
IOL = 40mA, Note 2.
±120
µA
4
pF
115
pF
Per Output
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC950/951 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
3.0
ns
tr, tf
TCLK Input Rise/Falls
fref
Reference Input Frequency
Note 1.
Note 1.
MHz
fXtal
Crystal Oscillator Frequency
10
25
MHz
frefDC
Reference Input Duty Cycle
25
75
%
Condition
Note 2.
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.
2. See Applications Info section for more crystal information.
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
tr, tf
Output Rise/Fall Time
tpw
Output Duty Cycle
tsk(O)
Output–to–Output Skews
Min
Typ
Max
Unit
0.10
1.0
ns
tCYCLE/2–1000
tCYCLE/2+1000
ps
ps
Same Frequencies
200
375
Different Frequencies
Qafmax < 150MHz
Qafmax > 150MHz
325
500
750
fVCO
PLL VCO
Lock
Range
Feedback = VCO/4
Feedback = VCO/8
Feedback = VCO/16
fmax
Maximum Output
Frequency
Qa (÷2)
Qa/Qb (÷4)
Qb (÷8)
tpd
Input to Ext_FB Delay
(Note 1.)
TCLK
PECL_CLK
tPLZ,HZ
200
200
200
480
480
480
MHz
180
120
60
MHz
400
–600
ps
Output Disable Time
7
ns
tPZL
Output Enable Time
6
ns
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
tlock
Maximum PLL Lock Time
10
ms
50
–950
250
–770
±100
ps
Condition
0.8 to 2.0V
MPC951
MPC950 or 951
MPC950
fref = 50MHz
Feedback=VCO/8
Note 2.
1. The specification is guaranteed for the MPC951 only. The tpd window is specified for a 50Mhz input reference clock. The window will
enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period.
2. See Applications Info section for more jitter information.
APPLICATIONS INFORMATION
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The feedback frequency
should be used to situate the VCO into a frequency range in
which the PLL will be stable. The design of the PLL is such
that for output frequencies between 25 and 180MHz the
MPC950/951 can generally be configured into a stable
region.
Programming the MPC950/951
The MPC950/951 clock driver outputs can be configured
into several frequency relationships, in addition the external
feedback option of the MPC951 allows for a great deal of
flexibility in establishing unique input to output frequency
relationships. The output dividers for the four output groups
allows the user to configure the outputs into 1:1, 2:1, 4:1 and
4:2:1 frequency ratios. The use of even dividers ensures that
the output duty cycle is always 50%. Table 1 illustrates the
various output configurations, the table describes the outputs
using the VCO frequency as a reference. As an example for a
4:2:1 relationship the Qa outputs would be set at VCO/2, the
Qb’s and Qc’s at VCO/4 and the Qd’s at VCO/8. These
settings will provide output frequencies with a 4:2:1
relationship.
The relationship between the input reference and the
output frequency is also very flexible. Table 2 shows the
multiplication factors between the inputs and outputs for the
MPC950. For external feedback (MPC951) Table 1 can be
used to determine the multiplication factor, there are too
many potential combinations to tabularize the external
feedback condition. Figure 1 through Figure 6 illustrates
several programming possibilities, although not exhaustive it
is representative of the potential applications.
The division settings establish the output relationship, but
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
MPC950 MPC951
reference and translate with near zero delay to low skew
LVCMOS outputs. Clock trees implemented in this fashion
will show significantly tighter skews than trees developed
from CMOS fanout buffers.
Using the MPC951 as a Zero Delay Buffer
The external feedback option of the MPC951 clock driver
allows for its use as a zero delay buffer. By using one of the
outputs as a feedback to the PLL the propagation delay
through the device is eliminated. The PLL works to align the
output edge with the input reference edge thus producing a
near zero delay. The input reference frequency affects the
static phase offset of the PLL and thus the relative delay
between the inputs and outputs.
When used as a zero delay buffer the MPC951 will likely
be in a nested clock tree application. For these applications
the MPC951 offers a LVPECL clock input as a PLL reference.
This allows the user to use LVPECL as the primary clock
distribution device to take advantage of its far superior skew
performance. The MPC951 then can lock onto the LVPECL
To minimize part–to–part skew the external feedback
option again should be used. The PLL in the MPC951
decouples the delay of the device from the propagation delay
variations of the internal gates. From the specification table
one sees a Tpd variation of only ±200ps, thus for multiple
devices under identical configurations the part–to–part skew
will be around 1000ps (350ps for Tpd variation plus 350ps
output–to–output skew plus 300ps for I/O jitter). By running
the devices at the highest possible input reference, this
part–to– part skew can be minimized. Higher input reference
frequencies will minimize both I/O jitter and tpd variations.
Table 1. Programmable Output Frequency Relationships
INPUTS
OUTPUTS
fsela
fselb
fselc
fseld
Qa
Qb
Qc
Qd
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Table 2. Input Reference versus Output Frequency Relationships (MPC950 Only)
FB_Sel = ‘1’
FB_Sel = ‘0’
Config
fsela
fselb
fselc
fseld
Qa
Qb
Qc
Qd
Qa
Qb
Qc
Qd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4x
4x
4x
4x
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
2x
x
x
x
x
2x
2x
2x
2x
x
x
x
x
2x
2x
x
x
2x
2x
x
x
2x
2x
x
x
2x
2x
x
x
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
2x
x
8x
8x
8x
8x
8x
8x
8x
8x
4x
4x
4x
4x
4x
4x
4x
4x
4x
4x
4x
4x
2x
2x
2x
2x
4x
4x
4x
4x
2x
2x
2x
2x
4x
4x
2x
2x
4x
4x
2x
2x
4x
4x
2x
2x
4x
4x
2x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
4x
2x
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
MPC950
‘1’
‘1’
‘1’
‘0’
‘0’
Qa
fsela
fselb
fselc
fseld
FBsel
Qb
Qc
Qd
16.66MHz
1
1
2
5
MPC950
66.66MHz
‘1’
‘0’
‘0’
‘1’
‘1’
33.33MHz
33.33MHz
33.33MHz
Qb
Qc
Qd
16.66MHz
1
1
2
5
‘0’
‘0’
‘1’
‘1’
‘0’
33.33MHz
33.33MHz
Qa
Qb
Qc
Ext_FB
75MHz
Input Ref
Qd
‘0’
‘0’
‘0’
‘1’
fsela
fselb
fselc
fseld
Qa
Qb
Qc
Ext_FB
75MHz
1
25MHz
Figure 5. “Zero” Delay Buffer
5
80MHz
40MHz
40MHz
Input Ref
Qd
1
100MHz
1
50MHz
2
50MHz
5
25MHz
1
Figure 6. “Zero” Delay Frequency Multiplier
The typical method of measuring the jitter is to accumulate a
large number of cycles, create a histogram of the edge
placements and record peak–to–peak as well as standard
deviations of the jitter. Care must be taken that the measured
edge is the edge immediately following the trigger edge. If
this is not the case the measurement inaccuracy will add
significantly to the measured jitter. The oscilloscope cannot
collect adjacent pulses, rather it collects data from a very
large sample of pulses. It is safe to assume that collecting
pulse information in this mode will produce jitter values
somewhat larger than if consecutive cycles were measured,
therefore, this measurement will represent an upper bound of
cycle–to–cycle jitter. Most likely, this is a conservative
estimate of the cycle–to–cycle jitter.
Jitter Performance of the MPC950/951
With the clock rates of today’s digital systems continuing
to increase more emphasis is being placed on clock
distribution design and management. Among the issues
being addressed is system clock jitter and how that affects
the overall system timing budget. The MPC950/951 was
designed to minimize clock jitter by employing a differential
bipolar PLL as well as incorporating numerous power and
ground pins in the design. The following few paragraphs will
outline the jitter performance of the MPC950/951, illustrate
the measurement limitations and provide guidelines to
minimize the jitter of the device.
The most commonly specified jitter parameter is
cycle–to–cycle jitter. Unfortunately with today’s high
performance measurement equipment there is no way to
measure this parameter for jitter performance in the class
demonstrated by the MPC950/951. As a result different
methods are used which approximate cycle–to–cycle jitter.
TIMING SOLUTIONS
BR1333 — Rev 6
Qc
160MHz
Input Ref
75MHz
5
33.33MHz
Figure 4. Triple Frequency Configuration
75MHz
2
2
Qd
75MHz
1
1
Qb
MPC951
1
1
Qa
fsela
fselb
fselc
fseld
FBsel
33.33MHz
20MHz
MPC951
66.66MHz
MPC950
66.66MHz
Input Ref
fsela
fselb
fselc
fseld
66.66MHz
Figure 2. Dual Frequency Configuration
Figure 3. Dual Frequency Configuration
‘1’
‘0’
‘0’
‘0’
5
66.66MHz
Input Ref
MPC950
Qa
2
Qc
Qd
Input Ref
fsela
fselb
fselc
fseld
FBsel
1
Qb
66.66MHz
Figure 1. Dual Frequency Configuration
‘1’
‘1’
‘1’
‘1’
‘0’
1
Qa
fsela
fselb
fselc
fseld
FBsel
There are two sources of jitter in a PLL based clock driver,
the commonly known random jitter of the PLL and the less
intuitive jitter caused by synchronous, different frequency
outputs switching. For the case where all of the outputs are
7
MOTOROLA
MPC950 MPC951
switching at the same frequency the total jitter is exactly
equal to the PLL jitter. In a device, like the MPC950/951,
where a number of the outputs can be switching
synchronously but at different frequencies a “multi–modal”
jitter distribution can be seen on the highest frequency
outputs. Because the output being monitored is affected by
the activity on the other outputs it is important to consider
what is happening on those other outputs. From Figure 9,
one can see for each rising edge on the higher frequency
signal the activity on the lower frequency signal is not
constant. The activity on the other outputs tends to alter the
internal thresholds of the device such that the placement of
the edge being monitored is displaced in time. Because the
signals are synchronous the relationship is periodic and the
resulting jitter is a compilation of the PLL jitter superimposed
on the displaced edges. When histograms are plotted the
jitter looks like a “multi–modal” distribution as pictured in
Figure 9. Depending on the size of the PLL jitter and the
relative displacement of the edges the “multi–modal”
distribution will appear truly “multi–modal” or simply like a
“fat” Gaussian distribution. Again note that in the case where
all the outputs are switching at the same frequency there is
no edge displacement and the jitter is reduced to that of
the PLL.
1
2
1
Figure 10 graphically represents the PLL jitter of the
MPC950/951. The data was taken for several different output
configurations. By triggering on the lowest frequency output
the PLL jitter can be measured for configurations in which
outputs are switching at different frequencies. As one can
see in the figure the PLL jitter is much less dependent on
output configuration than on internal VCO frequency.
40
35
Conf 1
Conf 2
Conf 3
RMS Jitter (ps)
30
25
20
15
10
5
0
160
240
320
400
480
560
VCO Frequency (MHz)
Conf 1 = All Outputs at the Same Frequency
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
2
Figure 8. RMS PLL Jitter versus VCO Frequency
1
Paek–to–Peak Jitter (ps)
400
2
Conf 2
Conf 3
350
300
250
200
150
160
Peak–to–Peak PLL Jitter
Peak–to–Peak Period Jitter
240
320
400
480
560
VCO Frequency (MHz)
Conf 2 = 4 Outputs at X, 5 Outputs at X/2
Conf 3 = 1 Output at X, 8 Outputs at X/4
1
2
3
1
2
1
2
2
3
Figure 9. Peak–to–Peak Period Jitter versus
VCO Frequency
Two different configurations were chosen to look at the
period displacement caused by the switching outputs.
Configuration 3 is considered worst case as the “trimodal”
distribution (as pictured in Figure 9) represents the largest
spread between distribution peaks. Configuration 2 is
considered a typical configuration with half the outputs at a
high frequency and the remaining outputs at one half the high
frequency. For these cases the peak–to–peak numbers are
reported in Figure 11 as the sigma numbers are useless
because the distributions are not Gaussian. For situations
where the outputs are synchronous and switching at different
frequencies the measurement technique described here is
insufficient to use for establishing guaranteed limits. Other
techniques are currently being investigated to identify a more
accurate and repeatable measurement so that guaranteed
3
Peak–to–Peak PLL Jitter
Peak–to–Peak Period Jitter
Figure 7. PLL Jitter and Edge Displacement
MOTOROLA
8
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
resistance of 10–15Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20KHz. As the noise frequency crosses the
series resonant point of an individual capacitor it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL. It is
recommended that the user start with an 8–10Ω resistor to
avoid potential VCC drop problems and only move to the
higher value resistors when a higher level of attenuation is
shown to be needed.
limits can be provided. The data generated does give a good
indication of the general performance, a performance that in
most cases is well within the requirements of today’s
microprocessors.
Finally from the data there are some general guidelines
that, if followed, will minimize the output jitter of the device.
First and foremost always configure the device such that the
VCO runs as fast as possible. This is by far the most critical
parameter in minimizing jitter. Second keep the reference
frequency as high as possible. More frequent updates at the
phase detector will help to reduce jitter. Note that if there is a
tradeoff between higher reference frequencies and higher
VCO frequency always chose the higher VCO frequency to
minimize jitter. The third guideline may be the most difficult,
and in some cases impossible, to follow. Try to minimize the
number of different frequencies sourced from a single chip.
The fixed edge displacement associated with the switching
noise in most cases nearly doubles the “effective” jitter of a
high speed output.
3.3V
RS=5–15Ω
PLL_VCC
Power Supply Filtering
The MPC950/951 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC950/951 provides
separate power supplies for the output buffers (VCCO) and
the phase–locked loop (VCCA) of the device. The purpose of
this design technique is to try and isolate the high switching
noise digital outputs from the relatively sensitive internal
analog phase–locked loop. In a controlled environment such
as an evaluation board this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
MPC950/951.
Figure 10 illustrates a typical power supply filter scheme.
The MPC950/951 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC950/951. From the data sheet the IVCCA
current (the current sourced through the VCCA pin) is
typically 15mA (20mA maximum), assuming that a minimum
of 3.0V must be maintained on the VCCA pin very little DC
voltage drop can be tolerated when a 3.3V VCC supply is
used. The resistor shown in Figure 10 must have a
TIMING SOLUTIONS
BR1333 — Rev 6
22µF
MPC950/951
0.01µF
VCC
0.01µF
Figure 10. Power Supply Filter
Although the MPC950/951 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Using the On–Board Crystal Oscillator
The MPC950/951 features an on–board crystal oscillator
to allow for seed clock generation as well as final distribution.
The on–board oscillator is completely self contained so that
the only external component required is the crystal. As the
oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the
MPC950/951 as possible to avoid any board level parasitics.
To facilitate co–location surface mount crystals are
recommended, but not required.
9
MOTOROLA
MPC950 MPC951
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC950/951 with just
a minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm lower
than the specified value. For most processor
implementations a few hundred ppm translates into kHz
inaccuracies, a level which does not represent a major issue.
fref
Parameter
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80Ω Max
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
Qn
LPF
+ fVCO
, fVCO + fQn · N · P
m
N fref + fQn ·mN · P
m = 8 (FBsel = ‘1’), 16(FBsel = ‘0’)
P=1
Figure 11. PLL Block Diagram
For the MPC950/951 clock driver, the following will provide
an example of how to determine the crystal frequency
required for a given design.
Given:
Qa = 160MHz
Qb = 80MHz
Qc = 40MHz
Qd = 40MHz
FBSel = ‘0’
fref
+ fQn ·mN · P
From Table 3
fQd = VCO/8 then N = 8 OR fQa = VCO/2 then N = 2
From Figure 11
m = 16 and P = 1
fref
* See accompanying text for series versus parallel resonant
discussion.
· 2 · 1
+ 40 ·168 · 1 + 20MHz OR 160 16
+ 20MHz
Driving Transmission Lines
The MPC950/951 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
The MPC950/951 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback
to the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal. To determine the crystal required to
produce the desired output frequency for an application
which utilizes internal feedback the block diagram of
Figure 11 should be used. The P and the M values for the
MPC950/951 are also included in Figure 11. The M values
can be found in the configuration tables included in this
applications section.
MOTOROLA
÷N
fref
Value
Fundamental AT Cut
÷P
÷m
Table 3. Crystal Specifications
Crystal Cut
VCO
Phase
Detector
10
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
be driven by each output of the MPC950/951 clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 12 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC950/951
clock driver is effectively doubled due to its capability to drive
multiple lines.
3.0
VOLTAGE (V)
2.5
MPC950/951
OUTPUT
BUFFER
IN
7Ω
RS = 43Ω
ZO = 50Ω
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
OutA
0.5
MPC950/951
OUTPUT
BUFFER
IN
RS = 43Ω
ZO = 50Ω
0
OutB0
2
4
7Ω
RS = 43Ω
ZO = 50Ω
8
TIME (nS)
10
12
14
Figure 13. Single versus Dual Waveforms
OutB1
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 14 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 12. Single versus Dual Transmission Lines
The waveform plots of Figure 13 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC950/951 output buffers
is more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC950/951. The output
waveform in Figure 13 shows a step in the waveform, this
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 43Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
MPC950/951
OUTPUT
BUFFER
RS = 36Ω
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
7Ω
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 43Ω || 43Ω
Ro = 7Ω
Figure 14. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
TIMING SOLUTIONS
BR1333 — Rev 6
6
11
MOTOROLA
MPC950 MPC951
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
D
SECTION AE–AE
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
MOTOROLA
M
N
0.20 (0.008)
SEATING
PLANE
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
TIMING SOLUTIONS
BR1333 — Rev 6
MPC950 MPC951
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
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P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
TIMING SOLUTIONS
BR1333 — Rev 6
◊
13
*MPC950/D*
MPC950/D
MOTOROLA
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