ETC2 MR27T6402L 4mâ word ã 16â bit or 8mâ word ã 8â bit p2rom Datasheet

FEDR27T6402L-002-03
Issue Date: Jan. 06, 2009
MR27T6402L
4M–Word × 16–Bit or 8M–Word × 8–Bit
P2ROM
FEATURES
PIN CONFIGURATION (TOP VIEW)
· 4,194,304-word × 16-bit / 8,388,608-word × 8-bit
electrically switchable configuration
· Access time
2.7 V to 3.6 V power supply 90 ns MAX
3.0 V to 3.6 V power supply 70 ns MAX
· Operating current 20 mA MAX (5MHz)
· Standby current
10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR27T6402L-xxxMA
44-pin plastic SOP (SOP44-P-600-1.27-K)
· MR27T6402L-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
· MR27T6402L-xxxLY
48-ball BGA (P-TFBGA48-6.4x10.0-0.80)
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
D0
D8
D1
D9
D2
D10
D3
D11
1
44 A20
2
43 A19
3
42 A8
4
41 A9
5
40 A10
6
39 A11
7
38 A12
8
37 A13
9
36 A14
10
35 A15
11
34 A16
12
33 BYTE#
13
32 VSS
14
31 D15/A–1
15
30 D7
16
29 D14
17
28 D6
18
27 D13
19
26 D5
20
25 D12
21
24 D4
22
23 VCC
44SOP
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory
with minimal effect on the production throughput. The cost
is included in the unit price.
· Custom Marking is available at no additional charge.
· Pin Compatible with Mask ROM and some FLASH
products.
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48 A16
2
47 BYTE#
3
46 VSS
4
45 D15/A–1
5
44 D7
6
43 D14
7
42 D6
8
41 D13
9
40 D5
10
39 D12
11
38 D4
12
37 VCC
13
36 D11
14
35 D3
15
34 D10
16
33 D2
17
32 D9
18
31 D1
19
30 D8
20
29 D0
21
28 OE#
22
27 VSS
23
26 CE#
24
25 A0
48TSOP(Type-I)
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
PIN CONFIGURATION (TOP VIEW): BGA PACKAGE
TOP View - Ball Side Down
1
2
3
4
5
6
A
A3
A7
NC
NC
A9
A13
B
A4
A17
NC
NC
A8
A12
C
A2
A6
A18
A21
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
D0
D2
D5
D7
A16
F
CE#
D8
D10
D12
D14
G
OE#
D9
D11
VCC
D13
H
VSS
D1
D3
D4
D6
BYTE#
D15 / A–1
VSS
48-ball BGA
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
BLOCK DIAGRAM
A–1
OE#
CE
OE
Row Decoder
CE#
BYTE#
Memory Cell Matrix
4M × 16-Bit or 8M × 8-Bit
Column Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
Address Buffer
× 8/× 16 Switch
Multiplexer
Output Buffer
D0
D2
D1
D4
D3
D6
D5
D8
D7
D10
D9
D12
D11
D14
D13
D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A21
D0 to D14
CE#
OE#
BYTE#
VCC
VSS
NC
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
No connect
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
CE#
L
L
OE#
L
L
Output disable
L
H
Standby
H
∗
BYTE#
H
L
VCC
H
2.7 V
to
3.6 V
D0 to D7
DOUT
L
H
D8 to D14
DOUT
Hi–Z
Hi–Z
Hi–Z
L
D15/A–1
L/H
∗
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Output short circuit current
Symbol
Ta
Tstg
VI
VO
VCC
PD
IOS
Condition
—
relative to VSS
Ta = 25°C
—
Value
0 to 70
–55 to 125
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–0.5 to 5
1.0
10
Unit
°C
°C
V
V
V
W
mA
RECOMMENDED OPERATING CONDITIONS
Parameter
VCC power supply voltage
Input “H” level
Input “L” level
Symbol
VCC
VIH
VIL
Condition
VCC = 2.7 to 3.6 V
Min.
2.7
2.2
–0.5∗∗
Typ.
—
—
—
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
VCC+0.5∗
V
0.6
V
Voltage is relative to VSS.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input
BYTE#
Output
Symbol
CIN1
CIN2
COUT
Condition
VI = 0 V
VO = 0 V
Min.
—
—
—
(VCC = 3.0 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
12
pF
—
200
—
12
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Parameter
Input leakage current
Output leakage current
VCC power supply current
(Standby)
VCC power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
ILI
ILO
ICCSC
ICCST
ICCA
VIH
VIL
VOH
VOL
Condition
VI = 0 to VCC
VO = 0 to VCC
CE# = VCC
CE# = VIH
CE# = VIL, OE# = VIH
f=5MHz
—
—
IOH = –1 mA
IOL = 2 mA
(VCC = 2.7 V to 3.6 V, Ta = 0 to 70°C)
Min.
Typ.
Max.
Unit
—
—
10
μA
—
—
10
μA
—
—
10
μA
—
—
1
mA
—
—
20
mA
2.2
–0.5∗∗
2.4
—
—
—
—
—
VCC+0.5∗
0.6
—
0.4
V
V
V
V
Voltage is relative to VSS.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
AC CHARACTERISTICS
Parameter
Address cycle time
Address access time
CE# access time
OE# access time
Output disable time
Output hold time
Parameter
Address cycle time
Address access time
CE# access time
OE# access time
Output disable time
Output hold time
Symbol
tC
tACC
tCE
tOE
tCHZ
tOHZ
tOH
Condition
—
CE# = OE# = VIL
OE# = VIL
CE# = VIL
OE# = VIL
CE# = VIL
CE# = OE# = VIL
(VCC = 2.7 V to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
90
—
ns
—
90
ns
—
90
ns
—
30
ns
0
30
ns
0
25
ns
0
—
ns
Symbol
tC
tACC
tCE
tOE
tCHZ
tOHZ
tOH
Condition
—
CE# = OE# = VIL
OE# = VIL
CE# = VIL
OE# = VIL
CE# = VIL
CE# = OE# = VIL
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
70
—
ns
—
70
ns
—
70
ns
—
30
ns
0
20
ns
0
20
ns
0
—
ns
Measurement conditions
Input signal level ................................... 0 V / Vcc
Input timing reference level................... 1/2Vcc
Output load ........................................... 50 pF
Output timing reference level ................ 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
TIMING CHART (READ CYCLE)
16-BIT READ MODE (BYTE# = VIH)
tC
tC
A0 to A21
tOH
tACC
tCE
CE#
tOE
tCHZ
tOH
OE#
tOHZ
tACC
D0 to D15
Valid Data
Hi-Z
Valid Data
Hi-Z
8-BIT READ MODE (BYTE# = VIL)
tC
tC
A-1 to A21
tOH
tACC
tCE
CE#
tOE
tCHZ
tOH
OE#
tOHZ
tACC
D0 to D7
Hi-Z
Valid Data
Valid Data
Hi-Z
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FEDR27T6402L-002-03
MR27T6402L / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
8/12
FEDR27T6402L-002-03
MR27T6402L / P2ROM
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
9/12
FEDR27T6402L-002-03
MR27T6402L / P2ROM
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
10/12
FEDR27T6402L-002-03
MR27T6402L / P2ROM
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
FEDR27T6402L-02-01
May. 9, 2005
–
–
1,5
1,5
5
5
–
–
1
1,2,10
FEDR27T6402L-002-02
FEDR27T6402L-002-03
Oct. 30, 2008
Jan. 6, 2009
Description
Final edition 1
Change tC, tACC, tCE (3.0V to 3.6V )to
70ns
Changed Input signal level from “0V/3V” to
“0V/Vcc”.
Changed company logo and name to OKI
SEMICONDUCTOR
Add MR27T6402L-xxxLY (BGA package)
11/12
FEDR27T6402L-002-03
MR27T6402L / P2ROM
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