MOSEL VITELIC MS7200L/7201AL/7202AL MS7200L/7201AL/7202AL 256 x 9, 512 x 9, 1K x 9 CMOS FIFO Features Descriptions ■ First-In/First-Out static RAM based dual port memory ■ Three densities in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags ■ Direct replacement for industry standard Mostek and IDT ■ Ultra high-speed 30 MHz FIFOs available with 33 ns cycle times. ■ Fully expandable in both depth and width ■ Simultaneous and asynchronous read and write ■ Auto retransmit capability ■ TTL compatible interface, single 5V ± 10% power supply ■ Available in 28 pin 300 mil and 600 mil plastic DIP, 32 Pin PLCC and 330 mil SOG The MS7200L/7201AL/7202AL are dual-port static RAM based CMOS First-In/First-Out (FIFO) memories organized in nine-bit wide words. The devices are configured so that data is read out in the same sequential order that it was written in. Additional expansion logic is provided to allow for unlimited expansion of both word size and depth. The dual-port RAM array is internally sequenced by independent Read and Write pointers with no external addressing needed. Read and write operations are fully asynchronous and may occur simultaneously, even with the device operating at full speed. Status flags are provided for full, empty, and half-full conditions to eliminate data underflow and overflow. The x9 architecture provides an additional bit which may be used as a parity or control bit. In addition, the devices offer a retransmit capability which resets the Read pointer and allows for retransmission from the beginning of the data. The MS7200L/7201AL/7202AL are available in a range of frequencies from 10 to 30 MHz (33 - 100 ns cycle times). A low power version with a 500µA power down supply current is available. They are manufactured on Mosel-Vitelic’s high performance 1.2µ CMOS process and operate from a single 5V power supply. Pin Configurations 28-PIN PDIP W 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 D0 6 XI 7 FF 8 Q0 9 300 mil 600 mil DIP & 330 mil SOG 23 FL / RT 22 RS 21 EF 20 XO / HF Block Diagram DATA INPUTS (Q0-Q8) Q1 10 19 Q7 Q2 11 18 Q6 Q3 12 17 Q5 Q8 13 16 Q4 GND 14 15 R WRITE CONTROL W RAM ARRAY 256x9 512x9 1Kx9 WRITE POINTER READ POINTER D2 D1 D0 XI FF Q0 Q1 NC Q2 2 THREE STATE BUFFERS D5 W NC 3 D4 D8 4 5 8 7 8 9 10 11 14 13 VCC D3 32-PIN PLCC 1 32 31 30 DATA OUTPUTS (Q0-Q8) 29 28 27 26 25 24 23 22 21 32 Pin PLCC Top View D6 D7 NC FL / RT RS EF XO / HF Q7 Q6 READ CONTROL R RESET LOGIC FLAG LOGIC EF HF FF Q5 R Q4 NC VSS Q8 Q3 14 15 16 17 18 19 20 EXPANSION LOGIC XI MS7200L/01AL/02AL Rev. 1.0 January 1995 1 XO RS FL / RT MS7200L/7201AL/7202AL MOSEL VITELIC Signal Descriptions INPUTS: Data In (D 0 - D 8) These data inputs accept 9-bit data words for sequential storage in the FIFO during write operations. First Load/Retransmit (FL/RT) This is a dual-purpose input. In single device mode (when Expansion In (XI) is grounded) this pin acts as the retransmit input. A LOW pulse on this will reset the read pointer to the first memory location of the FIFO. The write pointer is unaffected. Both the read enable (R) and write enable (W) inputs must remain HIGH during the retransmit cycle. In Depth Expansion mode this pin acts as a first load indicator. It must be grounded on the first device in the chain to indicate which device is the first to receive data. CONTROLS: Reset (RS) The reset input is active LOW. When asserted, the device is asynchronously reset, and both the read and write internal pointers are set to the first location in the FIFO. A Reset is required after power-up before a write operation can occur. Both Read Enable (R) and Write Enable (W) must be HIGH during Reset. OUTPUTS: Data Output (Q0 - Q 8) A 9 bit data word from the FIFO is output on these pins during read operations. They are in the high impedance state whenever R is HIGH. Read Enable (R) The read enable input is active LOW. As long as the Empty Flag (EF) is not set, the read cycle is started on the falling edge of this signal. The data is accessed on a First-In/First-Out basis, independent of any write activity, and is presented on the Data Output pins (Q0 - Q8). When R goes HIGH the Data Output pins return to the high impedance state, and the read pointer is incremented. When the FIFO is empty or all of the data has been read, the Empty Flag will be set and further read operations are inhibited until a valid write operation has been performed. Empty Flag (EF) This output is active LOW. When all of the data has been read from the FIFO (defined as when the Read pointer is one location behind the Write pointer) this flag will be set. The Data Output pins will be forced into the high impedance state, and all further read operations will be inhibited until a valid write operation has been performed (which will reset this flag). Write Enable (W) The write enable input is active LOW. As long as the Full Flag (FF) is not set, the write cycle is started on the falling edge of this signal. The data present on the Data Input pins (D0 - D8) is stored sequentially, independent of any read activity. When W goes HIGH the write cycle is terminated and the write pointer is incremented. When the maximum capacity of the FIFO has been reached the Full Flag will be set, and further write operations are inhibited until a valid read operation has been performed. Full Flag (FF) This output is active LOW. To prevent data overflow, when the maximum capacity of the FIFO has been reached (defined as when the Write pointer is one location behind the Read pointer) this flag will be set. All further write operations will be inhibited until a valid read operation has been performed (which will reset this flag). Expansion Out/Half Full Flag (XO/HF) This dual-purpose output is active LOW. In single device mode (when Expansion In (XI) is grounded) this flag will be set at the falling edge of the next write operation after the FIFO has reached one-half of its maximum capacity. This flag will remain set as long as the difference between the read pointer and the write pointer is greater than one-half of the maximum capacity of the FIFO. In Depth Expansion mode, this output is connected to the Expansion In Input of the next device in the chain. The Expansion Out pin provides a pulse to the next device in the chain when the last memory location has been reached. Expansion In (XI) This input pin serves two purposes. When grounded, it indicates that the device is being operated in the single device mode. In Depth Expansion mode, this pin is connected to the Expansion Out Output (XO) of the previous device. MS7200L/01AL/02AL Rev. 1.0 January 1995 2 MS7200L/7201AL/7202AL MOSEL VITELIC Absolute Maximum Ratings(1) Symbol Condition Unit Range Ambient Temperature Vcc Commercial 0°C to + 70°C 5V ± 10% VTERM Terminal Voltage with Repect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -10 to +125 °C TSTG Storage Temperature -60 to +150 °C 1.0 W Symbol mA C IN CQ PT Power Dissipation IOUT 1. Parameter Operating Range DC Output Current 20 Capacitance(1) TA = 25°C, f = 1.0MHz Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Condition Max. Unit Input Capacitance VIN = 0V 4 pF Output Capacitance VDQ = 0V 6 pF DC Electrical Characteristics (over the commercial operating range) Test Parameter V IL V IH I IL IOL V OL VOH ICC1 ICC2 ICCSB(S) ICCSB(L) Parameter MS7200L/7201AL MS7200L/7201AL 7202AL 7202AL (-25, -35) (-50, -80) Min. Typ. Max. Min. Typ. Max. Units Test Conditions Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage V CC = Max, V IN = 0Vto V CC V CC = Max, R= VIH, VIN = 0V toVCC V CC = Min, IOL = 8mA 2.0 -1 -10 - Output High Voltage V CC = Min, IOH = -2mA 2.4 - Operating Power Supply Current V CC = Max, II/O = 0mA, F = Fm ax V CC = Max, R = W = RS = FL / RT = Average Standby Current V IH, I I/O = 0mA V CC = Max, R = W = RS = FL / RT > Power Down Power Supply V CC-0.2V, V IN > V CC-0.2V or V IN < Current (Standard Power) 0.2V V CC = Max, R = W = RS = FL / RT > Power Down Power Supply V CC-0.2V, V IN > V CC-0.2V or V IN < Current (Low Power) 0.2V - 0.8 1 10 0.4 2.0 -1 -10 - - - 2.4 - - V - 125 - 50 80 mA - 15 - 5 8 mA - - 5 - - 5 mA - - 500 - - 500 µA - - - 0.8 1 10 0.4 V V µA µA V Truth Tables Single Device Configuration/Width Expansion Mode Mode Inputs Internal Status Outputs RS RT XI Read Pointer Write Pointer EF FF Reset 0 X 0 Location Zero Location Zero 0 1 1 Retransmit 1 0 0 Location Zero Unchanged X X X 0 Increment (1) Increment (1) X X X Read/Write 1 1 NOTE: 1. Pointer will increment if flag is high. HF Depth Expansion/Compound Expansion Mode Mode Inputs Internal Status Outputs RS FL XI Read Pointer Write Pointer EF FF Reset-First Device 0 0 (1) Location Zero Location Zero 0 1 Reset all Other Devices 0 1 (1) Location Zero Unchanged 0 1 Read/Write 1 X (1) X X X X NOTE: 1. XI is connected to XO of previous device. See Figure 15. RS = Reset Input. FL/RT = First Load/Retransmit. EF = Empty Flag Output. FF Full Flag Output. XI = Expansion Input. MS7200L/01AL/02AL Rev. 1.0 January 1995 3 MS7200L/7201AL/7202AL MOSEL VITELIC AC Electrical Characteristics (over the commercial operating range) Parameter Name Parameter ƒS Shift Frequency Read Cycle tRC Read Cycle Time tA Access Time tRPW Read Pulse Width tRR Read Recovery Time tRLZ (2) Read Pulse Low to Data Bus at Low Z tRHZ (2,3) Read Pulse High to Data Bus at High Z tDV Data Valid from Read Pulse High Write Cycle tWC Write Cycle Time tWPW(1) Write Pulse Width tWR Write Recovery Time tDS Data Setup Time tDH Data Hold Time tWLZ(2,3) Write Pulse High to Data Bus at Low Z Flag Timing tREF Read Low to Empty Flag Low tRHF Read High to Half Full Flag High tRFF Read High to Full Flag High tWEF Write High to Empty Flag High tWFF Write Low to Full Flag Low tWHF Write Low to Half Full Flag Low tRPE Read Pulse Width After EF High tWPF Write Pulse Width After FF High Reset Timing tRSC Reset Cycle Time tRS (1) Reset Pulse Width tRSS Reset Set Up Time tRSR Reset Recovery Time tEFL Reset to Empty Flag Low tHFH Reset to Half Full Flag High tFFH Reset to Full Flag High Retransmit Timing tRTC Retransmit Cycle Time tRT(1) Retransmit Pulse Width tRTS Retransmit Set up Time tRTR Retransmit Recovery Time Expansion Timing tXOL Read/Write to XO Low tXOH Read/Write to XO High tXI XI Pulse Width tXIS XI Set up Time tXIR XI Recovery Time MS7200L-25 MS7200L-35 MS7200L-50 MS7200L-80 MS7201AL-25 MS7201AL-35 MS7201AL-50 MS7201AL-80 MS7202AL-25 MS7202AL-35 MS7202AL-50 MS7202AL-80 Min. Max. Min. Max. Min. Max. Min. Max. -30 -22.2 -15 -10 Units MHz 33 -25 8 5 -5 -25 ---18 -- 45 -35 10 5 -5 -35 ---20 -- 65 -50 15 10 -5 -50 ---30 -- 100 -80 20 10 -5 -80 ---30 -- ns ns ns ns ns ns ns 33 25 8 15 0 5 ------- 45 35 10 18 0 10 ------- 65 50 15 30 5 15 ------- 100 80 20 40 10 20 ------- ns ns ns ns ns ns -- 25 -- 30 -- 45 -- 60 ns -----25 25 33 25 25 25 33 --- -----35 35 45 30 30 30 45 --- -----50 50 65 45 45 45 65 --- -----80 80 100 60 60 60 100 --- ns ns ns ns ns ns ns 33 25 25 8 ---- ----33 33 33 45 35 35 10 ---- ----45 45 45 65 50 50 15 ---- ----65 65 65 100 80 80 20 ---- ----100 100 100 ns ns ns ns ns ns ns 33 25 25 8 ----- 45 35 35 10 ----- 65 50 50 15 ----- 100 80 80 20 ----- ns ns ns ns --25 15 8 25 25 ---- --35 15 10 35 35 ---- --50 15 10 50 50 ---- --80 15 10 80 80 ---- ns ns ns ns ns NOTES: 1. Pulse widths less than minimum value are not allowed. 2. Values guaranteed by design, not currently tested. 3. Only applies to read data flow-through mode. MS7200L/01AL/02AL Rev. 1.0 January 1995 4 MS7200L/7201AL/7202AL MOSEL VITELIC AC Test Conditions Key to Switching Waveforms Input Pulse Levels 0V~ 3.0V Input Rise and Fall Times 5 ns Timing Reference Level 1.5V WAVEFORM AC Test Loads and Waveforms R1 480Ω 5V OUTPUT OUTPUT R2 255Ω R2 255Ω 5pF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE Figure 1a Figure 1b Equivalent to: THEVENIN EQUIVALENT 167 Ω OUTPUT 1.73V ALL INPUT PULSES 3.0V GND 5 ns 90% 10% 90% 10% 5 ns Figure 2 Timing Waveforms RESET t RSC t RS RS t RSS W t EFL t RSR EF HF, FF OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE "OFF" STATE R1 480Ω 5V 30pF INPUTS t HFH , t FFH t RSS R ASYNCHRONOUS READ OPERATION t RC t RPW t RR tA R t RLZ Q0-Q8 tA t DV t RHZ READ DATA VALID MS7200L/01AL/02AL Rev. 1.0 January 1995 5 READ DATA VALID MS7200L/7201AL/7202AL MOSEL VITELIC Timing Waveforms ASYNCHRONOUS WRITE OPERATION t WC t WPW t WR W t DS D0-D8 t DH WRITE DATA VALID WRITE DATA VALID RETRANSMIT t RTC FL / RT t RT t RTS R, W t RTR EMPTY FLAG TIMING W t WEF EF t RPE R t RPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH MS7200L/01AL/02AL Rev. 1.0 January 1995 6 MS7200L/7201AL/7202AL MOSEL VITELIC Timing Waveforms FULL FLAG TIMING R t RFF FF t WPF W t WPF : EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH HALF-FULL FLAG TIMING HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS W t RHF R t WHF HF FULL FLAG FROM LAST WRITE TO FIRST READ LAST WRITE FIRST READ R W t WFF tRFF FF MS7200L/01AL/02AL Rev. 1.0 January 1995 7 ADDITIONAL FIRST WRITE READS MS7200L/7201AL/7202AL MOSEL VITELIC Timing Waveforms EMPTY FLAG FROM LAST READ TO FIRST WRITE LAST READ FIRST WRITE ADDITIONAL WRITES FIRST READ W R t REF tWEF EF tA DATA OUT VALID VALID READ DATA FLOW-THROUGH MODE DATA IN W tRPE R EF tWEF tWLZ DATA OUT tREF tA DATA OUT VALID WRITE DATA FLOW-THROUGH MODE R tWPF W tRFF FF t WFF tDH DATA IN VALID DATA IN tDS tA DATA OUT DATA OUT VALID MS7200L/01AL/02AL Rev. 1.0 January 1995 8 MS7200L/7201AL/7202AL MOSEL VITELIC Timing Waveforms EXPANSION IN t XI t XIR XI t XIS WRITE TO FIRST PHYSICAL LOCATION W t XIS R READ FROM FIRST PHYSICAL LOCATION EXPANSION OUT W WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION R t XOL t XOL t XOH t XOH XO Operating Modes: Single Device Mode (Note: The7201A Lis used as example - these figures apply to all three devices, MS7200L/ 7201AL/7202AL When one MS7201AL is used standalone in Single Device Mode, the Expansion In (XI) control input pin must be grounded. See Figure 3. HALF FULL FLAG (HF) (W) (D0-D8) (FF) (RS) WRITE READ DATA IN FULL FLAG DATA OUT MS 7201A RESET EMPTY FLAG RETRANSMIT EXPANSION IN XI Figure 3. Single Device Mode MS7200L/01AL/02AL Rev. 1.0 January 1995 9 (R) (Q0-Q8) (EF) (RT) MS7200L/7201AL/7202AL MOSEL VITELIC Width Expansion Mode Word width may be expanded by connecting the corresponding control input signals of multiple devices together. The EMPTY, HALF FULL and FULL FLAGS (EE, HF and FF) can be detected by any particular device. Figure 4 shows an 18 bit wide configuration using two devices. They may be configured to any word width in this manner. HALF FULL FLAG (HF) 9 DATA IN (HF) HALF FULL FLAG (D) MS 7201A 9 18 (W) (FF) WRITE READ BITS 0-8 FULL FLAG BITS 9-17 (RS) (R) (EF) EMPTY FLAG RESET RETRANSMIT (RT) 18 MS 7201A XI 9 (Q) 9 DATA OUT XI Figure 4. Width Expansion Mode NOTES: Flag detection is accomplished by monitoring the EF, HF and EF pins on the device used in the Width Expansion Mode. Do not connect output control signals together. Depth Expansion (Daisy Chain) Mode 3. The EXPANSION OUT (XO) pin of each device must be connected to the EXPANSION IN (XI) pin of the next device as shown in Figure 5. 4. External logic is required to generate a common FULL FLAG (FF) and EMPTY FLAG (EF) signal by ORing all of the FFs together and ORing all of the EFs together. 5. The RETRANSMIT (RT) fuction and HALF FULL FLAG (HF) are not available in Daisy Chain Mode. Word depths may be expanded in multiples of 512 words by Daisy Chaining the devices together as follows: 1. The FIRST LOAD (FL) control signal of the first device must be grounded. This FIFO represents word 1-512. 2. All other devices in the Daisy Chain must have the FIRST LOAD (FL) control signal tied to VCC in the inactive-high state. XO W FF 9 9 D MS 7201 R EF 9 WORDS 10251536 XI Q FL VCC XO FF FULL 9 MS 7201 EF EMPTY WORDS 15131024 XI FL XO FF 9 MS 7201 EF WORDS 1-512 FL RS XI Figure 5. Diagram of a 1536 x 9 FIFO in Depth Expansion Mode MS7200L/01AL/02AL Rev. 1.0 January 1995 10 MS7200L/7201AL/7202AL MOSEL VITELIC Bidirectional Mode Data buffering between two systems can be achieved by pairing two FIFO arrays as shown in Figure 6. This allows each system to READ and WRITE shared data. The FULL FLAG (FF) must be monitored on the FIFO where WRITE ENABLE (W) is used and the EMPTY FLAG (EF) must be monitored on the FIFO where READ ENABLE (R) is used. Both Width Expansion and Depth Expansion Modes may be used in combination with Bidirectional Mode. Compound Expansion Mode: Both Width Expansion Mode and Depth Expansion (Daisy Chain) Mode can be used together to configure a large FIFO array (See Figure 4 and 5). WA RB FFA EFB HFB MS7201 DA 0-8 QB 0-8 SYSTEM A SYSTEM B QA 0-8 MS7201 DB RA WB EFA HFA FFB Figure 6. BiDirectional FIFO Mode Ordering Information Speed (ns) 25 25 25 25 35 35 35 35 50 50 50 50 80 80 80 80 Ordering Part Number MS7201AL-25PC MS7202AL-25PC MS7200-25NC MS7201AL-25NC MS7202AL-25NC MS7200-25JC MS7201AL-25JC MS7202AL-25JC MS7200-25FC MS7201AL-25FC MS7202AL-25FC MS7201AL-35PC MS7202AL-35PC MS7200-35NC MS7201AL-35NC MS7202AL-35NC MS7200-35JC MS7201AL-35JC MS7202AL-35JC MS7200-35FC MS7201AL-35FC MS7202AL-35FC MS7201AL-50PC MS7202AL-50PC MS7200-50NC MS7201AL-50NC MS7202AL-50NC MS7200-50JC MS7201AL-50JC MS7202AL-50JC MS7200-50FC MS7201AL-50FC MS7202AL-50FC MS7201AL-80PC MS7202AL-80PC MS7200-80NC MS7201AL-80NC MS7202AL-80NC MS7200-80JC MS7201AL-80JC MS7202AL-80JC MS7200-80FC MS7201AL-80FC MS7202AL-80FC MS7200L/01AL/02AL Rev. 1.0 January 1995 11 Package 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil 28 Pin Plastic DIP - 600 mil 28 Pin Plastic DIP - 300 mil 32 Pin Plastic PLCC 28 Pin Small Outline - 330 mil Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C