OKI MSM13R0000 Universal serial bus controller 0.5um technology mega macrofunction Datasheet

Technical Brief
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W712
Universal Serial Bus Controller
0.5µ m Technology
Mega Macrofunction
January 1997
■ ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Contents
Description................................................................................................................................................................ 1
Features ..................................................................................................................................................................... 1
Signal Descriptions .................................................................................................................................................. 4
Functional Description ............................................................................................................................................ 7
Protocol Engine .................................................................................................................................................. 7
DPLL..................................................................................................................................................................... 7
Timer .................................................................................................................................................................... 7
Status/Control ................................................................................................................................................... 7
FIFO Control ...................................................................................................................................................... 7
Application Interface ......................................................................................................................................... 8
Frame Timer Synthesizer................................................................................................................................... 8
Remote Wakeup.................................................................................................................................................. 8
USB Transfers ..................................................................................................................................................... 8
USB Interface ...................................................................................................................................................... 8
Glossary ..................................................................................................................................................................... 9
Appendix ................................................................................................................................................................. 10
Oki Semiconductor
W712 USB Device Controller
0.5µm Technology Mega Macrofunction
DESCRIPTION
The Universal Serial Bus (USB) Device Controller Mega Macrofunction is a featured element in Oki’s
0.5µm Sea of Gates (SOG) and Customer Structured Array (CSA) families. Oki's USB mega macrofunction
provides a USB interface, control/status block, FIFO control, and application interface in two highly integrated submodules for system design interfaces based on the USB protocol. The submodule partitioning
allows custom configurations to be easily developed. The USB mega macrofunction connects an industry
standard USB interface with a microprocessor-style parallel application interface. This straightforward
interface permits easy integration of the USB mega macrofunction to the target application. Using Oki’s
USB mega macrofunction, designers can reduce development time, risk, and introduce their USB based
products to market faster. Oki’s W712 USB Device Controller mega macrofunction provides a complete
USB device interface solution and is fully compliant with the Universal Serial Bus 1.0 specification. For
more details on the Universal Serial Bus 1.0 specification, refer to www.usb.org.
FEATURES
• USB 1.0 compliant
• Full-speed (12 Mb/sec) and low-speed (1.5 Mb/sec)
support
• Microprocessor-style parallel application interface
• Supports isochronous, control, interrupt and bulk
transfers
• Supports four transmit FIFO’s
- Three 64 byte
- One 2 Kbyte (2-level)
• Supports four receive FIFO’s
- Three 64 byte
- One 2 Kbyte (2-level)
• Supports one control endpoint and six
additional endpoint addresses
• Expandable up to 32 endpoint addresses
• Customizable to specific application
requirements
Supported ASIC Families
Family Name
Family Type
MSM13R0000
Sea of Gates
MSM98R000
Customer Structured Array
Oki Semiconductor
1
■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Recommended Operating Conditions (VSS = 0 V)
Parameter
Symbol
Min.
Typ.
Max
Unit
Power supply voltage
VDD
2.7
3.3
3.6
V
Operating temperature
Tj
-40
+25
+85
°C
Mega Macrofunction Characteristics
Mega Macrofunction
W712
Description
Logic Gate Count
Logic Pin Count
USB Device Controller
15797
139
W712
USB Interface
Application Interface
usb_dpin
usb_dmin
usb_rxd
usb_dpout
usb_dmout
usb_txenb
full_spden
sel_ext_pll
sys_clock
sys_reset
testmode
mwr_rdb
[7:0]ma
[7:0]md
mrdyb
[7:0]pd
[3:0]pkt_rdy
setup_rdy
setup_rdy2
iso_err
usb_reset
validsof
validin
validout
[7:0]trx_out_data
[7:0]rcv_out_data
[7:0]trx_in_data
[2:0]trx_sel
[8:0]trx_wr_ptr
[8:0]trx_rd_ptr
[6:0]trx_wrb
[7:0]rcv_in_data
[2:0]rcv_sel
[8:0]rcv_wr_ptr
[8:0]rcv_rd_ptr
[6:0]rcv_wrb
osc_clk
usb_clk_ext
usb_rxd_out
Figure 1. Logic Symbol
2
Oki Semiconductor
FIFO Interface
DPLL Interface
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ W712 USB Device Controller ■
W712
Z712a
Clock
W712b
DPLL
Status/Control
Application
Interface
To
Application
Module
Protocol Engine
To USB Transceiver
FIFO Control
To FIFO’s
(data path)
To FIFO’s
(control)
To FIFO’s
(data path)
Figure 2. W712 Block Diagram
ASIC
W712 Mega Macrofunction
Clock
DPLL
Status/
Control
Optional
External
DPLL
Application
Interface
Application
Module
External
Module I/O
Protocol
Engine
USB Cable
USB
Transceiver
FIFO
Control
Data Path
FIFO(s)/
Data Mux(s)
Data Path
Figure 3. Example USB Mega Macrofunction Application
Oki Semiconductor
3
■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
SIGNAL DESCRIPTIONS
USB Interface
Signal
Type
Assertion
Description
USB Data Plus In. This input and the usb_dmin input are the received single ended data
from the USB transceiver. The table below shows values and results for these signals.
usb_dpin
Input
—
usb_dmin
Input
—
usb_dpin
usb_dmin
0
0
Result
SE0
0
1
Logic “0”
1
0
Logic “1”
1
1
Undefined
USB Data Minus In. This input and the usb_dpin input are the received single ended data
from the USB transceiver. See the table for the usb_dpin description, above, for values
and results of these signals.
USB Data Plus Out. This output and the usb_dmout signal come from the USB transmit
engine and drive the differential output buffers. The table below shows values and results
for these signals.
usb_dpout
Output
—
0
Result
SE0
0
1
Logic “0”
1
0
Logic “1”
1
1
Undefined
—
USB Data Minus Out. This output and the usb_dpout signal come from the USB transmit
engine and drive the differential output buffers. See the signal description for usb_dpout,
above, for a description of signal values and results.
Input
—
USB Differential Received Data. This input comes from the USB differential receiver, and
connects to the W712 mega macrofunction.
Output
LOW
USB 3-State Output Enable. This signal connects to the transceiver EB input through an
inverter gate. When the W712 mega macrofunction asserts this signal LOW, the transceiver transmits data on the USB bus. See Appendix for the USB transceiver Data Sheets.
usb_txenb
4
usb_dmout
0
Output
usb_dmout
usb_rxd
usb_dpout
Oki Semiconductor
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ W712 USB Device Controller ■
Application Interface
Signal
sys_clock
sys_reset
Type
Assertion
Description
Input
—
Clock. Attach a 12-MHz clock signal to this input for full-speed operation and 1.5 MHz for
low-speed operation.
Input
HIGH
W712 Reset. Asserting this signal HIGH resets the W712 mega macrofunction. The application module is required to assert this signal at power-on.
Input
—
Write/Read Select. When external application logic asserts this signal HIGH, the application is in WRITE mode. When asserted LOW, the application is in READ mode. External
application logic asserts this signal HIGH when writing data to the transmit FIFOs or to the
register files. External application logic asserts this signal LOW when reading data from
the receiving FIFOs or from the register files. The register files contain information describing the function and transaction status.
Output
HIGH
Input
—
Address Bus. These eight inputs receive the address of the register files in the USB device
controller.
Input
—
Input Data Bus. These eight inputs receive the data to be stored in the register files or
transmit FIFOs.
Input
LOW
Data Strobe. When asserted LOW and in WRITE mode, the data on the [7:0]md signal
lines are valid for writing. When asserted LOW and in READ mode, the data on the [7:0]pd
signals are valid for reading.
Output
—
Output Data Bus. These eight outputs transmit data received from either the register files
or the receive FIFOs.
Output
HIGH
Packet Ready. When the W712 asserts this signal, it indicates that one of the four receive
FIFOs contains valid data. The application reads the data through the [7:0]pd bus.
Input
—
USB Full Speed Enable. The application module sets this pin to “1” to select full-speed
operation and “0” to select low-speed operation.
Output
HIGH
Setup Ready. Asserting this signal HIGH indicates an 8-byte SETUP data has been received from the USB bus.
Output
HIGH
Isochronous Error. Used for loopback testing or to indicate isochronous data has been received with DATA1 PID.
Output
HIGH
Valid SOF. This signal is asserted for two bit times, asynchronous to sys_clock, and indicates a valid SOF token is received when asserted HIGH.
Input
HIGH
Select External PLL. Asserting this signal HIGH selects the external PLL option.
Output
HIGH
Second Setup Ready. Asserting this signal HIGH indicates a new 8-byte SETUP DATA has
been received, while internally the device controller still sees the “setup_rdy” signal asserted. This signal will be asserted for two bit times, asynchronous to sys_clock.
Input
HIGH
Testmode. Asserting this signal invokes a loopback test mode.
Output
HIGH
Valid IN. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid IN
token is received when asserted HIGH.
Output
HIGH
Valid OUT. Asserted for two bit times, asynchronous to sys_clock, and indicates a valid
OUT token is received when asserted HIGH.
mwr_rdb
usb_reset
[7:0]ma
[7:0]md
mrdyb
[7:0]pd
[3:0]pkt_rdy
full_spden
setup_rdy
iso_err
validsof
sel_ext_pll
setup_rdy2
testmode
validin
validout
USB Reset. This is the reset signal from the USB device controller.
Oki Semiconductor
5
■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
FIFO Interface
Signal
[7:0]trx_out_data
[7:0]rcv_out_data
Type
Assertion
Description
Input
—
Transmit FIFO(s} data output. Output data from the transmission RAM selected for reading.
Input
—
Receive FIFO(s) data output. Output data from the receiving RAM selected for reading.
[7:0]trx_in_data
Output
—
Transmit FIFO(s) data input. Input data to all transmission RAMs.
[2:0]trx_sel
Output
HIGH
[8:0]trx_wr_ptr
Output
—
[8:0]trx_rd_ptr
Output
—
[6:0]trx_wrb
Output
LOW
Transmit FIFO(s) select. Selects one of the seven transmission RAMs for reading.
Transmit FIFO(s) write pointer. Write address to all transmission RAMs.
Transmit FIFO(s) read pointer. Read address to all transmission RAMs.
Transmit FIFO(s) write strobe. Write enable. One bit per transmission RAM.
[7:0]rcv_in_data
Output
—
[2:0]rcv_sel
Output
HIGH
Receive FIFO(s) data input. Input data to all receiving RAMs.
[8:0]rcv_wr_ptr
Output
—
Receive FIFO(s) write pointer. Write address to all receiving RAMs.
[8:0]rcv_rd_ptr
Output
—
Receive FIFO(s) read pointer. Read address to all receiving RAMs.
[6:0]rcv_wrb
Output
LOW
Type
Assertion
Description
Input
–
Oscillator Clock. Attach a 48 MHz clock signal for full-speed operation or a 6 MHz clock
signal for low-speed operation.
Input
–
USB Clock External. This is the output clock signal from an external DPLL. This clock
should run at 12 MHz for full-speed operation or 1.5 MHz for low-speed operation. If an
external DPLL is not used, this pin should be connected to VDD or GND.
Output
–
Synchronized USB Differential Received Data. This signal comes from the USB differential receiver and is synchronized with the oscillator input. This signal connects to the external DPLL if it is used.
Receive FIFO(s) select. Selects one of the seven receiving RAMs for reading.
Receive FIFO(s) write strobe. Write enable. One bit per receiving RAM.
DPLL Interface
Signal
osc_clk
usb_clk_ext
usb_rxd_out
6
Oki Semiconductor
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ W712 USB Device Controller ■
FUNCTIONAL DESCRIPTION
The W712 controller consists of two submodules, the Z712a hard macro, and the W712b soft macro, each
containing multiple function blocks. The Z712a includes the Protocol Engine, DPLL, and Timer Blocks.
The W712b includes the Status/Control, FIFO Control, Application Interface, Frame Timer Synthesizer,
and remote wakeup blocks.
Protocol Engine
The Protocol Engine handles the USB communication protocol. It performs packet sequencing, signal
generation/detection, CRC generation/checking, NRZI data encoding, bit-stuffing and packet ID (PID)
generation/decoding.
DPLL
The Digital Phase Locked Loop extracts the clock and data from the USB differential received data.
Timer
The Timer block monitors idle time on the USB bus.
Status/Control
The Status/Control block uses transfer type and FIFO state information to manage the reception and
transmission of USB data. It monitors the transaction status and communicates control events to the application via the Application Interface.
FIFO Control
The FIFO control block manages all FIFO operations for transmitting and receiving USB data sets. The
W712 supports eight FIFOs (four transmit and four receive). They can be configured as described in the
table below.
FIFO Configuration
FIFO Type
Endpoint Address
Programmable
Function
Transmit
0
64 bytes
Control Transfers
Transmit
5
64 bytes
Interrupt and Bulk Transfers
Transmit
6
64 bytes
Interrupt and Bulk Transfers
Transmit
7
2 Kbytes
Isochronous, Interrupt, and Bulk Transfers
Receive
0
64 bytes
Control Transfers
Receive
1
64 bytes
Bulk Transfers
Receive
2
64 bytes
Bulk Transfers
Receive
3
2 Kbytes
Isochronous and Bulk Transfers
Endpoints 3 and 7 are 2-level FIFOs which support up to two separate data sets of variable sizes. All FIFOs
have flags that detect a full or empty FIFO and have the capability of re-transmitting or re-receiving the
current data set.
Oki Semiconductor
7
■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Application Interface
The Application Interface uses an i486-like bus to interface between the customer’s module and the W712.
By using an i486-like bus protocol, the W712 can be easily integrated into any customer-designed module.
The integration is limited only by the available gates and I/O pins in the array. The Customer Application
Module may have its own external I/O, which do not interface with the W712. All application interface
signals are unidirectional, and are either inputs or outputs of the W712.
Frame Timer Synthesizer
This block synthesizes the SOF signal in the event of a SOF token is lost.
Remote Wakeup
This block provides support for the remote wakeup function.
USB Transfers
The W712 supports all four transfer types defined by the USB specification. These are: Control, Isochronous, Interrupt, and Bulk.
• Control transfers must be supported by every peripheral for configuration, command and status
information flow between the host and peripheral.
• Isochronous transfers provide guaranteed bus access and constant data rates for USB devices.
• Interrupt transfers support human input devices that need to communicate small amounts of data
infrequently.
• Bulk transfers enable devices to transfer large amounts of data as bus bandwidth becomes available.
USB Interface
The W712 connects to the Universal Serial Bus via Oki’s universal USB transceivers. The USB specific I/O
converts the W712’s internal unidirectional signals into compliant USB signals. The universal USB transceiver allows the designers’ application module to interface with the physical layer of the Universal Serial
Bus. It transmits and receives serial data at both full-speed (12Mb/s) and low-speed (1.5Mb/s) data rates.
See Appendix for Oki’s USB transceiver Data Sheets.
8
Oki Semiconductor
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ W712 USB Device Controller ■
GLOSSARY
Explanation
Term
Bandwidth
The amount of data transmitted per unit of time, typically bits per second (bps) or bytes per second (Bps).
Bit
A unit of information used by digital computers. Represents the smallest piece of addressable memory within a
computer. A bit expresses the choice between two possibilities and is typically represented by a logical one (1) or
zero (0).
Bit Stuffing
Insertion of a “0” bit into a data stream to cause an electrical transition on the data wires allowing a PLL to remain
locked.
Bulk Transfer
Nonperiodic, large burst communication typically used for a transfer that can use any available bandwidth and also
be delayed until bandwidth is available.
Control Transfer
One of four Universal Serial Bus Transfer Types. Control transfers support configuration/command/status type
communications between client and function.
CRC
See Cyclic Redundancy Check.
Cyclic Redundancy Check
A check performed on data to see if an error has occurred in transmitting, reading, or writing the data. The result
of a CRC is typically stored or transmitted with the checked data. The stored or transmitted result is compared to
a CRC calculated for the data to determine if an error has occurred.
Device Endpoint
A uniquely identifiable portion of a Universal Serial Bus device that is the source or sink of information in a
communication flow between the host and device.
Endpoint
See Device Endpoint.
Interrupt Transfer
One of four Universal Serial Bus Transfer Types. Interrupt transfers characteristics are small data, non-periodic,
low frequency, bounded latency, device initiated communication typically used to notify the host of device service
needs.
Isochronous Transfer
One of four Universal Serial Bus Transfer Types. Isochronous transfers are used when working with isochronous
data. Isochronous transfers provide periodic, continuous communication between host and device.
Non-Return-to-Zero-Invert
A method of encoding serial data in which ones and zeroes are represented by opposite and alternating high and
low voltages where there is no return to zero (reference) voltage between encoded bits. Eliminates the need for
clock pulses.
NRZI
See Non-Return-to-Zero-Invert.
PLL
Phase Locked Loop. A circuit that acts as a phase detector to keep an oscillator in phase with an incoming
frequency.
Protocol
A specific set of rules, procedures, or conventions relating to format and timing of data transmission between two
devices.
Transaction
The delivery of service to an endpoint. Consists of a token packet, optional data packet, and optional handshake
packet. Specific packets are allowed/required based on the transaction type.
Transfer
One or more bus transactions to move information between a software client and its function.
Transfer Type
Determines the characteristics of the data flow between a software client and its function. Four Transfer types are
defined: control, interrupt, bulk, and isochronous.
Universal Serial Bus
A collection of Universal Serial Bus devices and the software and hardware that allow them to connect the
capabilities provided by functions to the host.
Universal Serial Bus Interface
The hardware interface between the Universal Serial Bus cable and a Universal Serial Bus device. This includes the
protocol engine required for all Universal Serial Bus devices to be able to receive and send packets.
USB
See Universal Serial Bus.
Oki Semiconductor
9
■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
10
Oki Semiconductor
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ W712 USB Device Controller ■
APPENDIX
0.5µm MSM13R0000 SOG
and MSM98R000 CSA
USB I/O
Library Data Sheets
The following section contains USB I/O library data sheets
Oki Semiconductor
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■ W712 USB Device Controller ■ –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
12
Oki Semiconductor
0.5µm Sea of Gates-MSM13R0000
BUD2SLL
MSM13R-Rel. 1.0
Cell Count
USB I/O Buffer
with Full / Low Speed
4 I/O 2 PADs
Logic symbol
I
A
Y
YB
O
I
AN
YD
YBN
O
EB
I
S
YN
GN
Truth Table
Pin Definition
Fan-in
Fan-out
(MAX.)
Name
Type
A
In
2.9
-
AN
In
2.9
-
EB
In
3.0
-
GN
In
7.3
-
S
In
5.8
-
YB
I/O
-
-
YBN
I/O
-
-
YD
Out
-
43
Y
Out
-
40
YN
Out
-
40
Input
S
EB
A
AN
GN
YB
YBN
YB
YBN
YD
Y
YN
0
1
0
1
X
X
X
1
0
0
1
X
X
X
1
1
1
1
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
Z
1
0
Z
0
1
0
1
-
1
0
0
1
-
0
1
X
X
0
1
1
0
1
0
1
0
1
X
1
0
0
1
1
0
X
0
1
0
1
X
X
0
1
0
1
X
1
0
0
1
X
X
1
0
0
1
X
1
1
1
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
Z
1
0
Z
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
-
-
0
1
X
X
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
X
1
0
0
1
1
0
1
0
0
1
X
1
1
1
1
1
1
1
1
1
1
Note:
S=0: Low Speed Function
S=1: Full Speed Function
BUD2SLL
Oki Semiconductor
Output
0.5µm Sea of Gates-MSM13R0000
MSM13R-Rel. 1.0
USB I/O Buffer
with Full / Low Speed
BUD2SLL
Delay Parameters (VDD = 3.3V,Tj=25°C)
To
LH/HL
tpd0'
(ns)
α
(ns/FO)
γ
(ns/pF)
YB
YD
YBN
YD
GN
YD
YB
Y
YBN
YN
LH
HL
LH
HL
LH
HL
LH
HL
LH
HL
1.658
1.593
1.658
1.593
0.668
1.230
0.480
1.033
0.480
1.033
0.021
0.016
0.021
0.016
0.021
0.016
0.022
0.032
0.022
0.032
0.582
0.384
0.582
0.384
0.582
0.378
0.591
0.767
0.591
0.767
tpd0'
(ns)
α
(ns/FO)
-
γ
(ns/pF)
S=0: Low Speed
To
LH/HL
A
YB
AN
YBN
EB
YB
EB
YBN
GN
YB
GN
YBN
LH
HL
LH
HL
LZ
ZL
HZ
ZH
LZ
ZL
HZ
ZH
LZ
ZL
HZ
ZH
LZ
ZL
HZ
ZH
113.448
112.385
121.419
112.658
1.992
2.567
1.496
70.919
2.516
2.798
2.562
67.373
1.853
2.127
1.335
93.127
2.401
2.367
2.401
89.655
4 I/O 2 PADs
S=1: Full Speed
From
From
Cell Count
0.082
0.071
0.082
0.071
0.190
0.071
0.215
0.082
0.190
0.071
0.215
0.082
0.190
0.071
0.215
0.082
0.190
0.071
0.215
0.082
α
γ
(ns/FO)
(ns/pF)
A
LH
YB
4.550
0.608
HL
4.261
0.238
AN
4.569
0.498
LH
YBN
4.246
0.237
HL
EB
YB
LZ
1.191
0.152
ZL
4.774
0.149
HZ
3.193
0.165
ZH
1.221
0.068
EB
YBN
LZ
1.194
0.366
ZL
4.773
0.145
HZ
3.703
0.407
ZH
0.692
0.098
Power Dissipation (VDD = 3.3V,Tj =25°C)
S=0:Low Speed Function
AC: 2940.4µW/MHz
DC: 311.2µW
YB=VIH=3.3V, YBN=VIL=0V
1730.9µW(#2) YB=VOH≥2.8V, YBN=VOL≤0.3V
1353.8µW(#2) YB=VOL≤0.3V, YBN=VOH≥2.8V
0.0µW when Power Down Mode(GN=1) is used
S=1:Full Speed Function
AC: 48.0µW/MHz
DC: 311.2µW
YB=VIH=3.3V, YBN=VIL=0V
1009.4µW(#1) YB=VOH≥2.8V, YBN=VOL≤0.3V
723.4µW(#1) YB=VOL≤0.3V, YBN=VOH≥2.8V
0.0µW when Power Down Mode(GN=1) is used
From
To
LH/HL
tpd0'
(ns)
Output Switching Parameters (VDD = 3.3V,Tj =25°C)
DC Parameters (VDD: core/IO = 3.3/3.3V±0.3V,Tj = 0 to 85°C)
Parameter
VDI
Vt+
VtVOH
VOL
Value
0.2V
2.0V
0.8V
2.8V
0.3V
Conditions
15kΩ to GND
1.5kΩ to 3.6V
Note: VDI = Differential Input Sensitivity
BUD2SLL
Oki Semiconductor
Output
#1
YB
YBN
#1
#2
YB
YBN
#2
tr0
(ns)
γr
(ns/pF)
tf0
(ns)
γf
(ns/pF)
1.822
0.095
2.041
0.090
1.491
0.105
1.821
0.087
79.749
0.106
77.070
0.055
136.166
0.001
78.704
0.085
Note: #1 = Full Speed Function
YB: RPD=15kΩ , RPU=1.5kΩ
YBN: RPD=15kΩ
#2 = Low Speed Function
YB: RPD=15kΩ
YBN: RPD=15kΩ , RPU=1.5kΩ
References
See the USB Specification Revision 1.0 for more information on USB functionality.
The information contained herein can change without notice owing to product and/or technical improvements.
Please make sure before using the product that the information you are referring to is up-to-date.
The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action
and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in
the actual circuit and assembly designs.
OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect,
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to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range.
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When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges,
including but not limited to operating voltage, power dissipation, and operating temperature.
The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office
automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for
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Copyright 1995 OKI SEMICONDUCTOR
OKI Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by
OKI Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by OKI
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granted under any patents or patent rights of OKI.
Oki Semiconductor
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