OKI MSM512805C-40TS-K 262,144-word x 8-bit dynamic ram : fast page mode type with edo Datasheet

E2G0021-17-41
¡ Semiconductor
MSM512805C
¡ Semiconductor
This version:
Jan. 1998
MSM512805C
Previous version: May 1997
262,144-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM512805C is a 262,144-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM512805C achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer
metal CMOS process. The MSM512805C is available in a 26/24-pin plastic SOJ or 26/24-pin plastic
TSOP.
FEATURES
• 262,144-word ¥ 8-bit configuration
• Single 5 V power supply, ±5% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 512 cycles/8 ms
• Fast page mode with EDO, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package options:
26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27)
(Product : MSM512805C-xxJS)
26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM512805C-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
MSM512805C-40
40 ns 20 ns 10 ns 10 ns
MSM512805C-45
MSM512805C-50
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
80 ns
735 mW
45 ns 24 ns 14 ns 14 ns
90 ns
682.5 mW
50 ns 26 ns 14 ns 14 ns
100 ns
630 mW
5.25 mW
1/16
¡ Semiconductor
MSM512805C
PIN CONFIGURATION (TOP VIEW)
VSS 1
26 VSS
VSS 1
26 VSS
DQ1 2
25 DQ8
DQ1 2
25 DQ8
DQ2 3
24 DQ7
DQ2 3
24 DQ7
DQ3 4
23 DQ6
DQ3 4
23 DQ6
DQ4 5
22 DQ5
DQ4 5
22 DQ5
WE 6
21 CAS
WE 6
21 CAS
RAS 8
19 OE
RAS 8
19 OE
A0 9
18 A8
A0 9
18 A8
A1 10
17 A7
A1 10
17 A7
A2 11
16 A6
A2 11
16 A6
A3 12
15 A5
A3 12
15 A5
VCC 13
14 A4
VCC 13
14 A4
26/24-Pin Plastic SOJ
Pin Name
A0 - A8
Function
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 - DQ8
Note:
26/24-Pin Plastic TSOP
(K Type)
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
The same GND voltage level must be provided to every VSS pin.
2/16
¡ Semiconductor
MSM512805C
BLOCK DIAGRAM
RAS
Timing
Generator
Timing
Generator
CAS
9
Column
Address
Buffers
9
Write
Clock
Generator
Column
Decoders
WE
OE
8
Internal
Address
Counter
A0 - A8
Refresh
Control Clock
Sense
Amplifiers
8
I/O
Selector
Row
Address
Buffers
9
Row
Decoders
Word
Drivers
8
8
8
8
9
Output
Buffers
Input
Buffers
DQ1 - DQ8
8
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/16
¡ Semiconductor
MSM512805C
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.75
5.0
5.25
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
(VCC = 5 V ±5%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A8)
CIN1
—
6
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 - DQ8)
CI/O
—
7
pF
4/16
¡ Semiconductor
MSM512805C
DC Characteristics
Parameter
(VCC = 5 V ±5%, Ta = 0°C to 70°C)
Symbol
Condition
MSM512805 MSM512805 MSM512805
C-45
C-40
C-50
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
Input Leakage Current
ILI
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
140
—
130
—
120
mA 1, 2
—
2
—
2
—
2
—
1
—
1
—
1
—
140
—
130
—
120
—
5
—
5
—
5
—
140
—
130
—
120
mA 1, 2
—
110
—
100
—
90
mA 1, 3
0 V £ VI £ 6.5 V;
All other pins not
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current (Standby)
Current (Standby)
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
tRC = Min.
≥ VCC –0.2 V
mA
1
RAS cycling,
ICC3 CAS = VIH,
mA 1, 2
tRC = Min.
RAS = VIH,
ICC5 CAS = VIL,
mA
1
DQ = enable
Average Power
Supply Current
RAS, CAS cycling,
RAS, CAS = VIH
(RAS-only Refresh)
Power Supply
0 V £ VO £ 5.25 V
ICC2 RAS, CAS
Average Power
Supply Current
DQ disable
ICC6
RAS cycling,
CAS before RAS
RAS = VIL,
ICC7 CAS cycling,
tHPC = Min.
Notes : 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/16
¡ Semiconductor
MSM512805C
AC Characteristics (1/2)
(VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3
Parameter
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Access Time from RAS
MSM512805
C-40
MSM512805
C-45
MSM512805
C-50
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
tRWC
tHPC
80
130
20
—
—
—
90
140
20
—
—
—
100
150
20
—
—
—
ns
ns
ns
tHPRWC
70
—
75
—
77
—
ns
Symbol
tRAC
—
40
—
45
—
50
ns
4, 5, 6
Access Time from CAS
tCAC
Access Time from Column Address
Access Time from CAS Precharge
tAA
tCPA
—
—
10
20
—
—
14
24
—
—
14
26
ns
ns
4, 5
4, 6
—
25
—
28
—
30
ns
4
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
tDOH
10
—
—
—
0
5
14
—
—
—
0
5
14
—
—
ns
ns
ns
4
4
Data Output Hold After CAS Low
—
0
5
CAS to Data Output Buffer Turn-off Delay Time tCEZ
RAS to Data Output Buffer Turn-off Delay Time tREZ
0
12
12
0
7, 8
0
12
12
ns
0
12
12
0
0
ns
7, 8
OE to Data Output Buffer Turn-off Delay Time
0
12
0
12
0
13
ns
7
tOEZ
WE to Data Output Buffer Turn-off Delay Time tWEZ
0
12
0
12
0
13
ns
7
Transition Time
Refresh Period
50
8
2
—
50
8
2
—
50
8
ns
ms
3
tREF
2
—
RAS Precharge Time
tRP
30
—
35
—
40
—
ns
RAS Pulse Width
tRAS
40
10,000
45
10,000
50
10,000
ns
RAS Pulse Width (Fast Page Mode with EDO) tRASP
40
100,000
45
100,000
50
100,000
ns
RAS Hold Time
RAS Hold Time referenced to OE
tRSH
tROH
10
10
—
—
14
10
—
—
14
10
—
—
ns
ns
CAS Precharge Time (Fast Page Mode with EDO) tCP
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
10
10,000
10
10,000
10
10,000
ns
CAS Hold Time
CAS to RAS Precharge Time
tCSH
tCRP
40
5
—
—
45
5
—
—
50
5
—
—
ns
RAS Hold Time from CAS Precharge
tRHCP
tCHO
25
—
28
—
30
—
ns
OE Hold Time from CAS (DQ Disable)
5
—
5
—
5
—
ns
RAS to CAS Delay Time
RAS to Column Address Delay Time
tRCD
tRAD
15
10
30
20
17
12
31
21
18
13
36
24
ns
ns
RAS to Second CAS Delay Time
tRSCD
40
—
45
—
50
—
ns
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
5
—
7
—
8
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
tAR
10
—
12
—
13
—
ns
Column Address Hold Time from RAS
30
—
35
—
40
—
ns
Column Address to RAS Lead Time
tRAL
20
—
24
—
26
—
ns
tT
ns
5
6
6/16
¡ Semiconductor
MSM512805C
AC Characteristics (2/2)
(VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3
Parameter
Symbol
MSM512805
C-40
MSM512805
C-45
MSM512805
C-50
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
—
0
—
0
—
ns
Read Command Set-up Time
tRCS
0
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
9
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
10
Write Command Hold Time
tWCH
10
—
12
—
13
—
ns
Write Command Hold Time from RAS
tWCR
30
—
35
—
40
—
ns
Write Command Pulse Width
tWP
10
—
10
—
10
—
ns
WE Pulse Width (DQ Disable)
tWPE
5
—
5
—
5
—
ns
OE Command Hold Time
OE Precharge Time
OE Command Hold Time
tOEH
tOEP
tOCH
10
7
7
—
—
—
12
7
7
—
—
—
13
7
7
—
—
—
ns
ns
ns
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tRWL
tCWL
10
10
—
—
14
14
—
—
14
14
—
—
ns
ns
Data-in Set-up Time
Data-in Hold Time
Data-in Hold Time from RAS
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
tDS
tDH
tDHR
tOED
tCWD
tAWD
tRWD
0
10
—
—
0
12
—
—
0
13
—
—
ns
ns
30
10
—
—
—
—
40
13
—
—
ns
ns
30
40
60
—
—
—
35
12
36
48
70
—
—
—
38
52
75
—
—
—
ns
ns
ns
10
10
10
CAS Precharge WE Delay Time
tCPWD
45
—
46
—
50
—
ns
10
CAS Active Delay Time from RAS Precharge
tRPC
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)
tCSR
tCHR
0
10
20
—
—
—
0
10
25
—
—
—
0
10
25
—
—
—
ns
ns
ns
9
11
11
7/16
¡ Semiconductor
Notes:
MSM512805C
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 50 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/16
E2G0095-17-41H
,
,,
,
,
,,,,
,,
¡ Semiconductor
MSM512805C
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
tCSH
tCRP
tRCD
VIH –
CAS
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRSH
tCAS
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
OE
VIH –
VIL –
tAA
tROH
tREZ
tOEA
VIH –
VIL –
tCAC
tRAC
DQ
VOH –
tOEZ
Open
VOL –
tRCH
tRRH
tCEZ
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
VIH –
CAS
VIL –
VIH –
VIL –
tCSH
tRCD
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
WE
tRAL
VIH –
VIL –
tWCH
tWP
tCWL
tWCR
tRWL
VIH –
OE
VIL –
tDS
DQ
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
9/16
,
,,
¡ Semiconductor
MSM512805C
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH –
VIL –
tRP
tAR
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
10/16
,,,,
,
,
¡ Semiconductor
MSM512805C
Fast Page Mode Read Cycle (Part-1)
tRASP
RAS
VIH –
VIL –
tAR
tCRP
CAS
VIH
VIL
WE
tRHCP
tHPC
tRCD
tCP
tCP
tCAS
–
–
tCAS
tCAS
tRAD
tASR
Address
tRP
tRSCD
VIH –
VIL –
tASC
tRAH
Row
tCSH
tCAH
tASC
Column
tASC
tCAH
Column
Column
tRCS
tRRH
VIH –
VIL –
tCHO
DQ
tOCH
tRAC
tAA
OE
tCAH
tOEP
tCPA
tOEA
tCAC
VOH –
VOL –
tCLZ
tOEZ
tCAC
Valid
Data-out
Valid
Data-out
tOEA
tOEA
tCAC
tDOH
tOEP
tAA
tAA
VIH –
VIL –
tOEZ
Valid*
Data-out
* : Same Data,
tREZ
Valid*
Data-out
"H" or "L"
Fast Page Mode Read Cycle (Part-2)
tRASP
RAS
VIH –
VIL –
tAR
WE
OE
DQ
VIH –
VIL –
VIH –
VIL –
tRCD
tCP
tCAS
tCAS
tRAD
tRAH
tCSH
tASC tCAH
Row
tASC
Column
tCAH
Column
tRCS
tASC
tCAH
Column
tRCS
tRAC
tAA
VIH –
VIL –
VOH –
VOL –
tCRP
tCP
tCAS
VIH –
VIL –
tASR
Address
tRHCP
tHPC
tCRP
CAS
tRP
tRSCD
tRCH
tWPE
tAA
tAA
tCPA
tOEA
tCAC
tCLZ
tWEZ
Valid
Data-out
tCAC
tDOH
tCAC
Valid
Data-out
tCEZ
Valid
Data-out
"H" or "L"
11/16
,,,
,
,
¡ Semiconductor
MSM512805C
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tRSCD
RAS
VIH –
VIL –
tAR
CAS
tRAD
tRAH
tASR
Address
WE
VIH –
VIL –
OE
VIH –
VIL –
tASC
Column
tWCS
DQ
tCP
tCAS
tCSH
tASC tCAH
Row
tDHR
tHPC
tCP
tCAS
VIH –
VIL –
VIH –
VIL –
tHPC
tRCD
tCRP
VIH –
VIL –
tCAH
tWCS
tDH
Valid
Data-in
Column
tWCH
tDS
tRSH
tCAH
tASC
Column
tWCH
tDS
tCAS
tDH
Valid
Data-in
tWCS
tWCH
tDS
tDH
Valid
Data-in
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
tRSCD
RAS
tRWD
VIH –
VIL –
tAR
tCRP
CAS
VIH –
VIL –
VIH –
VIL –
tCWD
tRAD
tASR
Address
tCP
tRCD
Row
tCWL
tCAH
tRCS
tAWD
VIH –
VIL –
tAWD
tDS tWP
VIH –
VIL –
tCAC
VI/OH –
VI/OL –
tOED
tOEZ
Valid
Data-out
tCLZ
tRWL
tCWD
tRAC
tOEA
DQ
tCPA
tCAH
Column
tAA
OE
tASC
Column
tRCS
WE
tCPWD
tHPRWC
tRAH
tASC
tAA
tOEH
tDS
tOED
tOEA
tCAC
tDH
Valid
Data-in
tOEZ
Valid
Data-out
tCLZ
tWP
tOEH
tDH
Valid
Data-in
"H" or "L"
12/16
,
¡ Semiconductor
MSM512805C
RAS-Only Refresh Cycle
tRC
RAS
VIL –
CAS
Address
VIH –
VIL –
tRP
tRAS
VIH –
tCRP
tRPC
tASR
VIH –
tRAH
Row
VIL –
tCEZ
DQ
VOH –
Open
VOL –
Note: WE, OE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
tRP
RAS
VIH –
VIL –
DQ
VIH –
VIL –
VOH –
VOL –
tRP
tRPC
tRPC
tCP
CAS
tRAS
tCSR
tCHR
tCEZ
Open
Note: WE, OE, Address = "H" or "L"
13/16
,
,,
,,
,
,,
¡ Semiconductor
MSM512805C
Hidden Refresh Read Cycle
tRC
tRAS
RAS
CAS
VIH –
VIL –
tCRP
VIH –
VIL –
WE
OE
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
Row
Column
tRCS
tRRH
tRAL
VIH –
VIL –
tAA
tROH
tOEA
VIH –
VIL –
VOH –
VOL –
tCHR
tCAH
tRAH
tCEZ
tCAC
tCLZ
tRAC
DQ
tRP
tAR
tASR
Address
tRC
tRAS
tRP
tOEZ
Open
tREZ
Valid Data-out
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRAS
RAS
CAS
Address
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
OE
VIH –
VIL –
DQ
VIH –
VIL –
tRP
tAR
tCRP
tASR
tRCD
tRSH
tRAD
tASC
tCAH
tRAH
tCHR
tRAL
Column
Row
tRWL
tWCH
tWCS
WE
tRC
tRAS
tRP
tWP
tWCR
tDS
tDH
Valid Data-in
tDHR
"H" or "L"
14/16
¡ Semiconductor
MSM512805C
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/24-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/16
¡ Semiconductor
MSM512805C
(Unit : mm)
TSOPII26/24-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/16
Similar pages