OKI MSM514260E-70 262,144-word x 16-bit dynamic ram : fast page mode type Datasheet

Semiconductor
This version:Aug.2000
MSM514260E
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514260E is a 262,144-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology.
The MSM514260E achieves high integration, high-speed operation, and low-power consumption because Oki
manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514260E
is available in a 40-pin plastic SOJ, 44/40-pin plastic TSOP.
FEATURES
•
262,144-word × 16-bit configuration
•
Single 5V power supply, ±10% tolerance
•
Input
: TTL compatible, low input capacitance
•
Output
: TTL compatible, 3-state
•
Refresh
: 512 cycles/8 ms
•
Fast page mode, read modify write capability
•
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•
Package options:
40-pin 400mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM514260E-xxJS)
44/40-pin 400mil plastic TSOP
(TSOPII44/40-P-400-0.80-K)
(Product : MSM514260E-xxTS-K)
xx : indicates speed rank.
PRODUCT FAMILY
Family
MSM514260E
Access Time (Max.)
Cycle Time
Power Dissipation
tRAC
tAA
tCAC
tOEA
(Min.)
Operating (Max.)
60ns
30ns
15ns
15ns
110ns
633mW
70ns
35ns
20ns
20ns
130ns
578mW
Standby (Max.)
5.5mW
1/14
MSM514260E
PIN CONFIGRATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VCC 20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40-Pin Plastic SOJ
VSS
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44
43
42
41
40
39
38
37
36
35
VSS
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
NC 13
NC 14
WE 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
VCC 22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
44/40-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0 − A8
Address Input
RAS
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
UCAS
Upper Byte Column Address Strobe
DQ1 - DQ16
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every V CC pin, and the same
GND voltage level must be provided to every VSS pin.
2/14
MSM514260E
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
I/O
Controller
9
9
Row
Address
Buffers
Output
Buffers
8
Input
Buffers
8
8
Input
Buffers
8
8
Output
Buffers
8
DQ1 - DQ8
Column
Address
Buffers
9
Internal
Address
Counter
A0 - A8
8
Sense Amplifiers
Refresh
Control Clock
9
Row
Decoders
Column Decoders
Word
Drivers
I/O
Selector
16
16
DQ9 - DQ16
Memory
Cells
8
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1-DQ8
DQ9-DQ16
H
*
*
*
*
High-Z
High-Z
Standby
L
H
H
*
*
High-Z
High-Z
Refresh
L
L
H
H
L
DOUT
High-Z
Lower Byte Read
L
H
L
H
L
High-Z
DOUT
Upper Byte Read
L
L
L
H
L
DOUT
DOUT
Word Read
L
L
H
L
H
DIN
Don’t Care
Lower Byte Write
L
H
L
L
H
Don’t Care
DIN
Upper Byte Write
L
L
L
L
H
DIN
DIN
Word Write
L
L
L
H
H
High-Z
High-Z

* : “H” or “L”
3/14
MSM514260E
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
−0.5 to VCC + 0.5
V
Voltage VCC supply Relative to VSS
VCC
−0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
−55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Notes:
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
VIH
VIL
4.5
5.0
5.5
V
0
0
0
V
2.4

VCC + 0.5*1
V
−0.5

0.8
V
*2
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Input Capacitance (A0 – A8)
Input Capacitance
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 – DQ16)
Symbol
Typ.
Max.
Unit
CIN1

5
pF
CIN2

7
pF
CI/O

7
pF
4/14
MSM514260E
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
Parameter
Symbol
Condition
MSM514260
E-60
MSM514260
E-70
Min.
2.4
Max
.
VCC
0
Unit
Note
2.4
Max
.
VCC
V
0.4
0
0.4
V
−10
10
−10
10
µA
−10
10
−10
10
µA

115

105
mA
1,2
RAS, CAS = VIH

2

2
RAS, CAS ≥
VCC – 0.2V


mA
1
1
1

115

105
mA
1,2

5

5
mA
1

115

105
mA
1,2

115

105
mA
1,3
Min.
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
0V ≤ VI ≤ 6.5V ;
Input Leakage Current
ILI
Output Leakage Current
ILO
Average Power Supply Current
(Operating)
Power Supply Current
(Standby)
Average Power Supply Current
(RAS-only Refresh)
Power Supply Current
(Standby)
ICC1
ICC2
All other pins not
under test = 0V
DQ disable
0V ≤ VO ≤ VCC
RAS, CAS cycling,
tRC = Min.
RAS cycling,
ICC3
CAS = VIH,
tRC = Min.
RAS = VIH,
ICC5
CAS = VIL,
DQ = enable
Average Power Supply Current
(CAS before RAS Refresh)
Average Power Supply Current
(Fast Page Mode)
Notes: 1.
ICC6
RAS = cycling,
CAS before RAS
RAS = VIL,
ICC7
CAS cycling,
tPC = Min.
ICC Max. is specified as ICC for output open condition.
2.
The address can be changed once or less while RAS = VIL.
3.
The address can be changed once or less while CAS = VIH.
5/14
MSM514260E
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
MSM514260
E-60
MSM514260
E-70
Min.
Max.
Min.
Max.
tRC
110

130

ns
tRWC
155

185

ns
tPC
40

45

ns
tPRWC
85

100

ns
Access Time from RAS
tRAC

60

70
ns
4,5,6
Access Time from CAS
tCAC

15

20
ns
4,5
Access Time from Column Address
tAA

30

35
ns
4,6
Access Time from CAS Precharge
tCPA

35

40
ns
4,12
Access Time from OE
tOEA

15

20
ns
4
Output Low Impedance Time from CAS
tCLZ
0

0

ns
4
CAS to Data Output Buffer Turn-off Delay Time
tOFF
0
15
0
15
ns
7
OE to Data Output Buffer Turn-off Delay Time
tOEZ
0
15
0
15
ns
7
Transition Time
tT
3
50
3
50
ns
3
Refresh Period
tREF

8

8
ms
RAS Precharge Time
tRP
40

50

ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
15

20

ns
RAS Hold Time referenced to OE
tROH
15

20

ns
CAS Precharge Time (Fast Page Mode)
tCP
10

10

ns
CAS Pulse Width
tCAS
15
10,000
20
10,000
ns
CAS Hold Time
tCSH
60

70

ns
CAS to RAS Precharge Time
tCRP
5

5

ns
12
RAS Hold Time from CAS Precharge
tRHCP
35

40

ns
12
RAS to CAS Delay Time
tRCD
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

10

ns
Column Address Set-up Time
tASC
0

0

ns
11
Column Address Hold Time
tCAH
10

15

ns
11
Parameter
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Symbol
Unit
Note
14
6/14
MSM514260E
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
Parameter
Symbol
MSM514260
E-60
MSM514260
E-70
Min.
Max.
Min.
Max.
Unit
Note
Column Address to RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
11
Read Command Hold Time
tRCH
0

0

ns
8,11
Read Command Hold Time referenced to RAS
tRRH
0

0

ns
8
Write Command Set-up Time
tWCS
0

0

ns
9,11
Write Command Hold Time
tWCH
10

15

ns
11
Write Command Pulse Width
tWP
10

10

ns
OE Command Hold Time
tOEH
15

20

ns
Write Command to RAS Lead Time
tRWL
15

20

ns
Write Command to CAS Lead Time
tCWL
15

20

ns
13
Data-in Set-up Time
tDS
0

0

ns
10,11
Data-in Hold Time
tDH
10

15

ns
10,11
OE to Data-in Delay Time
tOED
15

20

ns
CAS to WE Delay Time
tCWD
40

50

ns
9
Column Address to WE Delay Time
tAWD
55

65

ns
9
RAS to WE Delay Time
tRWD
85

100

ns
9
CAS Precharge WE Delay Time
tCPWD
60

70

ns
9
CAS Active Delay Time from RAS Precharge
tRPC
5

5

ns
11
RAS to CAS Set-up Time (CAS before RAS)
tCSR
10

10

ns
11
RAS to CAS Hold Time (CAS before RAS)
tCHR
10

10

ns
12
7/14
MSM514260E
Notes:
1.
A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2.
The AC characteristics assume tT = 5ns.
3.
VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified t RCD (Max.)
limit, then the access time is controlled by tCAC.
6.
Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (Max.)
limit, then the access time is controlled by tAA.
7.
tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8.
tRCH or tRRH must be satisfied for a read cycle.
9.
tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), t AWD ≥ tAWD (Min.) and t CPWD ≥ tCPWD (Min.), then
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.
10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle,
and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is
earlier.
12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
13. tCWL should be satisfied by both UCAS and LCAS.
14. tCP is determined by the time both UCAS and LCAS are high.
8/14
MSM514260E
Timing Chart
•
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRAD
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
VIH
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tOEA
VIH
VIL
tCAC
tRAC
DQ
tOFF
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
•
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
Valid Data-in
tDH
Open
“H” or “L”
9/14
MSM514260E
•
Read Modify Write Cycle
tRWC
RAS
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRSH
tCAS
VIH
VIH
VIL
tCRP
tRAD
VIL
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Column
tRCS
tCWD
tWP
tRWD
WE
OE
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
tDH
Valid
Data-in
“H” or “L”
10/14
MSM514260E
•
Fast Page Mode Read Cycle
tRASP
RAS
VIH
VIL
tRCD
tCRP
CAS
tCP
VIH
VIL
VIH
VIL
tRAD
tCSH
tRAH tASC
tCP
Row
tASC
Column
tCAH
Column
tRCS
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
VIH
VIL
tRAC
tCPA
tOFF
tOEZ
tCLZ
VOH
tAA
tOEA
tCAC
DQ
tASC
Column
tRCH
tCRP
tRAL
tCAH
tOEA
OE
tRSH
tCAS
tCAS
tCAH
tRCS
WE
tRHCP
tCAS
tASR
Address
tRP
tPC
tCPA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
VOL
tRRH
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
Valid
Data-out
“H” or “L”
•
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
tPC
VIH
VIL
tCRP
tCP
VIH
VIL
tRAH
tASC
Row
tCSH
tCAH
tASC
Column
tWCS
VIH
tWCH
tWP
tCRP
tRAL
tCAH
tASC
Column
tRWL
tCWL
tCWL
tWCS
tWCH
tWP
tWCS
tWP
tWCH
VIL
tDS
DQ
tCAH
Column
tCWL
WE
tRSH
tCAS
tCAS
tRAD
VIL
VIH
tCP
tCAS
tASR
Address
tRCD
tRHPC
VIH
VIL
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
tDS
tDH
Valid
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/14
MSM514260E
•
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
CAS
tCSH
VIH
VIL
tRCD
VIL
tCAH
tCWL
tASC
Row
tASC
tRAL
tCWL
Column
tCWD
tRCS
tCPWD
tCWD
tAWD
tAWD
tRCS
tPWD
tCWD
tCPWD
tCWL
tRWL
VIH
tAWD
VIL
tWP
tCPA
tDH
VIH
tWP
tDH
tCAC
VI/OH
tOEZ
Out
VI/OL
tCLZ
tCPA
tAA
tOEA
tOED
VIL
In
tDH
tDS
tOEA
tOED
tOEZ
tCAC
tWP
tROH
tDS
tAA
tDS
tOEA
Out
tOED
tOEZ
tCAC
In
Out
In
tCLZ
tCLZ
Note: Out = Valid Data-out, In = Valid Data-in
•
tCRP
tCAH
Column
tAA
DQ
tCAS
tASC
Column
tRAC
OE
tCP
tCAS
tRAD
VIL
VIH
tRP
tRSH
tCAH
tRCS
WE
tCP
tCAS
VIH
tRAH
tASR
Address
tPRWC
“H” or “L”
RAS-only Refresh Cycle
tRC
RAS
tRAS
VIH
tRP
VIL
tCRP
CAS
Address
DQ
tRPC
VIH
VIL
VIH
VIL
VOH
VOL
tASR
tRAH
Row
tOFF
Open
Note: WE, OE = “H” or “L”
“H” or “L”
12/14
MSM514260E
•
CAS before RAS Refresh Cycle
tRP
RAS
CAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tOFF
DQ
VOH
Open
VOL
“H” or “L”
Note: WE, OE, Address = “H” or “L”
•
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRCD
tRSH
tCHR
tRAD
VIL
VIH
VIL
tRAH
tASC
tCAH
Column
Row
tRCS
WE
tRP
tRP
VIH
tASR
Address
tRC
tRAS
tRAS
tCAC
tRRH
VIH
tRAL
VIL
tAA
tROH
OE
DQ
VIH
VIL
VOH
VOL
tOFF
tOEA
tRAC
tOEZ
tCLZ
Open
Valid Data-out
“H” or “L”
13/14
MSM514260E
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRAS
tRCD
tRSH
VIH
VIL
tRAH
tRAL
tASC
Row
tCAH
Column
tWCS
WE
OE
DQ
tRP
tRAD
VIL
VIH
tRP
tCHR
tASR
Address
tRC
tRAS
tWCH
VIH
VIL
tWP
VIH
VIL
VIH
VIL
tDS
tDH
Valid Data-in
“H” or “L”
14/14
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit and assembly designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
OKI assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to:traffic control, automotive, safety, aerospace,
nuclear power control, and medical, including lift support and maintenance.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.
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