OKI MSM514265E-XXJS 262,144-word x 16-bit dynamic ram : fast page mode type with edo Datasheet

PEDD514265ESL-01
This version : Jan. 2001
Semiconductor
MSM514265E/ESL
Preliminary
262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM514265E/ESL is a 262,144-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM514265E/ESL achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS
process. The MSM514265E/ESL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The
MSM514265ESL (the Self-refresh version) is specially designed for lower-power applications.
FEATURES
•
262,144-word × 16-bit configuration
•
Single 5V power supply, ±10% tolerance
•
Input
: TTL compatible, low input capacitance
•
Output
: TTL compatible, 3-state
•
Refresh
: 512 cycles/8ms, 512 cycles/128 ms (SL version)
•
Fast page mode with EDO, read modify write capability
•
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•
CAS before RAS self-refresh capability (SL version)
•
Package options:
40-pin 400mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM514265E/ESL-xxJS)
44/40-pin 400mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265E./ESL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Family
MSM514265E/ESL
Cycle Time
Power Dissipation
tRAC
tAA
tCAC
tOEA
(Min.)
Operating (Max.)
Standby (Max.)
60ns
30ns
15ns
15ns
104ns
633mW
70ns
35ns
20ns
20ns
124ns
578mW
5.5mW/
1.1mW (SL version)
PEDD514265ESL-01
MSM514265E/ESL
PIN CONFIGRATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
WE 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
VCC 20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44
43
42
41
40
39
38
37
36
35
VSS
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
NC 13
NC 14
WE 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
VCC 22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
40-Pin Plastic SOJ
44/40-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0 − A8
Address Input
RAS
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
UCAS
Upper Byte Column Address Strobe
DQ1–DQ16
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same
GND voltage level must be provided to every VSS pin.
PEDD514265ESL-01
MSM514265E/ESL
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
LCAS
UCAS
I/O
Controller
9
9
Output
Buffers
8
Input
Buffers
8
8
Input
Buffers
8
8
Output
Buffers
8
DQ1~DQ8
Column
Address
Buffers
9
Internal
Address
Counter
A0~A8
8
9
Row
Decoders
16
Sense Amplifiers
Refresh
Control Clock
Row
Address
Buffers
Column Decoders
Word
Drivers
I/O
Selector
16
DQ9~DQ16
Memory
Cells
8
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1-DQ8
DQ9-DQ16
H
*
*
*
*
High-Z
High-Z
Standby
L
H
H
*
*
High-Z
High-Z
Refresh
L
L
H
H
L
DOUT
High-Z
Lower Byte Read
L
H
L
H
L
High-Z
DOUT
Upper Byte Read
L
L
L
H
L
DOUT
DOUT
Word Read
L
L
H
L
H
DIN
Don’t Care
Lower Byte Write
L
H
L
L
H
Don’t Care
DIN
Upper Byte Write
L
L
L
L
H
DIN
DIN
Word Write
L
L
L
H
H
High-Z
High-Z

* : “H” or “L”
PEDD514265ESL-01
MSM514265E/ESL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
−0.5 to VCC + 0.5
V
Voltage VCC supply Relative to VSS
VCC
−0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
−55 to 150
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Notes:
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
VIH
VIL
4.5
5.0
5.5
V
0
0
0
2.4

−0.5

*2
V
VCC + 0.5
*1
0.8
V
V
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(VCC = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Input Capacitance (A0 – A8)
Input Capacitance
(RAS, LCAS, UCAS, WE, OE)
Output Capacitance (DQ1 - DQ16)
Symbol
Typ.
Max.
Unit
CIN1

5
pF
CIN2

7
pF
CI/O

7
pF
PEDD514265ESL-01
MSM514265E/ESL
DC Characteristics
(VCC = 5V ± 10%, Ta = 0°C to 70°C)
Parameter
Symbol
MSM514265
E/ESL-60
MSM514265
E/ESL-70
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
V
− 10
10
− 10
10
µA
− 10
10
− 10
10
µA

115

105
mA
1,2
RAS, CAS = VIH

2

2

1
1

mA
RAS, CAS ≥
VCC − 0.2V
1

200

200
µA
1,5
Condition
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
Input Leakage Current
ILI
Output Leakage Current
ILO
Average Power Supply Current
(Operating)
Power Supply Current
(Standby)
Average Power Supply Current
(RAS-only Refresh)
Power Supply Current
(Standby)
Average Power Supply Current
(CAS before RAS Refresh)
Average Power Supply Current
(Fast Page Mode)
Average Power Supply Current
(Battery Backup)
Average Power Supply Current
(CAS before RAS Self-Refresh)
Notes: 1.
ICC1
ICC2
0V ≤ VI ≤ VCC+0.5V;
All other pins not
under test = 0V
DQ disable
0V ≤ VO ≤ VCC
RAS, CAS cycling,
tRC = Min.
Unit Note
ICC3
RAS cycling,
CAS = VIH,
tRC = Min.

115

105
mA
1,2
ICC5
RAS = VIH,
CAS = VIL,
DQ = enable

5

5
mA
1
ICC6
RAS = cycling,
CAS before RAS

115

105
mA
1,2
ICC7
RAS = VIL,
CAS cycling,
tHPC = Min.

115

105
mA
1,3
ICC10
tRC = 125µs
CAS before RAS
tRAS = 1µs

300

300
µA
1,4
,5
ICCS
RAS ≤ 0.2V,
CAS ≤ 0.2V,

300

300
µA
1,5
ICC Max. is specified as ICC for output open condition.
2.
The address can be changed once or less while RAS = VIL.
3.
The address can be changed once or less while CAS = VIH.
4.
VCC − 0.2V ≤ VIH ≤ VCC + 0.5V, − 0.5V ≤ VIL ≤ 0.2V.
5.
SL version.
PEDD514265ESL-01
MSM514265E/ESL
AC Characteristic (1/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
MSM514265
E/ESL-60
MSM514265
E/ESL-70
Min.
Max.
Min.
Max.
tRC
104

124

ns
Read Modify Write Cycle Time
tRWC
135

160

ns
Fast Page Mode Cycle Time
tHPC
25

30

ns
tHPRWC
68

78

ns
Access Time from RAS
tRAC

60

70
ns
4, 5, 6
Access Time from CAS
tCAC

15

20
ns
4,5
Access Time from Column Address
tAA

30

35
ns
4,6
Access Time from CAS Precharge
tCPA

35

40
ns
4,13
Access Time from OE
tOEA

15

20
ns
4
Output Low Impedance Time from CAS
tCLZ
0

0

ns
4
Data Output Hold After CAS Low
tDOH
5

5

ns
CAS to Data Output Buffer Turn-off Delay Time
tCEZ
0
15
0
20
ns
7,8
RAS to Data Output Buffer Turn-off Delay Time
tREZ
0
15
0
20
ns
7,8
OE to Data Output Buffer Turn-off Delay Time
tOEZ
0
15
0
20
ns
7
WE to Data Output Buffer Turn-off Delay Time
tWEZ
0
15
0
20
ns
7
Transition Time
tT
1
50
1
50
ns
3
Refresh Period
tREF

8

8
ms
Refresh Period (SL version)
tREF

128

128
ms
RAS Precharge Time
tRP
40

50

ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode with EDO)
tRASP
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
10

13

ns
RAS Hold Time referenced to OE
tROH
10

13

ns
CAS Precharge Time
(Fast Page Mode with EDO)
tCP
10

10

ns
CAS Pulse Width
tCAS
10
10,000
10
10,000
ns
CAS Hold Time
tCSH
40

45

ns
CAS to RAS Precharge Time
tCRP
5

5

ns
13
RAS Hold Time from CAS Precharge
tRHCP
35

40

ns
13
OE Hold Time from CAS (DQ Disable)
tCHO
5

5

ns
RAS to CAS Delay Time
tRCD
14
45
14
50
ns
5
RAS to Column Address Delay Time
tRAD
12
30
12
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

10

ns
Parameter
Random Read or Write Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Symbol
Unit
Note
16
15
PEDD514265ESL-01
MSM514265E/ESL
AC Characteristic (2/2)
(VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3
Parameter
Symbol
MSM514265
E-60
MSM514265
E-70
Min.
Max.
Min.
Max.
Unit
Note
Column Address Set-up Time
tASC
0

0

ns
12
Column Address Hold Time
tCAH
10

13

ns
12
Column Address to RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
12
Read Command Hold Time
tRCH
0

0

ns
9,12
Read Command Hold Time referenced to RAS
tRRH
0

0

ns
9
Write Command Set-up Time
tWCS
0

0

ns
10,12
Write Command Hold Time
tWCH
10

13

ns
12
Write Command Pulse Width
tWP
10

10

ns
WE Pulse Width (DQ Disable)
tWPE
7

7

ns
OE Command Hold Time
tOEH
10

13

ns
OE Precharge Time
tOEP
10

10

ns
OE Command Hold Time
tOCH
10

10

ns
Write Command to RAS Lead Time
tRWL
10

13

ns
Write Command to CAS Lead Time
tCWL
10

13

ns
14
Data-in Set-up Time
tDS
0

0

ns
11,12
Data-in Hold Time
tDH
10

13

ns
11,12
OE to Data-in Delay Time
tOED
15

20

ns
CAS to WE Delay Time
tCWD
35

45

ns
10
Column Address to WE Delay Time
tAWD
50

60

ns
10
RAS to WE Delay Time
tRWD
80

95

ns
10
CAS Precharge WE Delay Time
tCPWD
55

65

ns
10
CAS Active Delay Time from RAS Precharge
tRPC
5

5

ns
12
RAS to CAS Set-up Time (CAS before RAS)
tCSR
5

5

ns
12
RAS to CAS Hold Time (CAS before RAS)
tCHR
10

10

ns
13
RAS Pulse Width
(CAS before RAS Self-Refresh)
tRASS
100

100

µs
16
RAS Precharge Time
(CAS before RAS Self-Refresh)
tRPS
110

130

ns
16
CAS Hold Time
(CAS before RAS Self-Refresh)
tCHS
− 40

− 50

ns
16
PEDD514265ESL-01
MSM514265E/ESL
Notes:
1.
A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2.
The AC characteristics assume tT = 2ns.
3.
VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.
4.
This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF.
The output timing reference levels are VOH = 2.0V (IOH = −2mA) and VOL = 0.8V (IOH = 2mA).
5.
Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC.
6.
Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
7.
tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output
achieved the open circuit condition and are not referenced to output voltage levels.
8.
tCEZ, and tREZ must be satisfied for open circuit condition.
9.
tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle.
If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then
the cycle is a read modify write cycle and data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, then the condition of the data out (at access time)
is indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle,
and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is
earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. tCWL should be satisfied by both UCAS and LCAS.
15. tCP is determined by the time both UCAS and LCAS are high.
16. Only SL version.
PEDD514265ESL-01
MSM514265E/ESL
Timing Chart
•
Read Cycle
tRC
tRAS
VIH
RAS
VIL
tRP
tCSH
tCRP
CAS
VIH
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
tRAD
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
VIH
VIL
tCAC
tRAC
DQ
tREZ
tAOE
tCEZ
tOEZ
tCLZ
VOH
VOL
Valid Data-out
Open
“H” or “L”
•
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
Valid Data-in
tDH
Open
“H” or “L”
9/15
PEDD514265ESL-01
MSM514265E/ESL
•
Read Modify Write Cycle
RAS
tRWC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
VIH
VIL
VIH
VIL
tRSH
tCAS
tCRP
tRAD
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Column
tRCS
tCWD
tWP
tRWD
WE
OE
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tDH
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
Valid
Data-in
“H” or “L”
10/15
PEDD514265ESL-01
MSM514265E/ESL
•
Fast Page Mode Read Cycle (Part-1)
tRASP
RAS
tRCD
VIH
VIL
tCSH
tCRP
CAS
Address
VIH
VIL
tASR
tRAD
tRAH tASC
Row
tRHCP
tCP
tCP
tCAS
VIH
VIL
tRP
tHPC
tCAH
tCAS
tASC
Column
tCAS
tASC
tCAH
Column
Column
tRCS
WE
OE
tOCH
tRRH
VIH
tAA
VIL
tCAC
tRAC
tAA
VIH
tCHO
tOEP
tCAC
tOEP
tOEA
tAA
VIL
tCPA
tOEA
tCAC
DQ
tCAH
tDOH
VOH
VOL
tOEA
Valid
Data-out
Valid
Data-out
tCLZ
tOEZ
tREZ
Valid *
Data-out
Valid *
Data-out
tOEZ
* : Same Dada,
•
“H” or “L”
Fast Page Mode Read Cycle (Part-2)
tRASP
RAS
CAS
Address
tRCD
VIH
VIL
tCRP
tCSH
VIH
VIL
tASR
tRAD
tRAH tASC
Row
OE
tCAH
tRHCP
tCAS
tCAH
tASC
Column
tRCS
WE
tCP
tCAS
VIH
VIL
tRP
tHPC
Column
tCP
tCAS
tASC
tCAH
Column
tRCS
VIH
VIL
tAA
tRAC
VIH
tRCH
tWPE
tOEA
tAA
tCPA
tAA
tWEZ
tCAC
tDOH
VIL
tCAC
tCAC
DQ
VOH
VOL
tCLZ
Valid *
Data-out
Valid *
Data-out
* : Same Data,
tCEZ
Valid *
Data-out
“H” or “L”
11/15
PEDD514265ESL-01
MSM514265E/ESL
•
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
Address
WE
OE
tCSH
VIH
VIL
tCRP
tHPC
tRCD
tCP
VIH
VIL
tASR
tRAD
tRAH tASC
Row
tASC
Column
tWCS
VIH
tRSH
tCAS
tCAS
tCAH
tASC
tCAH
Column
tWCH
tWCS
tCAH
Column
tWCH
tWCS tWCH
VIL
VIH
VIL
tDS
DQ
tCP
tCAS
VIH
VIL
tHPC
VIH
tDH
tDS
tDH
Valid *
Data-in
VIL
tDS
Valid *
Data-in
tDH
Valid *
Data-in
“H” or “L”
•
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
RAS
VIL
CAS
tRWD
tCRP
tRCD
tCP
VIH
tASC
tASC
VIL
VIH
VIL
tRAD
tRAH
Row
tHPRWC
Column
VIH
VIL
Column
OE
tAWD
tAWD
tAA
tDS
tWP
tOED
tOEH
VIL
VI/OH
VI/OL
tWP
tDS
tOEA
tCAC
DQ
tCWD
tRCS
tRAC
VIH
tCAH
tCPA
tCWL
tCAH
tRCS
WE
tRWL
tCWD
tASR
Address
tCPWD
tOEZ
Valid *
Data-out
tCLZ
tDH
tOED
tCAC
Valid *
Data-in
tOEZ
Valid *
Data-out
tOEH
tDH
Valid *
Data-in
tCLZ
“H” or “L”
12/15
PEDD514265ESL-01
MSM514265E/ESL
•
RAS-Only Refresh Cycle
tRC
RAS
CAS
Address
tRAS
VIH
VIL
tRP
tCRP
tRPC
VIH
VIL
tASR tRAH
VIH
Row
VIL
tCEZ
DQ
VOH
Open
VOL
“H” or “L”
Note: WE, OE = “H” or “L”
•
CAS before RAS Refresh Cycle
tRP
RAS
CAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tCEZ
DQ
VOH
VOL
Open
Note: WE, OE, Address = “H” or “L”
13/15
PEDD514265ESL-01
MSM514265E/ESL
•
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRAS
tRCD
tRSH
tCHR
tRAD
VIL
tRAH
VIH
tASC
Row
VIL
tCAH
Column
tRCS
WE
tCAC
VIH
VIL
tRRH
tRAL
tAA
tWRH
tROH
OE
tRP
tRP
VIH
tASR
Address
tRC
tRAS
tWRP
tOEA
VIH
VIL
tOEZ
DQ
VOH
tRAC
Open
VOL
tCLZ
Valid Data-out
“H” or “L”
•
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
WE
tRCD
DQ
tRSH
tRAD
VIL
VIH
VIL
tRP
tRP
tCHR
tRAH
tASC
Row
tCAH
Column
tRAL
tRWL
tWP
VIH
VIL
tWCS
OE
tRAS
VIH
tASR
Address
tRC
tRAS
tWCH
VIH
VIL
VIH
VIL
tDS
tDH
Valid Data-in
“H” or “L”
14/15
PEDD514265ESL-01
MSM514265E/ESL
CAS before RAS Self-Refresh Cycle
tRP
RAS
tRPS
VIH
VIL
tRPC
tCP
CAS
tRASS
tRPC
tCSR
tCHS
VIH
VIL
tCEZ
DQ
VOH
VOL
Open
Note: WE, OE, Address = “H” or “L”
Only SL Version
“H” or “L”
15/15
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