OKI MSM514400E-70TS-K 1,048,576-word x 4-bit dynamic ram : fast page mode type Datasheet

PEDD514400EL-01
This version : Jan. 2001
Semiconductor
MSM514400E/EL
Preliminary
1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM514400E/EL is a 1,048,576-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM514400E/EL achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM514400E/EL is available in a 26/20-pin plastic SOJ, 26/20-pin plastic TSOP. The MSM514400EL (the
low-power version) is specially designed for lower-power applications.
FEATURES
•
1,048,576-word × 4-bit configuration
•
Single 5V power supply, ± 10% tolerance
•
Input
: TTL compatible, low input capacitance
•
Output
: TTL compatible, 3-state
•
Refresh
: 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
•
Fast page mode, read modify write capability
•
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•
Multi-bit test mode capability
•
Package options:
26/20-pin 300mil plastic SOJ
(SOJ26/20-P-300-1.27)
(Product : MSM514400E/EL-xxSJ)
26/20-pin 300mil plastic TSOP
(TSOPII26/20-P-300-1.27-K)
(Product : MSM514400E/EL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
Power Dissipation
Cycle Time
(Min.)
Operating (Max.) Standby (Max.)
tRAC
tAA
tCAC
tOEA
MSM514400E/EL-60
60ns
30ns
15ns
15ns
110ns
468mW
MSM514400E/EL-70
70ns
35ns
20ns
20ns
130ns
413mW
5.5mW/
1.1mW (L-version)
1/14
PEDD514400EL-01
MSM514400E/EL
PIN CONFIGRATION (TOP VIEW)
DQ1
DQ2
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18
17
16
15
14
A8
A7
A6
A5
A4
26/20-Pin Plastic SOJ
DQ1
DQ2
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18
17
16
15
14
A8
A7
A6
A5
A4
26/20-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0–A9
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1–DQ4
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
Note : The same power supply voltage must be provided to every VCC pin, and the
same GND voltage level must be provided to every VSS pin.
2/14
PEDD514400EL-01
MSM514400E/EL
BLOCK DIAGRAM
RAS
Timing
Generator
Timing
Generator
CAS
10
Column
Address
Buffers
10
Internal
Address
Counter
A0-A9
10
Row
Address
Buffers
Refresh
Control Clock
10
Row
Decoders
Word
Drivers
Sense Amplifiers
WE
Write
Clock
Generator
Column
decoders
4
I/O
Selector
OE
4
Output
Buffers
4
Input
Buffers
4
4
4
DQ1-DQ4
4
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/14
PEDD514400EL-01
MSM514400E/EL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VIN, VOUT
− 0.5 to Vcc + 0.5
V
Voltage on VSS Supply Relative to VSS
VCC
− 0.5 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
− 55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0 °C to 70 °C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Notes:
Symbol
Min.
Typ.
Max.
Unit
VCC
VSS
VIH
VIL
4.5
5.0
5.5
V
0
0
0
2.4

− 0.5
*2

V
Vcc + 0.5
*1
0.8
V
V
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(Vcc = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Input Capacitance (A0 – A9)
Input Capacitance (RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ4)
Symbol
Typ.
Max.
Unit
CIN1
CIN2
CI/O

6
pF

7
pF

7
pF
4/14
PEDD514400EL-01
MSM514400E/EL
DC Characteristics
(Vcc = 5V ± 10%, Ta = 0°C to 70°C)
Parameter
Symbol
MSM514400
E/EL-60
MSM514400
E/EL-70
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
V
−10
10
−10
10
µA
−10
10
−10
10
µA

85

75
mA
1, 2
RAS, CAS = VIH

2

2

1
1

mA
RAS, CAS
≥ VCC −0.2V
1

200

200
µA
1,5

85

75
mA
1, 2

5

5
mA
1

85

75
mA
1, 2

70

60
mA
1, 3

300

300
µA
1,4,5
Condition
Output High Voltage
VOH
IOH = −5.0mA
Output Low Voltage
VOL
IOL = 4.2mA
Unit
Note
0V ≤ VI ≤ VCC+0.5V;
Input Leakage Current
ILI
Output Leakage Current
ILO
Average Power Supply
Current
ICC1
(Operating)
Power Supply Current
(Standby)
Average Power Supply
Current
ICC2
(Standby)
DQ disable
0V ≤ VO ≤ 5.5V
RAS, CAS cycling,
tRC = Min.
RAS cycling,
ICC3
(RAS-only Refresh)
Power Supply Current
All other pins not
under test = 0V
CAS = VIH,
tRC = Min.
RAS = VIH,
ICC5
CAS = VIL,
DQ = enable
Average Power Supply
Current
ICC6
(CAS before RAS Refresh)
Average Power Supply
Current
(Battery Backup)
Notes: 1.
2.
3.
4.
5.
CAS before RAS
RAS = VIL,
ICC7
(Fast Page Mode)
Average Power Supply
Current
RAS = cycling,
CAS cycling,
tPC = Min.
ICC10
tRC = 125µs
CAS before RAS
tRAS ≤ 1µs
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC − 0.2V ≤ VIH ≤ VCC + 0.5V, − 0.5V ≤ VIL ≤ 0.2V.
L-version.
5/14
PEDD514400EL-01
MSM514400E/EL
AC Characteristic (1/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
Parameter
Symbol
MSM514400
E/EL-60
MSM514400
E/EL-70
unit
Note
Min.
Max.
Min.
Max.
tRC
110

130

ns
tRWC
155

185

ns
tPC
40

45

ns
tPRWC
85

100

ns
Access Time from RAS
tRAC

60

70
ns
4, 5, 6
Access Time from CAS
tCAC

15

20
ns
4, 5
Access Time from Column Address
tAA

30

35
ns
4, 6
Access Time from CAS Precharge
tCPA

35

40
ns
4
Access Time from OE
tOEA

15

20
ns
4
Output Low Impedance Time from CAS
tCLZ
0

0

ns
4
CAS to Data Output Buffer Turn-off
Delay Time
tOFF
0
15
0
20
ns
7
OE to Data Output Buffer Turn-off Delay
Time
tOEZ
0
15
0
20
ns
7
Transition Time
tT
3
50
3
50
ns
3
Refresh Period
tREF

16

16
ns
Refresh Period (L-version)
tREF

128

128
ms
RAS Precharge Time
tRP
40

50

ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
15

20

ns
RAS Hold Time referenced to OE
tROH
15

20

ns
CAS Precharge Time
(Fast Page Mode)
tCP
10

10

ns
CAS Pulse Width
tCAS
15
10,000
20
10,000
ns
CAS Hold Time
tCSH
60

70

ns
CAS to RAS Precharge Time
tCRP
5

5

ns
RAS Hold Time from CAS Precharge
tRHCP
35

40

ns
RAS to CAS Delay Time
tRCD
20
45
20
50
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
ns
6
Row Address Set-up Time
tASR
0

0

ns
Row Address Hold Time
tRAH
10

10

ns
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
6/14
PEDD514400EL-01
MSM514400E/EL
AC Characteristic (2/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
Parameter
Symbol
MSM514400
E/EL-60
MSM514400
E/EL-70
Min.
Max.
Min.
Max.
unit
Note
Column Address Set-up Time
tASC
0

0

ns
Column Address Hold Time
tCAH
10

15

ns
Column Address to RAS Lead Time
tRAL
30

35

ns
Read Command Set-up Time
tRCS
0

0

ns
Read Command Hold Time
tRCH
0

0

ns
8
Read Command Hold Time referenced
to RAS
tRRH
0

0

ns
8
Write Command Set-up Time
tWCS
0

0

ns
9
Write Command Hold Time
tWCH
10

10

ns
Write Command Pulse Width
tWP
10

10

ns
OE Command Hold Time
tOEH
15

20

ns
Write Command to RAS Lead Time
tRWL
15

20

ns
Write Command to CAS Lead Time
tCWL
15

20

ns
Data-in Set-up Time
tDS
0

0

ns
10
Data-in Hold Time
tDH
10

15

ns
10
OE to Data-in Delay Time
tOED
15

20

ns
CAS to WE Delay Time
tCWD
40

50

ns
9
Column Address to WE Delay Time
tAWD
55

65

ns
9
RAS to WE Delay Time
tRWD
85

100

ns
9
CAS Precharge WE Delay Time
tCPWD
60

70

ns
9
CAS Active Delay Time from RAS
Precharge
tRPC
5

5

ns
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
5

5

ns
RAS to CAS Hold Time
(CAS before RAS)
tCHR
10

10

ns
WE to RAS Precharge time
(CAS before RAS)
tWRP
10

10

ns
WE Hold Time (CAS before RAS)
tWRH
10

10

ns
WE Set-up Time (Test mode)
tWTS
10

10

ns
WE Hold Time (Test mode)
tWRH
10

10

ns
7/14
PEDD514400EL-01
MSM514400E/EL
Notes:
1.
A start-up delay of 200µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2.
The AC characteristics assume tT = 5ns.
3.
VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition
times (tT) are measured between VIH and VIL.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD
(Max.) limit, then the access time is controlled by tCAC.
6.
Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD
(Max.) limit, then the access time is controlled by tAA.
7.
tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8.
tRCH or tRRH must be satisfied for a read cycle.
9.
tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire
cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.),
then the cycle is a read modify write cycle and data out will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at
access time) is indeterminate.
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
8/14
PEDD514400EL-01
MSM514400E/EL
Timing Chart
•
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRAD
VIL
WE
OE
VIH
VIL
tCRP
tRSH
tCAS
VIH
tRAL
tASR
Address
tRCD
tRAH
tASC
Row
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tOEA
VIH
VIL
tCAC
tOFF
tRAC
DQ
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
•
Write Cycle (Early Write)
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
OE
DQ
VIH
VIL
VIH
tCRP
tRSH
tCAS
tRAH
tASC
Row
tCAH
Column
tCWL
tWCS
tWP
tWCH
VIL
tRWL
VIH
VIL
VIH
VIL
tDS
tD
Valid Data-in
Open
“H” or “L”
9/14
PEDD514400EL-01
MSM514400E/EL
•
Read Modify Write Cycle
tRWC
RAS
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRSH
tCAS
VIH
VIH
VIL
tCRP
tRAD
VIL
tASR
Address
tRCD
tRAH
Row
tASC
tCWL
tRWL
tCAH
Column
tRCS
tCWD
tRWD
WE
OE
tWP
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tCAC
tD
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
Valid
Data-in
“H” or “L”
10/14
PEDD514400EL-01
MSM514400E/EL
•
Fast Page Mode Cycle
tRASP
RAS
VIH
VIL
tRCD
tCRP
CAS
tCP
VIH
VIL
VIH
VIL
tRAD
tCSH
tRAH tASC
tCP
Row
tASC
Column
tCAH
Column
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
VIH
VIL
tRAC
tCPA
tOFF
tOEZ
tCLZ
VOH
tAA
tOEA
tCAC
DQ
tASC
tRCS
tRCH
tCRP
tRAL
tCAH
Column
tOEA
OE
tRSH
tCAS
tCAS
tCAH
tRCS
WE
tRHCP
tCAS
tASR
Address
tRP
tPC
tCPA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
VOL
tRRH
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
Valid
Data-out
“H” or “L”
•
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
RAS
CAS
tPC
VIH
VIL
tCRP
VIL
tRAH tASC
Row
tCSH
tCAH
tASC
Column
tCRP
tCAS
VIH
tCAH
tASC
Column
tCWL
tWCH
tWP
Column
tCWL
tWCS
tRAL
tCAH
tWCH
tWP
tCWL
tRWL
tWCS
tWP
tWCH
VIL
tDS
DQ
tCAS
tRSH
tRAD
VIL
VIH
tCP
tCAS
tWCS
WE
tCP
VIH
tASR
Address
tRCD
tRHPC
VIH
VIL
tD
Valid
Data-in
tDS
tD
Valid
Data-in
tDS
tD
Valid
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/14
PEDD514400EL-01
MSM514400E/EL
•
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
CAS
tCSH
VIH
VIL
tRCD
VIL
tCAH
tCWL
tASC
Row
tASC
tRAL
tCWL
Column
tCWD
tRCS
tCPWD
tCWD
tAWD
tAWD
tRCS
tRWD
tCWD
tCPWD
tCWL
tRWL
VIH
tAWD
VIL
tWP
tCPA
tDH
VIH
tWP
tD
tCAC
VI/OH
tOEZ
Out
VI/OL
tCLZ
tCPA
tAA
In
tOEA
tOED
tOEZ
tCAC
tD
tDS
tOEA
tOED
VIL
tWP
tROH
tDS
tAA
tDS
tOEA
Out
tOED
tOEZ
tCAC
In
Out
In
tCLZ
tCLZ
Note: In = Valid Data-in, Out = Valid Data-out
•
tCRP
tCAH
Column
tAA
DQ
tCAS
tASC
Column
tRAC
OE
tCP
tCAS
tRAD
VIL
VIH
tRP
tRSH
tCAH
tRCS
WE
tCP
tCAS
VIH
tRAH
tASR
Address
tPRWC
“H” or “L”
RAS-only Refresh Cycle
tRC
RAS
tRAS
VIH
tRP
VIL
tCRP
CAS
Address
DQ
tRPC
VIH
VIL
VIH
VIL
VOH
VOL
tAS
tRA
Row
tOFF
Open
Note: WE, OE = “H” or “L”
“H” or “L”
12/14
PEDD514400EL-01
MSM514400E/EL
•
CAS before RAS Refresh Cycle
tRP
RAS
CAS
WE
DQ
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tWR
tWR
tWR
VIH
VIL
tOFF
VOH
Open
VOL
Note: WE, OE, Address = “H” or “L”
•
“H” or “L”
Hidden Refresh Read Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRCD
tRSH
VIH
tRAD
VIL
VIH
VIL
tRAH
tASC
tCAH
Column
Row
tRCS
WE
tRP
tRP
tCHR
tASR
Address
tRC
tRAS
tRAS
tCAC
tRRH
VIH
tRAL
VIL
tAA
tROH
OE
DQ
VIH
VIL
VOH
VOL
tOFF
tOEA
tRAC
tOEZ
tCLZ
Open
Valid Data-out
“H” or “L”
13/14
PEDD514400EL-01
MSM514400E/EL
•
Hidden Refresh Write Cycle
tRC
RAS
CAS
VIH
VIL
tCRP
tRCD
tRSH
OE
DQ
tRP
VIH
tRAD
VIL
tRAH
VIH
VIL
tASC
Row
tRAL
tCAH
Column
tWCS
WE
tRP
tCHR
tASR
Address
tRC
tRAS
tRAS
tWCH
VIH
VIL
tWR
tWR
tWP
VIH
VIL
tDS
VIH
tD
Valid Data-in
VIL
“H” or “L”
•
Test Mode Initiate Cycle
tRC
tRP
RAS
CAS
tRAS
VIH
VIL
tRPC
tCP
VIH
tCSR
VIL
tWTS
WE
DQ
tCHR
VIH
VIL
VIH
VIL
tWTH
tOFF
Open
Note: OE, Address = “H” or “L”
“H” or “L”
14/14
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