OKI MSM518128L 131,072-word x 8-bit dynamic ram : fast page mode type Datasheet

E2G0012-17-41
¡ Semiconductor
MSM518128/L
¡ Semiconductor
This version:
Jan. 1998
MSM518128/L
Previous version: May 1997
131,072-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM518128/L is a 131,072-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM518128/L achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer
metal CMOS process. The MSM518128/L is available in a 26/24-pin plastic SOJ. The MSM518128L
(the low-power version) is specially designed for lower-power applications.
FEATURES
• 131,072-word ¥ 8-bit configuration
• Single 5 V power supply, ±5% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package:
26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM518128/L-xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
MSM518128/L-45
45 ns 24 ns 13 ns 13 ns
90 ns
682.5 mW
MSM518128/L-50
50 ns 26 ns 14 ns 14 ns
100 ns
630 mW
MSM518128/L-60
60 ns 30 ns 15 ns 15 ns
120 ns
525 mW
5.25 mW/
1.05 mW (L-version)
1/15
¡ Semiconductor
MSM518128/L
PIN CONFIGURATION (TOP VIEW)
VSS 1
26 VSS
DQ1 2
25 DQ8
DQ2 3
24 DQ7
DQ3 4
23 DQ6
DQ4 5
22 DQ5
WE 6
21 CAS
RAS 8
19 OE
A0 9
18 A8R
A1 10
17 A7
A2 11
16 A6
A3 12
15 A5
VCC 13
14 A4
26/24-Pin Plastic SOJ
Pin Name
A0 - A7, A8R
RAS
Row Address Strobe
CAS
Column Address Strobe
DQ1 - DQ8
Note:
Function
Address Input
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
The same GND voltage level must be provided to every VSS pin.
2/15
¡ Semiconductor
MSM518128/L
BLOCK DIAGRAM
RAS
Timing
Generator
Timing
Generator
CAS
8
Column
Address
Buffers
8
Write
Clock
Generator
Column
Decoders
WE
OE
8
Internal
Address
Counter
A0 - A7
Refresh
Control Clock
Sense
Amplifiers
8
I/O
Selector
A8R
1
Row
Address
Buffers
9
Row
Decoders
Word
Drivers
8
8
8
8
8
Output
Buffers
Input
Buffers
DQ1 - DQ8
8
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/15
¡ Semiconductor
MSM518128/L
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.75
5.0
5.25
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
(VCC = 5 V ±5%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A7, A8R)
CIN1
—
6
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 - DQ8)
CI/O
—
7
pF
4/15
¡ Semiconductor
MSM518128/L
DC Characteristics
Parameter
(VCC = 5 V ±5%, Ta = 0°C to 70°C)
Symbol
Condition
MSM518128 MSM518128 MSM518128
/L-45
/L-50
/L-60
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
130
—
120
—
100
mA 1, 2
—
2
—
2
—
2
—
1
—
1
—
1
—
200
—
200
—
—
130
—
120
—
5
—
—
130
—
—
0 V £ VI £ 6.5 V;
Input Leakage Current
ILI
All other pins not
under test = 0 V
Output Leakage Current
ILO
Average Power
Supply Current
ICC1
(Operating)
DQ disable
0 V £ VO £ 5.25 V
RAS, CAS cycling,
tRC = Min.
RAS, CAS = VIH
Power Supply
Current (Standby)
ICC2 RAS, CAS
≥ VCC –0.2 V
1
200
mA
1, 5
—
100
mA 1, 2
5
—
5
—
120
—
100
mA 1, 2
100
—
90
—
80
mA 1, 3
300
—
300
—
300
mA
RAS cycling,
Average Power
ICC3 CAS = VIH,
Supply Current
(RAS-only Refresh)
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5 CAS = VIL,
ICC6
Supply Current
(CAS before RAS Refresh)
mA
1
DQ = enable
Average Power
RAS cycling,
CAS before RAS
RAS = VIL,
Average Power
ICC7 CAS cycling,
Supply Current
(Fast Page Mode)
tPC = Min.
Average Power
tRC = 125 ms,
ICC10 CAS before RAS,
Supply Current
(Battery Backup)
Notes : 1.
2.
3.
4.
5.
mA
tRAS £ 1 ms
1, 4,
5
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS = VIH.
VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
L-version.
5/15
¡ Semiconductor
MSM518128/L
AC Characteristics (1/2)
(VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3
Parameter
MSM518128 MSM518128 MSM518128
/L-45
/L-50
/L-60
Unit Note
Symbol
Min. Max. Min. Max. Min. Max.
tRC
90
—
100
—
120
—
ns
tRWC
140
—
150
—
170
—
ns
tPC
34
—
36
—
40
—
ns
tPRWC
75
—
77
—
90
—
ns
Access Time from RAS
tRAC
—
45
—
50
—
60
ns
4, 5, 6
Access Time from CAS
tCAC
—
14
—
14
—
15
ns
4, 5
Access Time from Column Address
tAA
—
24
—
26
—
30
ns
4, 6
Access Time from CAS Precharge
tCPA
—
28
—
30
—
35
ns
4
Access Time from OE
tOEA
—
14
—
14
—
15
ns
4
Output Low Impedance Time from CAS
tCLZ
0
—
0
—
0
—
ns
4
CAS to Data Output Buffer Turn-off Delay Time
tOFF
0
10
0
10
0
10
ns
7
OE to Data Output Buffer Turn-off Delay Time
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
tOEZ
0
10
0
10
0
10
ns
7
Transition Time
tT
3
50
3
50
3
50
ns
3
Refresh Period
tREF
—
8
—
8
—
8
ms
Refresh Period (L-version)
tREF
—
64
—
64
—
64
ms
RAS Precharge Time
tRP
35
—
40
—
50
—
ns
RAS Pulse Width
tRAS
45
10,000
50
10,000
60
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
45
100,000
50
100,000
60
100,000
ns
RAS Hold Time
tRSH
14
—
14
—
15
—
ns
RAS Hold Time referenced to OE
tROH
10
—
10
—
10
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
14
10,000
14
10,000
15
10,000
ns
CAS Hold Time
tCSH
45
—
50
—
60
—
ns
CAS to RAS Precharge Time
tCRP
5
—
5
—
5
—
ns
RAS Hold Time from CAS Precharge
tRHCP
28
—
30
—
35
—
ns
RAS to CAS Delay Time
tRCD
17
31
18
36
20
45
ns
5
RAS to Column Address Delay Time
tRAD
12
21
13
24
15
30
ns
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
7
—
8
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
Column Address Hold Time
tCAH
12
—
13
—
15
—
ns
Column Address Hold Time from RAS
tAR
35
—
40
—
50
—
ns
Column Address to RAS Lead Time
tRAL
20
—
26
—
30
—
ns
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
8
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
8
6/15
¡ Semiconductor
MSM518128/L
AC Characteristics (2/2)
(VCC = 5 V ±5%, Ta = 0°C to 70°C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3
Parameter
Symbol
MSM518128 MSM518128 MSM518128
/L-45
/L-50
/L-60
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
Write Command Hold Time
tWCH
12
—
13
—
15
—
ns
Write Command Hold Time from RAS
tWCR
35
—
40
—
50
—
ns
Write Command Pulse Width
tWP
10
—
10
—
10
—
ns
OE Command Hold Time
tOEH
12
—
13
—
15
—
ns
Write Command to RAS Lead Time
tRWL
14
—
14
—
15
—
ns
Write Command to CAS Lead Time
tCWL
14
—
14
—
15
—
ns
Data-in Set-up Time
tDS
0
—
0
—
0
—
ns
10
Data-in Hold Time
tDH
12
—
13
—
15
—
ns
10
Data-in Hold Time from RAS
tDHR
35
—
40
—
50
—
ns
OE to Data-in Delay Time
tOED
12
—
13
—
15
—
ns
CAS to WE Delay Time
tCWD
36
—
38
—
50
—
ns
9
Column Address to WE Delay Time
tAWD
48
—
52
—
60
—
ns
9
RAS to WE Delay Time
tRWD
70
—
75
—
85
—
ns
9
CAS Precharge WE Delay Time
tCPWD
50
—
53
—
60
—
ns
9
CAS Active Delay Time from RAS Precharge
tRPC
0
—
0
—
0
—
ns
RAS to CAS Set-up Time (CAS before RAS)
tCSR
10
—
10
—
10
—
ns
RAS to CAS Hold Time (CAS before RAS)
tCHR
25
—
25
—
30
—
ns
9
7/15
¡ Semiconductor
Notes:
MSM518128/L
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 50 pF.
The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
8/15
E2G0092-17-41E
¡ Semiconductor
MSM518128/L
,
,,
,
,,,,
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCSH
tCRP
tRCD
VIH –
CAS
VIL –
VIH –
VIL –
tRSH
tCAS
tRAD
tASR
Address
tCRP
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
OE
VIH –
VIL –
tAA
tROH
tOEA
VIH –
VIL –
tCAC
tRAC
DQ
tRCH
tRRH
VOH –
tOEZ
Open
VOL –
tOFF
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
CAS
VIH –
VIL –
WE
VIH –
VIL –
tCSH
tRCD
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
tWCH
VIH –
tRWL
VIH –
VIL –
tDS
DQ
tCWL
tWP
VIL –
tWCR
OE
tRAL
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
9/15
,
,,
¡ Semiconductor
MSM518128/L
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH –
VIL –
tRP
tAR
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
10/15
,,,
,
,,,
¡ Semiconductor
MSM518128/L
Fast Page Mode Read Cycle
tRASP
VIH –
RAS V –
IL
VIH –
CAS
VIL –
Address
WE
VIH –
VIL –
tRP
tAR
tCRP
tRHCP
tPC
tRCD
tCP
tASR
tCP
tCAS
tCAS
tRAD
tRAH tASC
tCSH
tCAH
tASC
Column
Row
VIH –
VIL –
tCAC
VOH –
DQ
VOL –
Column
tRCS
tRCH
tRRH
tCPA
tOEA
tOFF
tOEZ
tRCH
tAA
tAA
tCAC
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
tCLZ
tRCS
tCPA
tOEA
tRAC
tRAL
tCAH
tASC
Column
tAA
VIH –
OE
VIL –
tCAS
tCAH
tRCH
tRCS
tCRP
tRSH
tCLZ
tOFF
tOEZ
Valid
Data-out
Valid
Data-out
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tAR
VIH –
RAS V –
IL
tCRP
VIH –
CAS
VIL –
Address
VIH –
VIL –
tRAH tASC
Row
tWCS
tDS
VIH –
VIL –
tCSH
tCAH
Column
tCWL
tWCH
tWP
tRAD
tRHCP
tRSH
tRCD
VIH –
WE
VIL –
DQ
tPC
tCAS
tASR
tRP
tWCR
tDH
Valid Data-in
tDHR
tCP
tCRP
tCP
tCAS
tASC
tCAH
tASC
Column
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
tCAS
tCAH
tRAL
Column
tRWL
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
Note: OE = "H" or "L"
"H" or "L"
11/15
¡ Semiconductor
MSM518128/L
,,,
,
,
,
,
Fast Page Mode Read Modify Write Cycle
tRASP
VIH –
RAS
VIL –
tAR
tRP
tCSH
tPRWC
tRCD
VIH –
CAS
VIL –
tASC
tCAH
tRAH
VIH –
VIL –
tCRP
tCAS
tASC
tCAH
tCAH
Column
Column
tASC
Column
Row
tRCS
tCPWD
tCWD
tRWD
tCWD
tRCS
V
WE IH –
VIL –
tCWL
tAWD
tCWL
tWP
tDH
VI/OH–
VI/OL –
Out
tCLZ
tOEA
tOED
tOEZ
tCAC
In
tDH
tDS
tOEA
tOEZ
tCAC
tWP
tCPA
tAA
tOED
VIH –
OE V –
IL
tCWL
tROH
tWP
tDH
tDS
tOEA
tRWL
tAWD
tCPA
tAA
tAA
tRAL
tRCS
tCPWD
tCWD
tAWD
tDS
tRAC
DQ
tCP
tCAS
tRAD
tASR
Address
tCP
tCAS
tRSH
Out
tOED
In
tCLZ
tOEZ
tCAC
Out
In
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
RAS
VIL –
CAS
Address
VIH –
VIL –
VIH –
VIL –
tRP
tRAS
VIH –
tCRP
tASR
tRPC
tRAH
Row
tOFF
DQ
VOH –
VOL –
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/15
,,
,
,,
¡ Semiconductor
MSM518128/L
CAS before RAS Refresh Cycle
tRC
tRP
RAS
VIH –
VIL –
DQ
tRP
tRPC
tRPC
tCSR
tCP
CAS
tRAS
VIH –
VIL –
tCHR
tOFF
VOH –
VOL –
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRAS
RAS
VIH –
VIL
tRP
tAR
VIH –
VIL –
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
tRAH
tASR
Address
tRAS
tRP
–
tCRP
CAS
tRC
Row
tCHR
tCAH
Column
tRCS
tRAL
VIH –
WE V
IL –
tRRH
tAA
tROH
tOEA
VIH –
OE V
IL –
tRAC
DQ
VOH –
VOL –
tCAC
tCLZ
tOFF
tOEZ
Valid Data-out
"H" or "L"
13/15
,
,,
,
¡ Semiconductor
MSM518128/L
Hidden Refresh Write Cycle
tRC
tRP
tRAS
RAS
VIH –
tRP
tAR
VIH –
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
tRAH
VIL –
tASR
Address
tRAS
VIL –
tCRP
CAS
tRC
tCHR
tCAH t
RAL
Column
Row
tWCS
VIH –
WE V
IL –
tWCH
tWP
tWCR
VIH –
OE V
IL –
tDS
V –
DQ IH
VIL –
tDH
Valid Data-in
tDHR
"H" or "L"
14/15
¡ Semiconductor
MSM518128/L
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/24-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
15/15
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