OKI MSM518205-80 4,194,304-word x 2-bit dynamic ram : fast page mode type with edo Datasheet

E2G0030-17-41
¡ Semiconductor
MSM518205
¡ Semiconductor
This version:MSM518205
Jan. 1998
Previous version: May 1997
4,194,304-Word ¥ 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM518205 is a 4,194,304-word ¥ 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM518205 achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MSM518205 is available in a 26/24-pin plastic SOJ or 26/24-pin plastic
TSOP.
FEATURES
• 4,194,304-word ¥ 2-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 4096 cycles/64 ms
• Fast page mode with EDO, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM518205-xxSJ)
26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM518205-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
MSM518205-60
60 ns 30 ns 15 ns 15 ns
110 ns
385 mW
MSM518205-70
70 ns 35 ns 20 ns 20 ns
130 ns
358 mW
MSM518205-80
80 ns 40 ns 20 ns 20 ns
150 ns
330 mW
5.5 mW
1/18
¡ Semiconductor
MSM518205
PIN CONFIGURATION (TOP VIEW)
VCC 1
26 VSS
VCC 1
26 VSS
DQ1 2
25 NC
DQ1 2
25 NC
DQ2 3
24 CAS1
DQ2 3
24 CAS1
WE 4
23 CAS2
WE 4
23 CAS2
RAS 5
22 OE
RAS 5
22 OE
A11R 6
21 A9
A11R 6
21 A9
A10R 8
19 A8
A10R 8
19 A8
A0 9
18 A7
A0 9
18 A7
A1 10
17 A6
A1 10
17 A6
A2 11
16 A5
A2 11
16 A5
A3 12
15 A4
A3 12
15 A4
VCC 13
14 VSS
VCC 13
14 VSS
26/24-Pin Plastic SOJ
Pin Name
A0 - A9,
A10R, A11R
RAS
Note :
26/24-Pin Plastic TSOP
(K Type)
Function
Address Input
Row Address Strobe
CAS1, CAS2
Column Address Strobe
DQ1, DQ2
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
2/18
¡ Semiconductor
MSM518205
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS1
CAS2
10
Column
Address
Buffers
Write
Clock
Generator
Column
Decoders
10
WE
OE
2
Internal
Address
Counter
A0 - A9
Refresh
Control Clock
Sense
Amplifiers
2
I/O
Selector
A10R, A11R
2
Row
Address
Buffers
12
Row
Decoders
Word
Drivers
2
2
2
2
10
Output
Buffers
Input
Buffers
DQ1, DQ2
2
Memory
Cells
VCC
On Chip
VBB Generator
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
CAS1
CAS2
WE
OE
DQ1
DQ2
H
*
H
*
H
*
*
High-Z
High-Z
Standby
L
High-Z
Refresh
L
L
H
*
L
High-Z
DOUT
High-Z
DQ1 Read
DOUT
DQ2 Read
*
H
L
H
L
H
L
High-Z
L
L
L
H
L
DOUT
DOUT
DQ1, DQ2 Read
L
L
H
L
H
DIN
L
H
L
L
H
Don't Care
Don't Care
DIN
DQ2 Write
L
L
L
L
H
DIN
DIN
DQ1, DQ2 Write
L
L
L
H
H
High-Z
High-Z
—
DQ1 Write
*: "H" or "L"
3/18
¡ Semiconductor
MSM518205
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
Input Capacitance
(A0 - A9, A10R, A11R)
Input Capacitance
(RAS, CAS1, CAS2, WE, OE)
Output Capacitance (DQ1, DQ2)
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
—
6
pF
CIN2
—
7
pF
CI/O
—
10
pF
4/18
¡ Semiconductor
MSM518205
DC Characteristics
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Condition
MSM518205 MSM518205 MSM518205
-60
-70
-80
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
70
—
65
—
60
mA 1, 2
—
2
—
2
—
2
—
1
—
1
—
1
—
70
—
65
—
60
mA 1, 2
—
5
—
5
—
5
mA
—
70
—
65
—
60
mA 1, 2
—
90
—
85
—
80
mA 1, 3
0 V £ VI £ 6.5 V;
Input Leakage Current
ILI
All other pins not
under test = 0 V
Output Leakage Current
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
ILO
DQ disable
0 V £ VO £ 5.5 V
RAS, CAS1, CAS2
ICC1 cycling,
tRC = Min.
RAS, CAS1, CAS2 = VIH
ICC2 RAS, CAS1, CAS2
≥ VCC –0.2 V
Average Power
RAS cycling,
Supply Current
ICC3 CAS1, CAS2 = VIH,
(RAS-only Refresh)
Power Supply
Current (Standby)
RAS = VIH,
ICC5 CAS1, CAS2 = VIL,
1
DQ = enable
RAS cycling,
Supply Current
ICC6 CAS1, CAS2
(CAS before RAS Refresh)
before RAS
Average Power
RAS = VIL,
Supply Current
1
tRC = Min.
Average Power
(Fast Page Mode)
mA
ICC7 CAS1, CAS2 cycling,
tHPC = Min.
Notes : 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS1, CAS2 = VIH.
5/18
¡ Semiconductor
MSM518205
AC Characteristics (1/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Parameter
Symbol
MSM518205 MSM518205 MSM518205
-70
-80
-60
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
110
—
130
—
150
tRWC
155
—
185
tHPC
25
—
30
—
—
205
35
—
—
tHPRWC
85
—
100
—
Access Time from RAS
tRAC
—
60
—
Access Time from CAS
tCAC
Access Time from Column Address
Access Time from CAS Precharge
tAA
tCPA
—
—
15
30
—
—
—
35
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
Data Output Hold After CAS Low
tDOH
CAS to Data Output Buffer Turn-off Delay Time
tCEZ
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
ns
—
ns
ns
105
—
ns
70
—
80
ns
4, 5, 6
20
35
—
—
20
40
ns
ns
4, 5
4, 6
—
40
—
45
ns
4, 15
15
—
—
0
20
—
—
0
20
—
ns
ns
4
4
5
—
5
—
5
—
ns
0
0
15
15
0
0
15
15
0
0
15
15
ns
ns
7, 8
RAS to Data Output Buffer Turn-off Delay Time tREZ
OE to Data Output Buffer Turn-off Delay Time
WE to Data Output Buffer Turn-off Delay Time
tOEZ
tWEZ
0
0
15
15
0
0
15
15
0
0
15
15
ns
ns
7
7
Transition Time
Refresh Period
tT
tREF
2
—
50
64
2
—
50
64
2
—
50
64
ns
ms
3
RAS Precharge Time
tRP
40
—
50
—
60
—
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode with EDO)
tRASP
60
100,000
70
100,000
80
100,000
ns
RAS Hold Time
RAS Hold Time referenced to OE
tRSH
tROH
15
10
—
—
20
10
—
—
20
10
—
—
ns
ns
CAS Precharge Time (Fast Page Mode with EDO)
tCP
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
10
10,000
10
10,000
15
10,000
ns
CAS Hold Time
CAS to RAS Precharge Time
tCSH
—
ns
—
50
10
—
—
45
10
—
tCRP
40
10
—
ns
RAS Hold Time from CAS Precharge
OE Hold Time from CAS (DQ Disable)
tRHCP
tCHO
35
5
—
—
40
10
—
—
45
10
—
—
ns
ns
RAS to CAS Delay Time
RAS to Column Address Delay Time
tRCD
45
30
20
15
50
35
20
15
60
40
ns
tRAD
20
15
RAS to Second CAS Delay Time
tRSCD
60
—
70
—
80
—
ns
Fast Page Mode Read Modify Write
Cycle Time
ns
7, 8
17
15
5
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
14
Column Address Hold Time
tCAH
10
—
15
—
15
—
ns
14
Column Address Hold Time from RAS
tAR
40
—
45
—
50
—
ns
Column Address to RAS Lead Time
tRAL
30
—
35
—
40
—
ns
6/18
¡ Semiconductor
MSM518205
AC Characteristics (2/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Parameter
MSM518205 MSM518205 MSM518205
-60
-70
-80
Unit Note
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
14
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
9, 14
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
9
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
10, 14
Write Command Hold Time
Write Command Hold Time from RAS
tWCH
tWCR
10
45
—
—
15
50
—
—
15
55
—
—
ns
ns
14
Write Command Pulse Width
WE Pulse Width (DQ Disable)
tWP
tWPE
10
5
—
—
10
10
—
—
10
10
—
—
ns
ns
OE Command Hold Time
tOEH
tOEP
—
—
—
—
20
10
10
—
—
—
20
10
10
—
—
ns
ns
ns
OE Precharge Time
OE Command Hold Time
tOCH
15
10
10
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tRWL
tCWL
15
15
—
—
20
20
—
—
20
20
—
—
ns
ns
16
Data-in Set-up Time
Data-in Hold Time
0
15
—
—
0
15
—
—
0
15
—
—
ns
ns
11, 14
11, 14
40
15
—
—
45
20
—
—
50
20
—
—
ns
ns
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
tDS
tDH
tDHR
tOED
tCWD
tAWD
tRWD
40
55
85
—
—
—
50
65
100
—
—
—
50
70
110
—
—
—
ns
ns
ns
10
10
10
CAS Precharge WE Delay Time
tCPWD
60
—
70
—
75
—
ns
10, 15
CAS Active Delay Time from RAS Precharge
tRPC
10
—
10
—
10
—
ns
14
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)
tCSR
tCHR
10
20
—
—
10
20
—
—
10
20
—
—
ns
ns
14
15
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
tWRP
tWRH
tWTS
tWTH
10
10
10
20
—
—
—
—
10
10
10
20
—
—
—
—
10
10
10
20
—
—
—
—
ns
ns
ns
ns
Data-in Hold Time from RAS
OE to Data-in Delay Time
7/18
¡ Semiconductor
Notes:
MSM518205
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated. In a test mode
CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 2 DQ
pins are used, a total of 8 data bits can be written in parallel into the memory array. In
a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data
bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the
memory device returned to its normal operating state by performing a RAS-only
refresh cycle or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
14. These parameters are determined by the falling edge of either CAS1 or CAS2,
whichever is earlier.
15. These parameters are determined by the rising edge of either CAS1 or CAS2,
whichever is later.
16. tCWL should be satisfied by both CAS1 and CAS2.
17. tCP is determined by the time both CAS1 and CAS2 are high.
8/18
¡ Semiconductor
MSM518205
Notes concerning CAS1 and CAS2 control
Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed
under the following conditions:
(1) The timing specification for CAS1 and CAS2 should be met individually.
(2) Different operation modes for CAS1/CAS2 are not allowed (as shown below).
RAS
CAS1
Delayed write
CAS2
Early write
WE
(3) Closely separated CAS1/CAS2 control is not allowed. However, when the condition
(tCP ≤ tUL) is satisfied, fast page mode can be performed.
RAS
CAS1
CAS2
tUL
9/18
E2G0099-17-41L
¡ Semiconductor
MSM518205
,,,
,
,
,,,,
,,
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
tCSH
tCRP
tRCD
VIH –
CAS
VIL –
tRAD
tASR
Address
VIH –
VIL –
tRSH
tCAS
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
OE
VIH –
VIL –
tAA
tROH
tREZ
tOEA
VIH –
VIL –
tCAC
tRAC
DQ
VOH –
tOEZ
Open
VOL –
tRCH
tRRH
tCEZ
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
VIH –
CAS
VIL –
VIH –
VIL –
tCSH
tRCD
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
WE
tRAL
VIH –
VIL –
tWCH
tWP
tCWL
tWCR
tRWL
VIH –
OE
VIL –
tDS
DQ
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
10/18
,,,
¡ Semiconductor
MSM518205
Read Modify Write Cycle
tRWC
tRAS
VIH –
RAS
VIL –
tRCD
tRSH
tCAS
VIH –
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tOEA
tOED
tCAC
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tAWD
tRCS
tRAC
DQ
tCRP
tCSH
tCRP
CAS
tRP
tAR
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
11/18
,,
,,
,
,
¡ Semiconductor
MSM518205
Fast Page Mode Read Cycle (Part-1)
tRASP
RAS
VIH –
VIL –
tAR
tCRP
CAS
WE
tRHCP
tHPC
tRCD
tCP
tCP
tCAS
VIH –
VIL –
tCAS
tCAS
tRAD
tASR
Address
tRP
tRSCD
VIH –
VIL –
tASC
tRAH
Row
tCSH
tCAH
tASC
Column
tASC
tCAH
Column
Column
tRCS
tRRH
VIH –
VIL –
tCHO
DQ
tOCH
tRAC
tAA
OE
tCAH
tOEP
tAA
VIH –
VIL –
tCPA
tOEA
tCAC
VOH –
VOL –
tOEZ
tCAC
Valid
Data-out
Valid
Data-out
tCLZ
tOEA
tOEA
tCAC
tDOH
tOEP
tAA
tOEZ
Valid*
Data-out
* : Same Data,
tREZ
Valid*
Data-out
"H" or "L"
Fast Page Mode Read Cycle (Part-2)
tRASP
RAS
tRSCD
VIH –
VIL –
tAR
VIH –
VIL –
WE
OE
DQ
VIH –
VIL –
VIH –
VIL –
tRCD
tCP
tCAS
tCAS
tRAD
tRAH
tCSH
tASC tCAH
Row
tASC
Column
tCAH
Column
tRCS
tASC
tCAH
Column
tRCS
tRAC
tAA
VIH –
VIL –
VOH –
VOL –
tCRP
tCP
tCAS
tASR
Address
tRHCP
tHPC
tCRP
CAS
tRP
tRCH
tWPE
tAA
tAA
tCPA
tOEA
tCAC
tCLZ
tWEZ
Valid
Data-out
tCAC
tDOH
tCAC
Valid
Data-out
tCEZ
Valid
Data-out
"H" or "L"
12/18
,,,
,
,
¡ Semiconductor
MSM518205
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tRSCD
RAS
VIH –
VIL –
tAR
CAS
tRAD
tRAH
tASR
VIH –
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tASC
Column
tWCS
DQ
tCP
tCAS
tCSH
tASC tCAH
Row
tDHR
tCAS
tCAH
tWCS
tDH
Valid
Data-in
Column
tWCH
tDS
tRSH
tCAH
tASC
Column
tWCH
tDS
VIH –
VIL –
tHPC
tCP
tCAS
VIH –
VIL –
Address
tHPC
tRCD
tCRP
tDH
Valid
Data-in
tWCS
tWCH
tDS
tDH
Valid
Data-in
"H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
tRSCD
RAS
tRWD
VIH –
VIL –
tAR
tCRP
CAS
VIH –
VIL –
VIH –
VIL –
tCWD
tRAD
tASR
Address
tCP
tRCD
Row
tCWL
tCAH
tRCS
tAWD
VIH –
VIL –
tAWD
tDS tWP
VIH –
VIL –
tCAC
VI/OH –
VI/OL –
tOED
tOEZ
Valid
Data-out
tCLZ
tRWL
tCWD
tRAC
tOEA
DQ
tCPA
tCAH
Column
tAA
OE
tASC
Column
tRCS
WE
tCPWD
tHPRWC
tRAH
tASC
tAA
tOEH
tDS
tOED
tOEA
tCAC
tDH
Valid
Data-in
tOEZ
Valid
Data-out
tCLZ
tWP
tOEH
tDH
Valid
Data-in
"H" or "L"
13/18
_
^
]
K
S
R
Q
P
O
N
M
F
:
¡ Semiconductor
MSM518205
RAS-Only Refresh Cycle
t RC
tRP
tRAS
RAS
V IH –
V IL –
tRPC
tCRP
CAS
V IH –
V IL –
tRAH
tASR
Address
V IH –
V IL –
Row
tCEZ
DQ
V OH –
V OL –
Open
Note: WE, OE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC
t RP
RAS
tRP
tRAS
VIH –
VIL –
t RPC
tRPC
tCP
CAS
tCSR
tCHR
tWRP
tWRH
VIH –
VIL –
WE
VIH –
VIL –
DQ
VOH –
VOL –
tWRP
t CEZ
Open
Note: OE, Address = "H" or "L"
"H" or "L"
14/18
,
,,
,,
,
,,
¡ Semiconductor
MSM518205
Hidden Refresh Read Cycle
tRC
tRAS
RAS
CAS
VIH –
VIL –
tCRP
VIH –
VIL –
WE
OE
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
Row
Column
tRCS
tRRH
tRAL
VIH –
VIL –
tAA
tROH
tOEA
VIH –
VIL –
VOH –
VOL –
tCHR
tCAH
tRAH
tCEZ
tCAC
tCLZ
tRAC
DQ
tRP
tAR
tASR
Address
tRC
tRAS
tRP
tOEZ
Open
tREZ
Valid Data-out
"H" or "L"
Hidden Refresh Write Cycle
tRC
tRAS
RAS
CAS
Address
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
VIH –
VIL –
OE
VIH –
VIL –
DQ
VIH –
VIL –
tRP
tAR
tCRP
tASR
tRCD
tRSH
tRAD
tASC
tCAH
tRAH
tCHR
tRAL
Column
Row
tRWL
tWCH
tWCS
WE
tRC
tRAS
tRP
tWP
tWCR
tDS
tDH
Valid Data-in
tDHR
"H" or "L"
15/18
,
¡ Semiconductor
MSM518205
Test Mode Initiate Cycle
tRC
tRP
RAS
VIH –
VIL –
tRPC
tCP
CAS
tRAS
tCSR
VIH –
VIL –
tWTS
WE
tCHR
tWTH
VIH –
VIL –
tOFF
DQ
VOH –
VOL –
Open
Note: OE, Address = "H" or "L"
"H" or "L"
16/18
¡ Semiconductor
MSM518205
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/24-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/18
¡ Semiconductor
MSM518205
(Unit : mm)
TSOPII26/24-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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