E2L0050-29-61 ¡ Semiconductor MSM5416126A ¡ Semiconductor This version: Jun. 1999 MSM5416126A Previous version: Jan. 1998 131,072-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The OKI MSM5416126A is a 128K-word ¥ 16-bit dynamic RAM fabricated in OKI's CMOS silicon gate technology. The MSM5416126A achieves high integration, high-speed operation, and lowpower consumption due to quadruple polysilicon double metal CMOS. The MSM5416126A has conventional two CAS type 256K ¥ 16 DRAM compatible pinout. The MSM5416126A is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. FEATURES • Fast Page Mode with Extended Data Out • Byte wide control: 2 CAS control • 131,072-word ¥ 16-bit organization • Pin compatible with 2 CAS type 256K ¥ 16 DRAM • Single 5 V power supply, ±10% tolerance • CAS before RAS refresh, Hidden refresh, RAS only refresh capability • Refresh: 512 cycles/8 ms • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM5416126A-xxJS) 44/40-pin 400 mil plastic TSOP (Type II) (TSOPII44/40-P-400-0.80-K) (Product : MSM5416126A-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM5416126A-40 Access Time (Max.) tRAC tAA tCAC tOEA 40 ns 22 ns 14 ns 14 ns Cycle Time (Min.) tRC tHPC 75 ns 20 ns Power Dissipation Operating (Max.) Standby (Max.) 770 mW MSM5416126A-45 45 ns 24 ns 14 ns 14 ns 85 ns 20 ns 715 mW MSM5416126A-50 50 ns 26 ns 14 ns 14 ns 100 ns 22 ns 660 mW MSM5416126A-60 60 ns 30 ns 15 ns 15 ns 120 ns 25 ns 605 mW 11 mW 1/22 ¡ Semiconductor MSM5416126A PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS DQ0 2 39 DQ15 DQ1 3 38 DQ14 DQ2 4 37 DQ13 DQ3 5 36 DQ12 VCC 6 35 VSS DQ4 7 34 DQ11 DQ5 8 33 DQ10 DQ6 9 32 DQ9 DQ7 10 31 DQ8 NC 11 30 NC NC 12 29 LCAS WE 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 VCC 20 21 VSS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS 44/40-Pin Plastic TSOP (II) (K Type) 40-Pin Plastic SOJ Pin Name Function Address Input A0 - A8 Row Address : A0 - A8 Column Address : A0 - A7 RAS Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS DQ0 - DQ15 Upper Byte Column Address Strobe Data - Input / Data - Output WE Write Enable OE Output Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/22 ¡ Semiconductor MSM5416126A BLOCK DIAGRAM OE RAS WE Timing Generator I/O Controller LCAS UCAS I/O Controller Burst Address Counter 8 Output Buffers 8 Input Buffers 8 8 Input Buffers 8 8 Output Buffers 8 DQ0 - DQ7 Column Address Buffers 8 8 Internal Address Counter A0 - A8 Refresh Control Clock Row Address Buffers 9 Row Decoders 9 Column Decoders Sense Amplifiers Word Drivers 16 I/O Selector 16 DQ8 - DQ15 Memory Cells 8 VCC On-chip VBB Generator VSS FUNCTION TABLE Input Pin RAS LCAS DQ Pin UCAS WE OE DQ0 - DQ7 DQ8 - DQ15 Function Mode H * * * * High-Z High-Z Standby L H H * * High-Z High-Z Refresh L L H H L Lower Byte Read H L H L DOUT High-Z High-Z L DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don't Care Lower Byte Write L H L L H Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z — * : "H" or "L" 3/22 ¡ Semiconductor MSM5416126A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on Any Pin Relative to VSS VT Ta = 25°C –1.0 to 7.0 V Short Circuit Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature Topr — 0 to 70 °C Storage Temperature Tstg — –55 to 150 °C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit Input Capacitance (A0 - A8) CIN1 — 7 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ0 - DQ15) CI/O — 10 pF Parameter 4/22 ¡ Semiconductor MSM5416126A DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –1.0 mA 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 1.0 mA 0 0.4 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI 0 V £ VI £ 6.5 V ; All other pins not –10 under test = 0 V 10 –10 10 –10 10 –10 10 mA Output Leakage Current ILO DQi Disable –10 0 V £ VO £ 5.5 V 10 –10 10 –10 10 –10 10 mA Average Power Supply Current (Operating) ICC1 RAS, CAS Cycling, tRC = Min. — 140 — 130 — 120 — 110 mA 1, 2 Power Supply Current (Standby) ICC2 RAS, CAS = VIH — 2 — 2 — 2 — 2 Average Power Supply Current (RAS Only Refresh) ICC3 RAS = Cycling, CAS = VIH, tRC = Min. — 140 — 130 — 120 — 110 Power Supply Current (Standby) ICC5 RAS = VIH, CAS = VIL, Dout = Enable — 5 — 5 — 5 — 5 Average Power Supply Current ICC6 (CAS before RAS Refresh) RAS = Cycling, CAS before RAS — 140 — 130 — 120 — 110 mA 1, 2 Average Power Supply Current (Fast Page Mode) RAS = VIL, CAS Cycling, tPC = Min. — 130 — 130 — 120 — 110 mA 1, 3 Notes : ICC7 mA 1 mA 1, 2 mA 1 1. Specified values are obtained with output open. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 5/22 ¡ Semiconductor MSM5416126A AC Characteristics (1/2) Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Symbol MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. — 120 — ns 145 — 165 — ns 22 — 25 — ns — 65 — 80 — ns 45 — 50 — 60 ns 4, 9, 10 — 14 — 14 — 15 ns — 24 — 26 — 30 ns 4, 10 14 — 14 — 14 — 15 ns 26 — 27 — 29 — 34 ns 4, 9, 10 0 — 0 — 0 — 0 — ns tRC 75 — 85 — 100 Read Modify Write Cycle Time tRWC 115 — 130 — Hyper Page Mode Cycle Time tHPC 20 — 20 — Fast Page Mode Read Modify Write Cycle Time tPRWC 60 — 60 Access Time from RAS tRAC — 40 — Access Time from CAS tCAC — 14 Access Time from Column Address tAA — 22 Access Time from OE tOEA — Access Time from CAS Precharge tCPA — Output Low Impedance Time from CAS tCLZ Random Read or Write Cycle Time 4, 9 Data Hold After CAS Low tCOH 3 — 3 — 3 — 3 — ns Output Buffer Turn-off Delay Time tOFF 3 8 3 8 3 8 3 10 ns 5 OE to Data Output Buffer Turn-off Delay Time tOEZ 3 8 3 8 3 8 3 10 ns 5 Transition Time tT 2 35 2 35 2 35 2 35 ns Refresh Period tREF — 8 — 8 — 8 — 8 ms — ns RAS Precharge Time tRP 25 — 30 — 40 — 50 RAS Pulse Width tRAS 40 10,000 45 10,000 50 10,000 60 RAS Pulse Width (Fast Page Mode) tRASP 40 100,000 45 100,000 50 100,000 60 100,000 ns RAS Hold Time tRSH 14 — 14 — 14 — 15 — ns RAS Hold Time referenced to OE tROH 8 — 8 — 10 — 10 — ns — ns 10,000 ns CAS Precharge Time (Fast Page Mode) tCP 5 — 6 — 7 — 8 CAS Pulse Width tCAS 8 10,000 8 10,000 9 10,000 12 CAS Hold Time tCSH 40 — 45 — 50 — 60 — ns CAS to RAS Precharge Time tCRP 5 — 5 — 5 — 5 — ns RAS to CAS Delay Time tRCD 18 26 18 31 20 36 20 45 ns 9 RAS to Column Address Delay Time tRAD 12 18 13 21 15 24 15 30 ns 10 Row Address Set-up Time tASR 0 — 0 — 0 — 0 — ns Row Address Hold Time tRAH 8 — 8 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — 0 — ns 11 Column Address Hold Time tCAH 6 — 6 — 8 — 10 — ns 11 Column Address Hold Time from RAS tAR 30 — 30 — 35 — 45 — ns Column Address to RAS Lead Time tRAL 22 — 24 — 26 — 30 — ns 14 10,000 ns 12 6/22 ¡ Semiconductor MSM5416126A AC Characteristics (2/2) Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Symbol MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — 0 — ns 6, 11 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — 0 — ns Write Command Set-up Time tWCS 0 — 0 — 0 — 0 — ns 8, 11 Write Command Hold Time tWCH 8 — 8 — 9 — 10 — ns Write Command Pulse Width tWP 7 — 8 — 9 — 10 — ns Write Command Hold Time from RAS tWCR 30 — 30 — 35 — 45 — ns OE Command Hold Time tOEH 8 — 8 — 9 — 10 — ns 11 6 11 Write Command to CAS Lead Time tCWL 7 — 8 — 9 — 12 — ns Write Command to RAS Lead Time tRWL 14 — 14 — 14 — 15 — ns Output Buffer Turn-off Delay Time from WE tWEZ 3 15 3 15 3 15 3 15 ns 5 Output Buffer Turn-off Delay Time from CAS tCEZ 3 8 3 8 3 8 3 10 ns 5 Data to CAS Delay Time tDZC 0 — 0 — 0 — 0 — ns Data to OE Delay Time tDZO 0 — 0 — 0 — 0 — ns Data-in Set-up Time tDS 0 — 0 — 0 — 0 — ns 7, 11 13 Data-in Hold Time tDH 7 — 8 — 9 — 10 — ns 7, 11 Data-in Hold Time referenced to RAS tDHR 30 — 30 — 35 — 45 — ns OE to Data-in Delay Time tOED 8 — 8 — 8 — 10 — ns CAS to WE Delay Time tCWD 28 — 30 — 32 — 35 — ns 8 Column Address to WE Delay Time tAWD 38 — 40 — 44 — 50 — ns 8 RAS to WE Delay Time tRWD 60 — 65 — 70 — 80 — ns 8 OE "L" to CAS "H" Lead Time tOCH 10 — 10 — 10 — 10 — ns CAS "H" to OE "L" Lead Time tCHO 10 — 10 — 10 — 10 — ns Hi-Z Command Pulse Width tOEP 10 — 10 — 10 — 10 — ns CAS Active Delay Time from RAS Precharge tRPC 0 — 0 — 0 — 0 — ns 11 RAS to CAS Set-up Time (CAS before RAS) tCSR 10 — 10 — 10 — 10 — ns 11 RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 10 — 10 — 10 — ns 12 7/22 ¡ Semiconductor Notes: MSM5416126A 1. An initial pause of 200 ms is required after power-up, followed by any 8 RAS cycles. (Example : RAS-only-refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. Output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. tCEZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 6. tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to UCAS, LCAS, leading edge in an early write cycle, and to WE leading edge in an OE control write cycle or a read modify write cycle. 8. tWCS, tCWD, tRWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.) and tAWD ≥ tAWD (Min.) , the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 11. These parameters are determined by the falling edge of UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high. 15. Input levels at the AC testing are 3.0 V/0.5 V. 8/22 ¡ Semiconductor MSM5416126A , ,, TIMING WAVEFORM Read Cycle (RAS Output Control) tRC tRP tRAS RAS tCRP tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tRCS tRRH WE tROH tOEZ tOEA OE tCAC tCEZ tAA DQ0 - 7 Open Valid Data tRAC DQ8 - 15 Open Valid Data "H" or "L" 9/22 ¡ Semiconductor MSM5416126A , ,, Read Cycle (CAS Output Control) tRC tRP tRAS RAS tCRP tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tRCS tRRH WE tROH tOEZ tOEA OE tCAC tCEZ tAA DQ0 - 7 Open Valid Data tRAC DQ8 - 15 Open Valid Data "H" or "L" 10/22 ¡ Semiconductor MSM5416126A , ,, , ,, Early Write Cycle (LCAS and UCAS Active) tRC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tCWL tRWL tWP WE tWCR tWCS tWCH OE tDHR tDS DQ0 - 7 Valid Data tDS DQ8 - 15 tDH tDH Valid Data "H" or "L" 11/22 ¡ Semiconductor MSM5416126A , ,, , ,, Late Write Cycle (LCAS and UCAS Active) tRC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH Row tRAL tASC tCAH Column tCWL tRWL tRCS tWP WE tWCR tOEH OE tOED tDH Valid Data DQ0 - 7 tOED DQ8 - 15 tDS tDS tDH Valid Data "H" or "L" 12/22 ¡ Semiconductor MSM5416126A , ,, ,, ,, Read Modify Write Cycle (LCAS and UCAS Active) tRWC tRP tRAS RAS tCSH tCRP tRCD UCAS LCAS tRSH tCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tAWD tCWL tRWL tWP tRCS WE tRWD tCWD tDZO tOEA tOEZ tOEH OE tOED tCAC tDZC tDS tCLZ Out DQ0 - 7 tDH In tRAC tCLZ DQ8 - 15 tDS Out tDH In "H" or "L" 13/22 ¡ Semiconductor MSM5416126A Fast Page Mode Read Cycle with Extended Data Out tRASP tRP RAS tCSH tHPC tRSH , , tCRP tCP tCP tCAS UCAS LCAS tCAS tCAS tRAD tASR A0 - A8 tRCD Row tRAH tAR tASC tCAH Column tASC tASC tCAH Column tRAL tCAH Column tRCH tRCS WE tAA tRRH tOEA OE tCAC tCAC tCOH DQ0 - 7 Open tRAC DQ8 - 15 Open tCAC tCOH tOFF tOEZ Valid Data tCPA tAA Valid Data tCPA tAA Valid Data Valid Data Valid Data Valid Data "H" or "L" 14/22 tCSH tCRP tRCD UCAS LCAS tHPC tRSH tCP tCAS tCP tCRP tCP tCAS tCAS tCAS tRAL tRAD , tASR tRAH A0 - A8 tASC Row tCAH tASC tCAH tASC tCAH tASC tCAH Column Column Column Column tRRH tRCS tRCH tRCS tRCH ¡ Semiconductor tAR RAS Fast Page Mode Read High-Z Operation tRP tRASP WE tRAC tCHO tOEA tCAC tOEP tAA OE tCAC tCOH tWP tOEP tCAC tCPA tAA tOCH tAA tOEZ tOEA tCAC tOEZ tOEA tWEZ tAA tCEZ Open Valid Data Valid Data Valid* Data Valid* Data Valid Data DQ8 - 15 Open Valid Data Valid Data Valid* Data Valid* Data Valid Data 15/22 * : Same Data, "H" or "L" MSM5416126A DQ0 - 7 ¡ Semiconductor MSM5416126A Fast Page Mode Early Write Cycle tRASP tRP RAS ,,, , ,, tCRP tCSH tCAS tCAS tAR tCAH tRAD tASR tRAH tASC Row tRAL tASC Column tWCS tWP tWCH tCAH Column tCWL WE tRSH tCP tCP tCAS UCAS LCAS A0 - A8 tHPC tRCD tASC Column tCWL tWCS tWP tWCH tCAH tCWL tWCS tWP tWCH OE tDS DQ0 - 7 Input Data tDS DQ8 - 15 tDH tDH Input Data tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data tDS tDH Input Data "H" or "L" 16/22 ¡ Semiconductor MSM5416126A Fast Page Mode Read Modify Write Cycle , , , , tRP tRASP tAR RAS tCSH tCRP tRCD tCAS tPRWC tCAS tCP tRSH tCAS tCP UCAS LCAS tRAD tASR tRAH A0 - A8 tCAH tASC Row tCAH tASC Column tAWD tCWD tWP tOEA tCWL tAWD tCWD tRCS Column tCWL tAWD WE tASC Column tCWL tRAL tCAH tCWD tWP tOEA tOEZ tWP tOEA tOEZ tOEZ OE tRAC tCAC tAA tCLZ DQ0 - 7 tDS Out tRAC DQ8 - 15 tCAC tDH tCAC tAA tCLZ tAA tDS tCLZ In Out tDH tCAC tAA tDS tDS Out tCAC tDH In tCLZ Out tCLZ In tDS Out tDH In tDH tAA In tDH tCAC tAA tDS tCLZ Out In "H" or "L" 17/22 , ,,, ¡ Semiconductor MSM5416126A CAS before RAS Refresh Cycle tRC tRP tRAS tRP RAS tRPC UCAS LCAS tCSR tRPC tCHR Inhibit Falling Transition A0 - A8 WE OE tOFF Open DQ0 - 7 tOFF DQ8 - 15 Open "H" or "L" 18/22 ¡ Semiconductor MSM5416126A Hidden Refresh Cycle , ,, , , tRC tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR UCAS LCAS tAR tRAD tASR A0 - A8 tRAH tRAL tASC Row tCAH Column tRRH tRCS WE tROH tOEZ tOEA OE tRAC tOFF tCAC tAA DQ0 - 7 Open Valid Data tRAC tCAC tAA DQ8 - 15 Open tOFF Valid Data "H" or "L" 19/22 ,,,, ¡ Semiconductor MSM5416126A RAS Only Refresh Cycle tRC tRAS tRP RAS tRPC tCRP UCAS LCAS A0 - A8 tASR tRAH Row WE OE DQ0 - 7 Open DQ8 - 15 Open "H" or "L" 20/22 ¡ Semiconductor MSM5416126A PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/22 ¡ Semiconductor MSM5416126A (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22/22 E2Y0002-29-11 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan