OKI MSM7579RS Single rail codec Datasheet

E2U0017-28-81
This
version: Aug. 1998
MSM7578H/7578V/7579
Previous version: Nov. 1996
¡ Semiconductor
MSM7578H/7578V/7579
¡ Semiconductor
Single Rail CODEC
GENERAL DESCRIPTION
The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
particularly optimized for telephone terminals in digital wireless systems and ISDN systems.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.
FEATURES
• Single power supply: +5.0 V ±5%
• Low power consumption
Operating mode:
25 mW Typ. 47 mW Max. VDD = 5 V
Power down mode:
0.05 mW Typ. 0.3 mW Max. VDD = 5 V
• ITU-T Companding law
MSM7578H:
m-law
MSM7579:
A-law
MSM7578V:
m/A-law pin-selectable
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Built-in reference voltage supply
• Directly drive a line transformer of 600 W
• The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/
7509B
• The 20-pin SSOP package products have 1/3 the foot print of conventional products
• Package options:
16-pin plastic DIP (DIP16-P-300-2.54)
(Product name : MSM7578HRS)
(Product name : MSM7579RS)
(Product name : MSM7578VRS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7578HGS-K)
(Product name : MSM7578VGS-K)
(Product name : MSM7579GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)
(Product name : MSM7579MS-K)
(Product name : MSM7578VMS-K)
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¡ Semiconductor
MSM7578H/7578V/7579
BLOCK DIAGRAM
AIN–
AIN+
–
+
RC
LPF
8th
BPF
PCMOUT
AD
CONV.
TCONT
AUTO
ZERO
PLL
GSX
BCLK
SGC
SG
AOUT
XSYNC
SG
GEN
VR
GEN
5th
LPF
–
+
RTIM
DA
CONV.
RCONT
PWD
PWD
Logic
SG
RSYNC
(ALAW)
PCMIN
PDN
VDD
AG
DG
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¡ Semiconductor
MSM7578H/7578V/7579
PIN CONFIGURATION (TOP VIEW)
SGC 1
16 AIN+
SGC 1
24 AIN+
SGC 1
20 AIN+
SG 2
15 AIN–
NC 2
23 AIN–
SG 2
19 AIN–
AOUT 3
14 GSX
SG 3
22 NC
AOUT 3
18 GSX
VDD 4
13 (ALAW)*
NC 4
21 GSX
VDD 4
17 (ALAW)*
DG 5
12 AG
20 NC
NC 5
16 NC
AOUT 5
11 BCLK
VDD 6
19 (ALAW)*
NC 6
15 NC
RSYNC 7
10 XSYNC
DG 7
18 AG
DG 7
14 AG
PCMIN 8
9 PCMOUT
NC 8
17 NC
PDN 8
NC 9
16 BCLK
RSYNC 9
12 XSYNC
15 NC
PCMIN 10
11 PCMOUT
PDN 6
16-Pin Plastic DIP
PDN 10
RSYNC 11
14 XSYNC
PCMIN 12
13 PCMOUT
13 BCLK
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7578VRS/MSM7578VGS-K/MSM7578VMS-K.
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¡ Semiconductor
MSM7578H/7578V/7579
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
C1
R2
Analog input
R1
GSX
AIN–
AIN+
SG
–
+
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
Gain = R2/R1 £ 10
2) Non inverting input type
C2
AIN+
AIN–
GSX
Analog input
R5
R4
R3
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
Gain = 1 + R4 / R3 £ 10
AG
Analog signal ground.
AOUT
Analog output.
The output signal has a maximum amplitude of 2.4 VPP above and below the signal ground
voltage (VDD/2).
The output load resistance is a minimum of 600 W.
During power saving, or power down mode, the output of AOUT is at the voltage level of the
signal ground.
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¡ Semiconductor
MSM7578H/7578V/7579
VDD
Power supply for +5 V.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the
power saving state.
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power saving
state.
5/18
¡ Semiconductor
MSM7578H/7578V/7579
DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7579 (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT
Input/Output Level
MSM7578H (m-law)
MSD
MSM7579 (A-law)
MSD
+Full scale
1 0 0 0
0 0 0 0
1 0 1 0
1 0 1 0
+0
1 1 1 1
1 1 1 1
1 1 0 1
0 1 0 1
–0
0 1 1 1
1 1 1 1
0 1 0 1
0 1 0 1
–Full scale
0 0 0 0
0 0 0 0
0 0 1 0
1 0 1 0
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¡ Semiconductor
MSM7578H/7578V/7579
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down mode.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input of the companding law selection.
Provides only for the MSM7578VRS/7578VGS-K/7578VMS-K. The CODEC will operate in the
m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin
is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is
internally pulled down.
7/18
¡ Semiconductor
MSM7578H/7578V/7579
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Power Supply Voltage
Parameter
VDD
—
0 to 7
V
Analog Input Voltage
VAIN
—
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
—
–0.3 to VDD + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supply Voltage
VDD
Operating Temperature
Ta
Condition
Voltage must be fixed
—
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
–30
+25
+85
°C
—
—
2.4
VPP
2.2
—
VDD
V
0
—
0.8
V
Analog Input Voltage
VAIN
Input High Voltage
VIH
Input Low Voltage
VIL
Clock Frequency
FC
BCLK
Sync Pulse Frequency
FS
XSYNC, RSYNC
6.0
8.0
9.0
kHz
Clock Duty Ratio
DC
BCLK
40
50
60
%
Digital Input Rise Time
tIr
XSYNC, RSYNC, BCLK,
—
—
50
ns
Digital Input Fall Time
tIf
PCMIN, PDN, ALAW
—
—
50
ns
tXS
BCLKÆXSYNC, See Timing Diagram
100
—
—
ns
tSX
XSYNCÆBCLK, See Timing Diagram
100
—
—
ns
tRS
BCLKÆRSYNC, See Timing Diagram
100
—
—
ns
tSR
RSYNCÆBCLK, See Timing Diagram
100
—
—
ns
Sync Pulse Width
tWS
XSYNC, RSYNC
1 BCLK
—
100
ms
PCMIN Set-up Time
tDS
—
100
—
—
ns
Connect AIN– and GSX
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
64, 128, 256, 512, 1024,
kHz
2048, 96, 192, 384, 768,
1536, 1544, 200
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
PCMIN Hold Time
Digital Output Load
tDH
—
100
—
—
ns
RDL
Pull-up resistor
0.5
—
—
kW
CDL
—
—
—
100
pF
Transmit gain stage, Gain= 1
–100
—
+100
mV
Transmit gain stage, Gain = 10
–10
—
+10
mV
XSYNC, RSYNC, BCLK
—
—
1
ms
Analog Input Allowable DC Offset
Voff
Allowable Jitter Width
—
8/18
¡ Semiconductor
MSM7578H/7578V/7579
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Symbol
IDD1
Power Supply Current
IDD2
IDD3
Condition
Min.
Typ.
Max.
Unit
Operating mode, No signal
—
5
9
mA
Power-down mode, PDN = 0
—
0.01
0.05
mA
—
1.2
3.0
mA
V
Power-save mode, PDN = 1,
XSYNC Æ OFF
Input High Voltage
VIH
—
2.2
—
VDD
Input Low Voltage
VIL
—
0.0
—
0.8
V
High Level Input Leakage Current
IIH
—
—
—
2.0
mA
Low Level Input Leakage Current
IIL
Digital Output Low Voltage
VOL
—
Pull-up resistance > 500 W
—
—
0.5
mA
0.0
0.2
0.4
V
Digital Output Leakage Current
IO
—
—
—
10
mA
Input Capacitance
CIN
—
—
5
—
pF
Analog Input Resistance
RIN
—
10
—
MW
AIN+, AIN–
Transmit Analog Interface Characteristics
(VDD = +5 V to ±5%, Ta = –30°C to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Resistance
RINX
AIN+, AIN–
10
—
—
MW
Output Load Resistance
RLGX
GSX with respect to SG
20
—
—
kW
Output Load Capacitance
CLGX
—
—
30
pF
–1.2
—
+1.2
V
–20
—
+20
mV
Output Amplitude
VOGX
Offset Voltage
VOSGX
Gain = 1
Receive Analog Interface Characteristics
(VDD = +5 V to ±5%, Ta = –30°C to +85°C)
Parameter
Output Load Resistance
Symbol
Condition
Min.
Typ.
Max.
Unit
0.6
—
—
kW
—
—
50
pF
–1.2
—
+1.2
V
—
+100
mV
RLAO
AOUT with respect to SG
Output Load Capacitance
CLAO
AOUT with respect to SG
Output Amplitude
VOAO AOUT with respect to SG
Offset Voltage
VOSAO AOUT with respect to SG
–100
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¡ Semiconductor
MSM7578H/7578V/7579
AC Characteristics
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Transmit Frequency Response
Receive Frequency Response
Loss T1
Freq.
(Hz)
60
Loss T2
300
Loss T3
1020
Loss T4
2020
Loss T5
Loss T6
Symbol
Receive Signal to Distortion Ratio
Receive Gain Tracking
Typ.
Max.
20
26
—
dB
–0.15
+0.07
+0.20
dB
Reference
0
Unit
dB
–0.04
+0.20
dB
3000
–0.15
+0.06
+0.20
dB
3400
0
0.4
0.80
dB
Loss R1
300
–0.15
–0.03
+0.20
dB
Loss R2
1020
Loss R3
2020
Loss R4
Loss R5
Reference
0
dB
–0.15
–0.02
+0.20
dB
3000
–0.15
+0.15
+0.20
dB
3400
0.0
0.4
0.80
dB
SD T1
3
35
43
—
SD T2
0
35
41
—
35
38
—
SD T4
–30
1020
*1
*2
–40
*2
29
30
27
—
–45
SD R1
3
36
43
—
SD R2
0
36
41
—
SD R3
–30
36
40
—
30
33.5
SD R4
1020
–40
SD R5
–45
GT T1
3
GT T3
*1
*2
*2
24
31
SD T5
GT T2
Transmit Gain Tracking
Min.
–0.15
SD T3
Transmit Signal to Distortion Ratio
Level Condition
(dBm0)
29
32
25
30
24
27
–0.3
+0.01
—
—
—
+0.3
–40
–0.3
0
+0.3
GT T4
–50
–0.6
–0.13
+0.6
GT T5
–55
–1.2
–0.15
+1.2
GT R1
3
–0.3
0
+0.3
GT R2
–10
–0.3
+0.10
+0.3
GT R4
–50
–0.6
+0.20
+0.6
GT R5
–55
–1.2
+0.25
+1.2
1020
dB
Reference
–40
GT R3
dB
Reference
–10
1020
26
dB
dB
*1 Psophometric filter is used
*2 Upper is specified for the MSM7578H, lower for the MSM7579
10/18
¡ Semiconductor
MSM7578H/7578V/7579
AC Characteristics (Continued)
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Idle Channel Noise
Symbol
Freq.
(Hz)
Nidle T
—
Nidle R
—
Level Condition
(dBm0)
AIN = SG
—
*1 *2
—
*1 *3
VDD = 5.0 V
AV T
Absolute Level (Initial Difference)
(Deviation of Temperature and Power)
—
Typ.
Max.
–72.5
–70
AV Tt
1020
0
VDD = +5 V
±5%
Ta = –30
AV Rt
to 85°C
Unit
dBmOp
–70.5
–68
—
–78
–75
0.5803
0.6007
0.6218
0.5803
0.6007
0.6218
–0.2
—
+0.2
dB
–0.2
—
+0.2
dB
—
—
0.60
ms
—
0.19
0.75
—
0.11
0.35
—
0.02
0.125
Vrms
Ta = 25°C
AV R
Absolute Level
Min.
A to A
Absolute Delay
Td
1020
tgd T1
500
0
BCLK
= 64 kHz
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
*1
*2
*3
*4
*4
tgd T2
600
tgd T3
1000
tgd T4
2600
—
0.05
0.125
tgd T5
2800
—
0.07
0.75
tgd R1
500
—
0.00
0.75
tgd R2
600
—
0.00
0.35
tgd R3
1000
—
0.00
0.125
tgd R4
2600
—
0.09
0.125
tgd R5
2800
—
0.12
0.75
TRANS Æ RECV
75
85
—
RECV Æ TRANS
70
80
—
CR T
CR R
1020
0
*4
0
0
ms
ms
dB
Psophometric filter is used
Upper is specified for the MSM7578H, lower for the MSM7579
MSM7578H: All "1", MSM7579: "11010101"
Minimum value of the group delay distortion
11/18
¡ Semiconductor
MSM7578H/7578V/7579
AC Characteristics (Continued)
(VDD = +5 V ±5%, Ta = –30°C to +85°C)
Parameter
Discrimination
Out-of-band Spurious
Intermodulation Distortion
Power Supply Noise Rejection Ratio
Freq.
Level Condition
(Hz)
(dBm0)
0 to
4.6 kHz to
DIS
0
4000 Hz
72 kHz
Symbol
S
IMD
300 to
0
3400
fa = 470
–4
fb = 320
PSR T
0 to
PSR R
50 kHz
50 mVPP
tSD
Digital Output Delay Time
tXD1
tXD2
CL = 100 pF
tXD3
4.6 kHz to
100 kHz
2fa – fb
*5
Min.
Typ.
Max.
Unit
30
32
—
dB
—
–37.5
–35
dBmO
—
–52
–35
dBmO
—
30
—
dB
20
—
200
20
—
200
20
—
200
20
—
200
ns
*5 The measurement under idle channel noise
12/18
,
,
¡ Semiconductor
MSM7578H/7578V/7579
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
1
2
tXS
XSYNC
4
5
6
7
8
9
10
11
9
10
11
tSX
tWS
tXD1
PCMOUT
3
tSD
MSD
D2
tXD2
D3
D4
D5
D6
tXD3
D8
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1.
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD.
Receive Timing
BCLK
1
tRS
RSYNC
2
3
4
6
7
8
tSR
tWS
tDS
PCMIN
5
MSD
D2
tDH
D3
D4
D5
D6
D7
D8
13/18
¡ Semiconductor
MSM7578H/7578V/7579
APPLICATION CIRCUIT
Analog interface
Digital interface
MSM7578H/7579
Analog input
AIN–
PCMOUT
1 kW
5V
PCM signal output
GSX
AOUT
Analog output
AIN+
PCMIN
BCLK
PCM data input
PCM Shift Clock input
SG
0.1 mF
XSYNC
8 kHz SYNC signal input
SGC
AG
DG
0V
–
+
+5 V
0 to 10 W
10 mF
1 mF
VDD
RSYNC
PDN
Power Down control input
"1" = Operation
"0" = Power down
The analog output signal has an amplitude of ±1.2 V above and below the offset voltage level of
VDD/2.
14/18
¡ Semiconductor
MSM7578H/7578V/7579
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.
15/18
¡ Semiconductor
MSM7578H/7578V/7579
PACKAGE DIMENSIONS
(Unit : mm)
DIP16-P-300-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.99 TYP.
16/18
¡ Semiconductor
MSM7578H/7578V/7579
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/18
¡ Semiconductor
MSM7578H/7578V/7579
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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