OKI MSM7732-01TB Audio codec Datasheet

OKI Semiconductor
MSM7732-01
FEDL7732-01-10
Issue Date: Nov. 2, 2005
Audio CODEC
GENERAL DESCRIPTION
The MSM7732 is a single-channel full duplex CODEC CMOS IC which performs mutual transcoding between the
analog voice band signals and 64 kbps PCM serial data.
This device performs such functions as DTMF tone and several types of tone generation, transmit/receive data
mute and gain control, and side tone path.
FEATURES
· Single 3 V power supply operation
VDD: 2.4 V to 3.3 V
· PCM interface data format : µ-law/A-law/linear (2’s complement) selectable
· PCM interface timing : long frame synchronous timing/short frame synchronous timing
· Full-duplex single channel operation
· Serial PCM transmission data rate: 64 kbps to 2048 kbps
· Low power consumption
Operating mode: 15 mW typ. (VDD = 3.0 V)
Power-down mode: 3 µW typ. (VDD = 3.0 V)
· Master clock frequency: 2.048 MHz
· Analog output stage
35 mW drive for receiver speaker (differential drive of 32 Ω)--Gain adjustable
66 mW drive for receiver speaker (differential drive of 30 Ω)--Gain adjustable
6.6 mW drive for earphone speaker (single drive of 32 Ω) --Gain adjustable
· Transmit/receive mute, transmit/receive programmable gain control
· Side tone path with programmable attenuation (8-step adjustment level)
· Built-in DTMF tone generator
· Built-in various ringing/function tone generator
· Built-in various ring back tone generator
· Serial MCU interface control: 3 bit
· Built-in transmit voice signal detector
· Built-in op amps and analog switches for various analog interface
· Package options :
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (MSM7732-01 MB)
48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (MSM7732-01 TB)
48-pin plastic LGA (P-TFLGA48-0707-0.8) (MSM7732-01 LB)
48-pin plastic BGA (P-LFBGA48-0707-0.8) (MSM7732-01 LA)
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MSM7732-01
BLOCK DIAGRAM
AMPAI
AMPAO
Voice
Detect
20 kΩ
AIN–
AIN+
GSX
AOUT–
PWI
VFRO
8.8 mW
SAO
for earphone
CR0-B2
CR4-B6
BPF
20 kΩ
CR2-B7
TX ON/OFF
PCM
Compand
–1
CR3-B7, 6, 5
off,–15 to –3 dB
2 dB step
32Ω
20 kΩ
LPF
D/A
32 Ω
to MCUI/F
CR4-B5
SWA
SWB
SWC
PCMOUT
CR0-B0
CR2-B6, 5, 4
–6 to +8 dB
2 dB step
32Ω
AOUT+
35 mW
for receiver
Slope
Filter
A/D
TONE
GEN.
CR3-B3, 2, 1, 0
–36 to –6 dB
2 dB step CR2-B3
RX ON/OFF
CR2-B2, 1, 0 CR1-B0
-12 to +9 dB Through
(0 dB loss)
3 dB step
or -12 loss
CR0-B0
PCM
Expand
PCMIN
CR1-B1
SWD
SWE
SG
VREF
BCLK
SYNC
EXCK
DEN
DIO
PDN
MCK
DG
VDD
AG2
AG1
MCU I/F
VA
Microphone
amp input
AMPA
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OKI Semiconductor
MSM7732-01
PIN CONFIGURATION (TOP VIEW)
1
30
2
29
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
11
20
12
19
13
18
14
17
15
16
DG
MCK
DEN
DIO
EXCK
PCMOUT
PCMIN
SYNC
BCLK
PDN
AG2
AOUT+
AOUT–
PWI
VA
37 NC
38 DIO
39 DEN
40 MCK
41 DG
42 NC
43 NC
44 VDD
45 SWA
46 SWB
47 SWC
48 NC
30-Pin Plastic SSOP
NC 1
36 NC
AMPAI 2
35 EXCK
AMPAO 3
34 PCMOUT
AIN+ 4
33 PCMIN
AIN– 5
32 SYNC
GSX 6
31 NC
NC 7
30 BCLK
NC 8
29 PDN
SWD 9
28 NC
SWE 10
27 AG2
NC 24
AOUT+ 23
AOUT– 22
NC 21
PWI 20
VA 19
SAO 18
NC 17
25 NC
AG1 16
NC 12
VFRO 15
26 NC
NC 14
SG 11
NC 13
VDD
SWA
SWB
SWC
AMPAI
AMPAO
AIN+
AIN–
GSX
SWD
SWE
SG
VFRO
AG1
SAO
NC: No Connection
48-Pin Plastic TQFP
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MSM7732-01
8
7
6
4
3
2
1
PWI
VA
SAO
AG1
VFRO
NC
NC
NC
SG
SWE
H
AG2
G
PDN
NC
BCLK
NC
NC
SWD
SYNC
NC
NC
GSX
PCMIN
NC
NC
AIN-
PCMOUT
NC
NC
AIN+
EXCK
DIO
NC
NC
NC
NC
NC
AMPAO
DEN
MCK
DG
VDD
SWA
SWB
SWC
AMPAI
F
E
D
C
B
A
AOUT+ AOUT-
5
NC
Index (A1)
NC: No Connection
48-Pin Plastic LGA
48-Pin Plastic BGA
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MSM7732-01
PIN DESCRIPTION
Pin
Symbol
Type
1
VDD
—
Power supply (3.0 V)
Description
2
SWA
IO
Analog switch A
3
SWB
IO
Analog switch B
4
SWC
IO
Analog switch C
5
AMPAI
I
6
AMPAO
O
Amplifier A output
7
AIN+
I
Transmit side amplifier non-inverting input
8
AIN–
I
Transmit side amplifier inverting input
Amplifier A inverting input
9
GSX
O
Transmit side amplifier output
10
SWD
IO
Analog switch D
11
SWE
IO
Analog switch E
12
SG
O
Analog signal ground (1.4 V)
13
VFRO
O
Receive side voice output
14
AG1
—
Analog ground 1 (0 V)
15
SAO
O
Receive side sounder amplifier output
16
VA
—
17
PWI
I
Receive side voice amplifier input
18
AOUT–
O
Receive side voice amplifier output –
19
AOUT+
O
Receive side voice amplifier output +
20
AG2
—
Analog ground 2 (0 V)
21
PDN
I
Analog power supply (3.0 V)
Power down control input
22
BCLK
I
PCM data shift clock input
23
SYNC
I
PCM data shift sync signal input
24
PCMIN
I
Receive side PCM signal input
25
PCMOUT
O
Transmit side PCM signal output
26
EXCK
I
27
DIO
IO
28
DEN
I
29
MCK
I
30
DG
—
Clock signal input for control register
Address and data input or output for control register
Enable signal input for control register
Master clock input (2.048 MHz)
Digital ground (0 V)
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MSM7732-01
PIN FUNCTIONAL DESCRIPTION
AIN+, AIN–, GSX
Transmit analog inputs and the output for transmit gain adjustment.
AIN– connects to inverting input of the internal transmit amplifier. AIN+ connects to non-inverting input of the
internal transmit amplifier. GSX connects to the internal transmit amplifier output. Refer to Figure 1 for gain
adjustment.
VFRO, SAO, AOUT+, AOUT–, PWI
Receive analog outputs and the outputs for receive gain adjustment.
VFRO is the receive filter output for the voice signal. SAO is the receive filter output for an acoustic component of
the sound tone. SAO can directly drive 32 Ω load. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive a 32 Ω load. Refer to Figure 1.
GSX
R2
Vi
C1 R1
Transmit Gain:
VGSX/Vi
–
+
to ENCODER
AIN+
10 µF
0.1 µF
AIN–
SG
+
–
AOUT+
Vo = VVFRO (R3/R4) ×2
R3
R4
VREF
–1
AOUT–
PWI
VFRO
SAO
D/A
Conv.
Sounder output signal
Figure 1 Analog Input/Output Interface
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MSM7732-01
SG
Analog signal ground.
The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors (10 µF in parallel with 0.1 µF
ceramic type) between this pin and AG to get the specified noise characteristics. During power-down, this output
voltage is 0 V.
AMPAI, AMPAO
Used for amplifier A. The pin AMPAI is connected to the amplifier A inverting input, and the pin AMPAO is
connected to the amplifier A output.
SWA, SWB, SWC
Used for the internal analog switch. The pin SWB connects to the pin SWA or the pin SWC. This is controlled by
CR1-B1.
SWD, SWE
Used for the internal analog switch. The pin SWD connects to the pin SWE or not. This is controlled by CR1-B2.
VDD, VA
+3 V power supply for analog. VDD is the digital power supply. VA is the analog power supply.
Since these pins are separated in the device, connect them as close as possible on the PCB.
DG, AG1, AG2
Ground. DG is the digital system ground. AG1 and AG2 are connected to the analog system ground.
The DG pin must be kept as close as possible to AG1 and AG2 on the PCB.
PDN
Power down and reset control input.
When set to digital “0”, the system changes to the power down state and control registers are reset. Since the power
down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic “0” when using
this pin.
Be sure to reset the control registers by executing this power down to keep this pin to digital “0” level for 200 ns or
longer after the power is turned on and VDD exceeds 2.4 V.
MCK
Master clock input.
The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK.
BCLK
Shift clock input for the PCM data.
The frequency is set in the range of 64 kHz to 2048 kHz.
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MSM7732-01
SYNC
8 kHz synchronous signal input for transmit and receive PCM data.
Synchronize this signal with BCLK signal. Refer to Figure 2.
PCMOUT
Transmit PCM data output.
This PCM output signal is output from MSB synchronously with the rising edge of BCLK and SYNC. Refer to
Figure 2. This is a logic output pin so that external pull-up is not required. This pin outputs logic "L" except during
effective PCM data bits, and outputs logic "H" during power-down.
PCMIN
Receive PCM data input.
This PCM input signal is shifted in on the falling edge of BCLK and is input from MSB.
Refer to Figure 2.
8 kHz (125 µs)
SYNC
BCLK
PCMIN or
PCMOUT
MSB
LSB
∗ 14 bit in the case of linear mode
(a) Long frame synchronous interface
8 kHz (125 µs)
SYNC
BCLK
PCMIN or
PCMOUT
MSB
LSB
∗ 14 bit in the case of linear mode
(b) Short frame synchronous interface
Figure 2 PCM Interface Basic Timing Diagram
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OKI Semiconductor
MSM7732-01
DEN, EXCK, DIO
Serial control ports for MCU interface.
Reading and writing data is performed by an external MCU through these pins. Eight registers with eight bits are
provided on the devices.
DEN is the "Enable" control signal input, EXCK is the data shift clock input, and DIO is the address and data input
or output. Figure 3 shows the input or output timing diagram.
DEN
EXCK
W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
DIO
(a) Write Data Timing Diagram
DEN
EXCK
DIO
R
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
input
output
(b) Read Data Timing Diagram
Figure 3 MCU Interface Input/Output Timing
Table 1 shows the register map.
Table 1
Name
Address
Control and Detect Data
A2
A1
A0
B7
CR0
0
0
0
A/µ SEL
CR1
0
0
1
—
CR2
0
1
0
CR3
0
1
1
TX
ON/OFF
CR5
1
1
0
0
GAIN2
0
OTHERS
1
SEL
—
CR6
1
1
0
CR7
1
1
1
PON
AOUT
—
B5
VOX
ON/OFF
VOX OUT
B4
PDN ALL PDN TX
—
—
TX GAIN2 TX GAIN1 TX GAIN0
Side Tone Side Tone Side Tone
DTMF/
CR4
B6
GAIN1
GAIN0
TONE
SAO/
SEND
VFRO
—
—
ON LVL1 ON LVL0
TX NOISE TX NOISE
LVL1
LVL0
R/W : Read/Write enable
R/W
B3
B2
B1
B0
PDN RX
SLP
SLP SEL
LNR
R/W
SW D/E
SW C/A
RX PAD
R/W
SHORT
FRAME
RX
ON/OFF
RX GAIN2 RX GAIN1 RX GAIN0
R/W
TONE
TONE
TONE
TONE
TONE
ON/OFF
GAIN3
GAIN2
GAIN1
GAIN0
TONE4
TONE3
TONE2
TONE1
TONE0
R/W
—
—
—
—
—
R/W
—
—
—
—
—
R/W
—
—
—
—
—
R
R/W
R : Read only register
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MSM7732-01
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
—
–0.3 to +5.0
V
Analog Input Voltage
VAIN
—
–0.3 to VDD+0.3
V
Digital Input Voltage
VDIN
—
–0.3 to VDD+0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supply Voltage
VDD
Operating Temperature
Ta
Input High Voltage
VIH
Condition
Voltage must be fixed
—
To all digital input pins
Min.
Typ.
Max.
+2.4
+3.0
+3.3
V
–40
—
+85
°C
0.7 x VDD
—
VDD
V
0.16 x
Unit
Input Low Voltage
VIL
To all digital input pins
0
—
Digital Input Rise Time
tir
To all digital input pins
—
—
50
ns
Digital Input Fall Time
tif
To all digital input pins
—
—
50
ns
VDD
V
Digital Output Load
CDL
To all digital output pins
—
—
100
pF
Bypass Capacitor for SG
CSG
Between SG and AG
10+0.1
—
—
µF
Master Clock Frequency
Bit Clock Frequency
FMCK
MCK
–0.01%
2.048
0.01%
MHz
FBCK1
BCLK (A/µ-law)
64
—
2048
kHz
FBCK2
BCLK (Linear)
128
—
2048
kHz
Synchronous Signal Frequency
FSYNC
SYNC
—
8.0
—
kHz
Clock Duty Ratio
DCLK
MCK, BCLK, EXCK
40
50
60
%
Sync Pulse Setting Time
TSB
SYNC → BCLK
-100
—
100
ns
TBS
BCLK → SYNC
100
—
—
ns
tWS
SYNC
1BCLK
—
100
µs
Synchronous Signal Width
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MSM7732-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Parameter
Symbol
IDD1
Condition
Operation Mode
No Signal (VDD = 3.0 V)
Min.
Typ.
Max.
Unit
0
5.0
11.0
mA
0
9.0
20.0
mA
0
1.0
10
µA
—
—
2.0
µA
Operation Mode
Power Supply Current
IDD2
No Signal (VDD = 3.0 V)
AOUT+, AOUT– or SAO is active
IDD3
Input Leakage Voltage
Power Down Mode
(VDD = 3.0 V, Ta = 25°C)
IIH
VI = VDD
IIL
VI = 0 V
Output High Voltage
VOH
IOH = 0.4 mA
Output Low Voltage
VOL
IOL = –1.2 mA
Input Capacitance
CIN
—
—
—
0.5
µA
0.5 x VDD
—
VDD
V
0
0.2
0.4
V
—
5
—
pF
Analog Interface Characteristics
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Parameter
Input Resistance
Output Load Resistance
Output Load Capacitance
Symbol
RINX
Condition
AMPAI, AIN+, AIN–, PWI
Min.
Typ.
Max.
Unit
10
—
—
MΩ
RLGX1
AMPAO, GSX, VFRO
20
—
—
kΩ
RLGX2
SAO, AOUT+, AOUT–
32
—
—
Ω
CLGX
Analog output pins
—
—
100
pF
—
—
*11.3
VPP
—
—
3.0
VPP
—
—
3.98
VPP
SAO, AOUT+, AOUT–(VO1, VO2)
—
—
1.0
%
* THD2
AOUT+, AOUT– (VO3)
—
1.0
—
%
VOFGX1
AMPAO, GSX
–20
—
20
mV
VOFGX2
VFRO, SAO, AOUT+, AOUT–
–100
—
100
mV
VO1
VO2
Output Amplitude
AMPAO, GSX, VFRO RL = 20 kΩ
SAO RL = 32Ω
AOUT+, AOUT–
Differential output VDD = 2.7 to 3.3 V
RL = 32Ω
AOUT+, AOUT–
2
* VO3
Differential output VDD = 3.0 V
RL = 30Ω
Total Harmonic Distortion
Input Offset Voltage
THD1
2
SG Output Voltage
VSG
SG
—
1.4
—
V
SG Output Impedance
RSG
SG
—
40
80
kΩ
—
—
300
Ω
Internal Switch ON Impedance
Rsw
All internal switches
*1 –7.7 dBm (600Ω) = 0 dBm0 , +3.17 dBm0 = 1.3 VPP
*2 Expected value
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MSM7732-01
AC Characteristics
(VDD = 2.4 V to 3.3 V, Ta = –40°C)
Parameter
Symbol
Freq.
(Hz)
LOSS T1
0 to 60
Condition
Level
(dBm0)
Others
LOSS T2 300 to 3000
Transmit Frequency Response
Receive Frequency Response
LOSS T3
1020
LOSS T4
3300
LOSS T5
3400
Ratio
Receive Signal to Distortion
Ratio
Transmit Gain Tracking
Receive Gain Tracking
Typ.
Max.
Unit
25
—
—
dB
—
0.20
dB
–0.15
0
—
Reference
dB
–0.15
—
0.80
dB
0
—
0.80
dB
LOSS R6
3968.75
13
—
—
dB
LOSS R1
0 to 3000
–0.15
—
0.20
dB
LOSS R2
1020
LOSS R3
3300
LOSS R4
3400
LOSS R5
3968.75
SD T1
Transmit Signal to Distortion
Min.
0
—
3
SD T2
SD T3
Reference
0
1020
–30
(*1)
dB
–0.15
—
0.80
dB
0
—
0.80
dB
13
—
—
dB
35
—
—
dB
35
—
—
dB
35
—
—
dB
SD T4
–40
28
—
—
dB
SD T5
–45
23
—
—
dB
SD R1
3
35
—
—
dB
35
—
—
dB
35
—
—
dB
SD R2
SD R3
0
1020
–30
(*1)
SD R4
–40
28
—
—
dB
SD R5
–45
23
—
—
dB
GT T1
3
–0.2
—
0.2
dB
GT T2
–10
GT T3
1020
–40
Reference
—
–0.2
—
dB
0.2
dB
GT T4
–50
–0.6
—
0.6
dB
GT T5
–55
–1.2
—
1.2
dB
GT R1
3
–0.2
—
0.2
dB
GT R2
–10
GT R3
1020
–40
Reference
—
dB
–0.2
—
0.2
dB
GT R4
–50
–0.6
—
0.6
dB
GT R5
–55
–1.2
—
1.2
dB
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OKI Semiconductor
MSM7732-01
AC Characteristics (Continued)
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Condition
Symbol
Parameter
Idle Channel Noise
Freq.
Level
Typ.
Max.
(Hz)
(dBm0)
—
AIN = SG
(*1)
—
—
–68
NIDLR
—
—
(*1,*2)
—
—
–72
GSX
0.285
VFRO
0.285
1020
Absolute Signal Amplitude
0
AVR
Ratio
Min.
NIDLT
AVT
Power Supply Noise Rejection
Others
PSRRT
Noise
Vrms
30
—
—
dB
0
—
200
ns
0
—
200
ns
0
—
200
ns
0
—
200
ns
tM1
50
—
—
ns
tM2
50
—
—
ns
tM3
50
—
—
ns
tM4
50
—
—
ns
tM5
100
—
—
ns
50
—
—
ns
0 to 50 kHz
tXD1
tRD1
Interface
tXD2
Level:
—
50 mVpp
1 LSTTL
—
+
100 pF
tRD2
See
Fig. 5
tXD3
tRD3
tM6
—
CL = 50 pF
tM7
See
Fig. 6
50
—
—
ns
tM8
0
—
100
ns
tM9
50
—
—
ns
tM10
50
—
—
ns
tM11
*3
0.359
dB
Digital Input/Output Timing PCM
*1
*2
(*3)
Vrms
—
tSDX
Shift Clock Frequency
0.320
0.359
—
Noise Freq:
tSDR
Setting Time
(*3)
dBm0p
30
PSRRR
Serial Port Digital Input/Output
0.320
Unit
fEXCK
—
—
EXCK
0
—
50
ns
—
—
10
MHz
Use the P-message weighted filter.
PCMIN input code "11010101"(A-law)
"11111111"(µ-law)
0.320 Vrms = 0 dBm0 = –7.7 dBm
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MSM7732-01
AC Characteristics (DTMF and Other Tones)
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Parameter
Frequency Difference
Symbol
Condition
Min.
Typ.
Max.
Unit
DFT
DTMF Tones, Other Tones
–1.5
—
+1.5
%
–18
–16
–14
dBm0
–16
–14
–12
dBm0
–10
–8
–6
dBm0
–8
–6
–4
dBm0
+1
+2
+3
dB
VTL
Original (Reference) Tones
Signal Level *4
VTH
VRL
VRH
Relative Level of DTMF Tones
*4
Transmit
DTMF (Low)
Tones
(Gain setting DTMF (High) and
0 dB)
Other Tones
Receive
DTMF (Low)
Tones
(Gain setting DTMF (High) and
–6 dB)
RDTMF
Other Tones
VTH/VTL, VRH/VRL
Does not include the setting value for the programmable gain.
AC Characteristics (Programmable Gain Stages)
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Parameter
Gain Accuracy
Symbol
Condition
Min.
Typ.
Max.
Unit
DG
All gain stages, to programmed value
–1
0
+1
dB
AC Characteristics (Voice Detect Function)
(VDD = 2.4 V to 3.3 V, Ta = –40°C to +85°C)
Parameter
Voice Detection Time
Voice Detection Accuracy
Symbol
Condition
TVON
Silence>Voice
TVOF
(Voice/Silence differential: 10 dB)
DVX
For detection level set values by
CR6-B6, B5
Min.
Typ.
Max.
Unit
—
5
—
ms
140
160
180
ms
–2.5
0
2.5
dB
14/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
TIMING DIAGRAM
Transmit Side PCM Timing (Normal Synchronous Interface)
BCLK
1
0
2
tSB
SYNC
3
4
5
6
7
8
9
10
9
10
tWS
tXD1
tXD2
tXD3
MSB
PCMOUT
LSB
tSDX
When tSB >= 0, the Delay of the MSB is defined as tXD1.
When tSB < 0, the Delay of the MSB is defined as tSDX.
Transmit Side PCM Timing (Short Frame Synchronous Interface)
BCLK
0
1
tSB
2
3
tXD1
tXD2
4
5
6
7
8
tBS
tWS
SYNC
tXD3
LSB
MSB
PCMOUT
Receive Side PCM Timing (Normal Synchronous Interface)
BCLK
0
1
2
tSB
SYNC
3
4
5
6
7
8
10
9
10
tWS
tRD1
tRD2
tRD3
MSB
PCMIN
9
LSB
tSDR
Receive Side PCM Timing (Short Frame Synchronous Interface)
BCLK
SYNC
PCMIN
0
1
tSB
2
3
tRD1
tRD2
4
5
6
7
8
tBS
tWS
MSB
tRD3
LSB
Figure 4 PCM Interface Timing
15/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
Serial Port Timing for Microcontroller Interface
DEN
tM5
tM2
3
2
1
EXCK
DIO
(WRITE)
DIO
(READ)
W/R
W/R
A1
A2
12
11
tM9
tM7
tM6
tM4
6
5
4
tM3
tM1
tM10
A1
A1
A0
B7
A0
tM8
B7
B1
B0
tM11
B1
B0
Figure 5 Serial Control Port Interface
16/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
FUNCTIONAL DESCRIPTION
Control Registers
CR0 (Basic operating mode 1)
Note: Initial Value: Reset state by PDN
B7
CR0
A/µ SEL
Initial Value
0
B6
PON
AOUT
0
B5
B4
B3
PDN ALL PDN TX PDN RX
0
0
B2
B1
B0
SLP
SLP SEL
LNR
0
0
0
3500
4000
0
B7………… PCM companding law select; 0/µ-law, 1/A-law
B6………… Power on control for output amps (AOUT+, AOUT–); 0/Power down, 1/Power on
B5………… Power down (entire system); 0/Power on, 1/Power down
When using this data for power down control, set pin PDN at “1” level.
The control registers are not reset by this signal.
B4………… Power down (transmit and amplifier A); 0/Power on, 1/Power down
B3………… Power down (receive only); 0/Power on, 1/Power down
B2………… Slope filter enable; 0/Slope filter disable, 1/ Slope filter enable
B1………… The type of slope filter select; 0/CASE1, 1/CASE2, refer to Figure 6.
B0………… PCM interface linear code select;
0/Companding law selected by CR0-B7
1/14-bit linear code (2’s complement) in spite of CR0-B7
6
4
2
Gain [dB]
0
CASE1
–2
CASE2
–4
–6
–8
–10
–12
–14
0
500
1000
1500
2000
2500
Frequency [Hz]
3000
Figure 6 Frequency Response of Slope Filter
17/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
CR1 (Basic operating mode 2)
B7
B6
B5
B4
CR1
—
—
—
—
Initial Value
0
0
0
0
B3
SHORT
FRAME
0
B2
SW D/E
0
B1
B0
SW C/A RX PAD
0
0
B7, B6, B5, B4……Not used
B3…………………Short frame synchronous interface select;
0/Long frame synchronous interface, 1/Short frame synchronous interface
…………………
B2
Analog switch control
: 0/SWD to SWE open, 1/ SWD to SWE closed
B1…………………Analog switch control
B0…………………Receive side PAD
: 0/SWB to SWA closed. The SWC pin is high impedance.
1/SWB to SWC closed. The SWA pin is high impedance.
: 1/inserted, 12 dB loss
0/no PAD
18/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment)
B7
CR2
Initial Value
B6
B5
B4
B3
B2
B1
B0
TX
TX
TX
TX
RX
RX
RX
RX
ON/OFF
GAIN2
GAIN1
GAIN0
ON/OFF
GAIN2
GAIN1
GAIN0
0
0
1
1
0
0
1
1
B7………………… PCM coder disable; 0/Enable, 1/Disable (transmit PCM idle pattern)
B6, B5, B4………… Transmit gain adjustment, refer to Table 2.
B3………………… PCM decoder disable; 0/Enable, 1/Disable (receive PCM idle pattern)
B2, B1, B0………… Receive gain adjustment, refer to Table 2.
Table 2
B6
B5
B4
Transmit Gain
B2
B1
B0
Receive Gain
0
0
0
–6 d B
0
0
0
–1 2 d B
0
0
1
–4 d B
0
0
1
–9 d B
0
1
0
–2 d B
0
1
0
–6 d B
0
1
1
0 dB
0
1
1
–3 d B
1
0
0
+2 dB
1
0
0
0 dB
1
0
1
+4 dB
1
0
1
+3 dB
1
1
0
+6 dB
1
1
0
+6 dB
1
1
1
+8 dB
1
1
1
+9 dB
The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain
settings for DTMF tones and other tones. Tone signal transmission is enabled by CR4-B6, and the gain setting is
set to the levels shown below.
DTMF tones (low group):
–16 dBm0
DTMF tones (high group) and other tones: –14 dBm0
For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1, 1, 1), then the following tones appear
at the PCMOUT pin.
DTMF tones (low group):
–8 dBm0
DTMF tones (high group) and other tones: –6 dBm0
Gain setting for the side tone (path to the receive side from the transmit side) and the receive side tone is provided
by register CR3.
19/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
CR3 (Side tone and other tone generator gain setting)
B7
B6
B5
B4
Side Tone Side Tone Side Tone
CR3
B3
B2
B1
B0
TONE
TONE
TONE
TONE
TONE
GAIN2
GAIN1
GAIN0
ON/OFF
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
Initial Value
B7, B6, B5…………Side tone path gain setting, refer to Table 3.
B4………………… Tone generator enable; 0/Disable, 1/Enable
B3, B2, B1, B0…… Tone generator gain adjustment for receive side, refer to Table 4.
Table 3
B7
B6
B5
Side Tone Path Gain
0
0
0
OFF
0
0
1
–15 dB
0
1
0
–13 dB
0
1
1
–11 dB
1
0
0
–9 dB
1
0
1
–7 dB
1
1
0
–5 dB
1
1
1
–3 dB
Table 4
B3
B2
B1
B0
Tone Generator Gain
B3
B2
B1
B0
Tone Generator Gain
0
0
0
0
OFF
1
0
0
0
–20 dB
0
0
0
1
–34 dB
1
0
0
1
–18 dB
0
0
1
0
–32 dB
1
0
1
0
–16 dB
0
0
1
1
–30 dB
1
0
1
1
–14 dB
0
1
0
0
–28 dB
1
1
0
0
–12 dB
0
1
0
1
–26 dB
1
1
0
1
–10 dB
0
1
1
0
–24 dB
1
1
1
0
–8 dB
0
1
1
1
–22 dB
1
1
1
1
–6 dB
The tone generator gain setting table for the receive side, as shown in Table 4, depends upon the following
reference levels.
DTMF tones (low group):
–2 dBm0
DTMF tones (high group) and other tones:
0 dBm0
For example, when selecting –6 dB (B3, B2, B1, B0) = (1, 1, 1, 1) as a tone generator gain, the signal amplitude of
each DTMF tone on SAO or VFRO is as follows:
DTMF tones (low group):
–8 dBm0
DTMF tones (high group) and other tones:
–6 dBm0
20/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
CR4 (Tone generator operating mode and frequency select)
CR4
B7
B6
B5
DTMF/
TONE
SAO/
Others SEL
SEND
VFRO
0
0
0
Initial Value
B7 ……………………
B6 ……………………
B5 ……………………
B4, B3, B2, B1, B0 …
B4
B3
B2
B1
B0
TONE4
TONE3
TONE2
TONE1
TONE0
0
0
0
0
0
DTMF or other tones select; 0/Others, 1/DTMF
Tone transmit enable (transmit side); 0/Voice signal (transmit), 1/Tone transmit
Tone output pin select (receive side); 0/VFRO, 1/SAO
Tone frequency setting, refer to Tables 5-1 and 5-2.
(a) B7 = 1 (DTMF tones)
Table 5-1
B4
B3
B2
B1
B0
Frequency
B4
B3
B2
B1
B0
Frequency
*
0
0
0
0
697 Hz + 1209 Hz
*
1
0
0
0
852 Hz + 1209 Hz
*
0
0
0
1
697 Hz + 1336 Hz
*
1
0
0
1
852 Hz + 1336 Hz
*
0
0
1
0
697 Hz + 1477 Hz
*
1
0
1
0
852 Hz + 1477 Hz
*
0
0
1
1
697 Hz + 1633 Hz
*
1
0
1
1
852 Hz + 1633 Hz
*
0
1
0
0
770 Hz + 1209 Hz
*
1
1
0
0
941 Hz + 1209 Hz
*
0
1
0
1
770 Hz + 1336 Hz
*
1
1
0
1
941 Hz + 1336 Hz
*
0
1
1
0
770 Hz + 1477 Hz
*
1
1
1
0
941 Hz + 1477 Hz
*
0
1
1
1
770 Hz + 1633 Hz
*
1
1
1
1
941 Hz + 1633 Hz
*Undefined
Frequency
B4
B3
B2
B1
B0
Frequency
1
0
0
0
0
1200 Hz
1
0
0
0
1
1300 Hz
1
0
0
1
0
—
(b) B7 = 0 (Other tones)
Table 5-2
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
—
1
0
0
1
1
1477 Hz
0
0
1
0
0
—
1
0
1
0
0
1633 Hz
0
0
1
0
1
—
1
0
1
0
1
2000 Hz
0
0
1
1
0
—
1
0
1
1
0
2100 Hz
0
0
1
1
1
—
1
0
1
1
1
—
0
1
0
0
0
—
1
1
0
0
0
2400 Hz
0
1
0
0
1
400 Hz
1
1
0
0
1
—
0
1
0
1
0
440 Hz
1
1
0
1
0
2500 Hz
0
1
0
1
1
480 Hz
1
1
0
1
1
—
0
1
1
0
0
—
1
1
1
0
0
—
2730 Hz/2500 Hz
8 Hz wamble
2000 Hz/2667 Hz
8 Hz wamble
1000 Hz/1333 Hz
8 Hz wamble
0
1
1
0
1
667 Hz
1
1
1
0
1
2700 Hz
0
1
1
1
0
800 Hz
1
1
1
1
0
—
0
1
1
1
1
1000 Hz
1
1
1
1
1
3000 Hz
21/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
CR5 (Not used)
B7
B6
B5
B4
B3
B2
B1
B0
CR5
––
––
––
––
––
––
––
––
Initial Value
0
0
0
0
0
0
0
0
B6
B5
B4
B3
B2
B1
B0
––
––
––
––
––
0
0
0
0
0
B7-B0……… Not used
CR6 (VOX function control)
B7
CR6
Initial Value
VOX
ON LVL1 ON LVL0
ON/OFF
0
0
0
B7 ……………………… VOX function enable; 0/Disable, 1/Enable
If B7 is set to a logic “1”, B3 should be set to a logic “1”.
B6, B5…………………… Voice detector level setting;
(0,0): –20 dBm0 (0,1): –26 dBm0 (1,0): –32 dBm0 (1,1): –38 dBm0
B4, B2, B1, B0 ………
Not used
CR7 (Detect register, read only)
B7
CR7
VOX OUT
Initial Value
0
B6
B5
TX NOISE TX NOISE
LVL1
LVL0
0
0
B4
B3
B2
B1
B0
––
––
––
––
––
*
*
*
*
*
*For IC testing
B7………………………… Voice detection; 0/Silence, 1/Voice detect
B6, B5…………………… Voice detect level (indicator);
(0,0): Below –50 dBm0
(0,1): –40 to –50 dBm0
(1,0): –30 to –40 dBm0
(1,1): Above –30 dBm0
Note:
These outputs are enabled when the VOX function is turned on by CR6-B7.
B4, B3, B2, B1, B0……… Not used
22/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
APPLICATION CIRCUIT
VDD
Mic
NC
48
SWC
47
SWB
46
SWA
45
VDD
44
NC
43
NC
42
DG
41
MCK
40
R1
C1
C4
NC
1
AMPAI
2
R2 AMPAO
3
AIN+
4
AIN –
C2 R3
5
GSX
6
NC
R4
7
NC
8
SWD
9
SWE
C3
10
SG
11
NC
C5
12
DEN
39
DIO
38
NC
37
C9
10 µF
GND
NC
MCU I/F
20 kΩ
Voice
PCM
Detect
Compand
20 kΩ
A/D
Slope
BPF
Filter
TONE / DTMF
Gen
D/A
PCM
LPF
Expand
VREF
20 kΩ
32Ω
32Ω
32Ω
C6
VDD
R5
Hands Free Kit
R6
AOUT22
AOUT+
23
NC
24
NC
13
NC
14
VFRO
15
AG1
16
NC
17
SAO
18
VA
19
PWI
20
NC
21
0.1 µF
36
EXCK
35
PCMOUT
34
PCMIN
33
SYNC
32
NC
31
BCLK
30
PDN
29
NC
28
AG2
27
NC GND
26
NC
25
Earphone
IN
OUT
C7
Speaker
23/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.19 TYP.
5/Dec. 5, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
24/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
(Unit: mm)
TQFP48-P-0707-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.13 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
25/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
(Unit: mm)
P-LFBGA48-0707-0.80
5
Package material
Package weight (g)
Rev. No./Last Revised
Epoxy resin
0.12 TYP.
1/Jun. 20, 2001
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
26/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
(Unit: mm)
P-TFLGA48-0707-0.80
5
Package material
Package weight (g)
Rev. No./Last Revised
Epoxy resin
0.10 TYP.
2/Jun. 20, 2001
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
27/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
REVISION HISTORY
Document
No.
Date
FEDL7732-01-04
Nov. 2001
FEDL7732-01-05
Jan. 15, 2002
Page
Previous Current
Edition
Edition
Description
―
―
Edition 4
26
26
Changed the package outline diagram.
27
27
Changed the package outline diagram.
FEDL7732-01-06
Jun. 3, 2004
2
2
Addition of RX PAD in the Block Diagram.
FEDL7732-01-07
Jun. 15, 2004
8
8
More clarification of PCMOUT output state
FEDL7732-01-08
Jul. 29, 2004
23
23
FEDL7732-01-09
May 18, 2005
2
2
10
10
FEDL7732-01-10
Nov 2, 2005
Addition of tSB
15
15
Addition of tSB
Addition of description about tXD1and tSDX
Correction of false connection of C2 and R3 in
APPLICATION CIRCUIT
Addition of TXON/OFF and RXON/OFF in the
Block Diagram
28/29
FEDL7732-01-10
OKI Semiconductor
MSM7732-01
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2005 Oki Electric Industry Co., Ltd.
29/29
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