Micron MT28F322D18FH-70BET Flash memory Datasheet

2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
MT28F322D20
MT28F322D18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
BALL ASSIGNMENT
58-Ball FBGA
• Flexible dual-bank architecture
– Support for true concurrent operation with zero
latency
– Read bank a during program bank b and vice versa
– Read bank a during erase bank b and vice versa
• Basic configuration:
Seventy-one erasable blocks
– Bank a (8Mb for data storage)
– Bank b (24Mb for program storage)
• VCC, VCCQ, VPP voltages
– 1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F322D18 only)
– 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V
VCCQ (MAX) (MT28F322D20 only)
– 0.9V (TYP) VPP (in-system PROGRAM/ERASE)
– 12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns/80ns @ 1.70V VCC
• Burst Mode read access (MT28F322D20)
– MAX clock rate: 54 MHz (tCLK = 18.5ns)
– Burst latency: 70ns @ 1.80V VCC and 54 MHz
– tACLK: 17ns @ 1.80V VCC and 54 MHz
• Page Mode read access1
– Eight-word page
– Interpage read access: 70ns/80ns @ 1.80V
– Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
– Asynchronous READ < 15mA (MAX)
– Standby < 50µA
– Automatic power saving feature (APS)
• Enhanced write and erase suspend options
– ERASE-SUSPEND-to-READ within same bank
– PROGRAM-SUSPEND-to-READ within same bank
– ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
– Extended command set
– Common flash interface
• PROGRAM/ERASE cycle
– 100,000 WRITE/ERASE cycles per block
2
3
4
5
6
7
8
A
A8
VSS
VCC
VPP
A18
A6
A4
B
A12
A9
A20
CLK
RST#
A17
A5
A3
C
A13
A10
ADV#
WE#
A19
A7
A2
D
A15
A14
WAIT#
A16
DQ12
WP#
E
VCCQ
DQ15
DQ6
DQ4
DQ2
DQ1
CE#
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
OE#
G
DQ7
VSSQ
DQ5
VCC
DQ3
VCCQ
DQ8
VSSQ
A1
Top View
(Ball Down)
NOTE: See page 7 for Ball Description Table.
See page 43 for mechanical drawing.
OPTIONS
MARKING
• Timing
70ns access
80ns access
• Frequency
54 MHz
40 MHz
No burst operation
• Boot Block Configuration
Top
Bottom
• Package
58-ball FBGA (8 x 7 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
NOTE: 1. Data based on MT28F322D20 device.
2. A “5” in the part mark represents two different
frequencies: 54 MHz (MT28F322D20) or 52 MHz
(MT28F322D18)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
1
A11
-70
-80
52
4
None
T
B
FH
ET
Part Number Example:
MT28F322D20FH-804 BET
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
GENERAL DESCRIPTION
Please refer to the Micron Web site (www.micron.com/
flash) for the latest data sheet.
The MT28F322D20 and MT28F322D18 are highperformance, high-density, nonvolatile Flash memory
solutions that can significantly improve system performance. This new architecture features a two-memorybank configuration that supports dual-bank operation
with no latency.
A high-performance bus interface allows a fast burst
or page mode data transfer; a conventional asynchronous bus interface is provided as well.
The devices allow soft protection for blocks, as readonly, by configuring soft protection registers with dedicated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of the
program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software
packages.
The devices are manufactured using 0.18µm process
technology.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ and
WRITE operations and are available in the following bank
segmentation configuration:
• Bank a is one-fourth of the memory containing
8 x 4K-word parameter blocks, while the remainder
of bank a is split into 15 x 32K-word blocks.
• Bank b represents three-fourths of the memory, is
equally sectored, and contains 48 x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard part
number is not printed on the top of each device. Instead,
an abbreviated device mark comprised of a five-digit
alphanumeric code is used. The abbreviated device marks
are cross referenced to the Micron part numbers in
Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F322D20FH-705 TET
MT28F322D20FH-705 BET
MT28F322D20FH-804 TET
MT28F322D20FH-804 BET
MT28F322D18FH-705 TET
MT28F322D18FH-705 BET
MT28F322D18FH-804 TET
MT28F322D18FH-804 BET
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
PRODUCT
MARKING
SAMPLE
MARKING
MECHANICAL
SAMPLE MARKING
FW546
FW547
FW548
FW549
FW558
FW559
FW543
FW542
FX546
FX547
FX548
FX549
FX558
FX559
FX543
FX542
FY546
FY547
FY548
FY549
FY558
FY559
FY543
FY542
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with several different combinations of features (see Figure 1).
Valid combinations of features and their corresponding
part numbers are listed in Table 2.
Figure 1
Part Number Chart
MT 28F 322 D20 FH-80 4 B ET
Micron Technology
Operating Temperature Range
ET = Extended (-40ºC to +85ºC)
Flash Family
Boot Block Starting Address
28F = Dual-Supply Flash
B = Bottom boot
T = Top boot
Density/Organization/Banks
322 = 32Mb (2,048K x 16)
bank a = 1/4; bank b = 3/4
Burst Mode Frequency
D = Asynchronous/Page/Burst Read
Blank = None
4 = 40 MHz
5 = 54 MHz (MT28F322D20) or
52 MHz (MT28F322D18)
Operating Voltage Range
Access Time
Read Mode Operation
-70 = 70ns
-80 = 80ns
18 = 1.70V–1.90V
20 = 1.80V–2.20V VCC
20 = 1.80V–2.25V VCCQ
Package Code
FH = 58-ball FBGA (8 x 7 grid)
Table 2
Valid Part Number Combinations
PART NUMBER
MT28F322D20FH-705 BET
MT28F322D20FH-705 TET
MT28F322D20FH-804 BET
MT28F322D20FH-804 TET
MT28F322D18FH-705 BET
MT28F322D18FH-705 TET
MT28F322D18FH-804 BET
MT28F322D18FH-804 TET
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
ACCESS
TIME (ns)
BOOT BLOCK
STARTING
ADDRESS
BURST
FREQUENCY
(MHz)
OPERATING
TEMPERATURE
RANGE
70
70
80
80
70
70
80
80
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
Top
54
54
40
40
52
52
40
40
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
PR Lock
PR Lock
Query
Query/OTP
OTP
DQ0–DQ15
Manufacturer’s ID
Data Input
Buffer
X DEC
Bank 1 Blocks
Y/Z DEC
Y/Z Gating/Sensing
Device ID
Block Lock
RCR
Data
Register
ID Reg.
RST#
CE#
WE#
OE#
Status
Reg.
CSM
Program/
Erase
Pump Voltage
Generators
WSM
DQ0–DQ15
Output
Multiplexer
I/O Logic
A0–A20
Output
Buffer
Address
Input
Buffer
Address
CNT WSM
WAIT#
ADV#
CLK
Address Latch
Address
Multiplexer
Y/Z DEC
Y/Z Gating/Sensing
X DEC
Bank 2 Blocks
BSM
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 2
Bottom Boot Block Device
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Bank b = 24Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
Address Range
(x16)
1F8000h-1FFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-097FFFh
090000h-097FFFh
088000h-087FFFh
080000h-087FFFh
Block
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
Bank a = 8Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Address Range
(x16)
078000h-07FFFFh
070000h-077FFFh
068000h-067FFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
007000h-007FFFh
006000h-006FFFh
005000h-005FFFh
004000h-004FFFh
003000h-003FFFh
002000h-002FFFh
001000h-001FFFh
000000h-000FFFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 3
Top Boot Block Device
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
Bank a = 8Mb
Block Size
(K-bytes/K-words)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
Address Range
(x16)
1FF000h-1FFFFFh
1FE000h-1FEFFFh
1FD000h-1FDFFFh
1FC000h-1FCFFFh
1FB000h-1FBFFFh
1FA000h-1FAFFFh
1F9000h-1F9FFFh
1F8000h-1F8FFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
Block
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
Bank b = 24Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range
(x16)
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-09FFFFh
090000h-097FFFh
088000h-08FFFFh
080000h-087FFFh
078000h-07FFFFh
070000h-077FFFh
068000h-06FFFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
000000h-007FFFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
BALL DESCRIPTIONS
58-BALL FBGA
NUMBERS
SYMBOL
TYPE
E8, D8, C8, B8,
A8, B7, A7, C7,
A2, B2, C2, A1,
B1, C1, D2, D1,
D4, B6, A6, C6,
B3
A0–A20
Input
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles.
B4
CLK
Input
Clock: Synchronizes the Flash memory to the system operating frequency
during synchronous burst mode READ operations. When configured for
synchronous burst mode READs, address is latched on the first rising (or
falling, depending upon the read configuration register setting) CLK edge
when ADV# is active or upon a rising ADV# edge, whichever occurs first.
CLK is ignored during asynchronous access READ and WRITE operations
and during READ PAGE ACCESS operations.1
C4
ADV#
Input
Address Valid: Indicates that a valid address is present on the address
inputs. Addresses are latched on the rising edge of ADV# during READ
and WRITE operations. ADV# may be tied active during asynchronous
READ and WRITE operations.1
A5
VPP
Input
Program/Erase Enable: [0.9V–1.95V or 11.4V–12.6V] Operates as input at
logic levels to control complete device protection. Provides factory
programming compatibility when driven to 11.4V–12.6V.
E7
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
F8
OE#
Input
Output Enable: Enables the output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.
C5
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is either a WRITE to the command state machine (CSM) or to the
memory array.
B5
RST#
Input
Reset: When RST# is a logic LOW, the device is in reset mode, which drives
the outputs to High-Z and resets the write state machine. When RST# is at
logic HIGH, the device is in standard operation. When RST# transitions
from logic LOW to logic HIGH, the device resets all blocks to locked and
defaults to the read array mode.
D6
WP#
Input
Write Protect: Controls the lock down function of the flexible locking
feature.
Input/
Output
Data Inputs/Outputs: Inputs array data on the second CE# and WE#
cycle during PROGRAM command. Inputs commands to the command
user interface when CE# and WE# are active. DQ0–DQ15 output data
when CE# and OE# are active.
Output
Wait: Provides data valid feedback during continuous burst read access.
The signal is gated by OE# and CE#. This signal is always kept at a valid
logic level.
F7, E6, E5, G5, DQ0–DQ15
E4, G3, E3, G1,
G7, F6, F5, F4,
D5, F3, F2, E2
D3
WAIT#
DESCRIPTION
NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The
WAIT# signal can be ignored when operating in asynchronous or page mode, as it is always held at logic “1” or “0,”
depending on the RCR8 setting (see Table 8).
(continued on next page)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
BALL DESCRIPTIONS (continued)
58-BALL FBGA
NUMBERS
SYMBOL
TYPE
A4, G4
VCC
Supply
Device Power Supply: [1.70V–1.90V (MT28F322D18) or 1.80V–2.20V
(MT28F322D20)] Supplies power for device operation.
E1, G6
VCCQ
Supply
I/O Power Supply: [1.70V–1.90V (MT28F322D18) or 1.80V–2.25V
(MT28F322D20)] Supplies power for input/output buffers.
G2, G8
VSSQ
Supply
I/O Ground. Do not float any ground ball.
A3, F1
VSS
Supply
Do not float any ground ball.
C3, D7
–
–
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
DESCRIPTION
Contact ball is not physically present.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are
automated by an on-chip WSM. (For more specific
information about the CSM transition states, see Micron
technical note TN-28-33, “Command State Machine Description and Command Definition.”
Once a valid PROGRAM/ERASE command is entered,
the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device
internally to accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is
completed. After the WSM completes its task, the WSM
status bit (SR7) (see Table 7) is set to a logic HIGH level (1),
allowing the CSM to respond to the full command set
again.
CE#, ADV#, and OE# must be at a logic LOW level (VIL),
and WE# and RST# must be at logic HIGH (VIH).
Table 6 illustrates the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a
command code be entered into the CSM. For each one of
the two memory partitions, an on-chip status register is
available. These two registers allow the progress of the
various operations that can take place on a memory bank
to be monitored. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within
the memory partition boundary, and reading the register
data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0SR7 correspond to DQ0–DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered, the
WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data.
See Table 4 for the CSM command definitions and data
for each of the bus cycles.
OPERATIONS
Device operations are selected by entering a standard
JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os
DQ0–DQ7. The number of bus cycles required to activate
a command is typically one or two. The first operation is
always a WRITE. Control signals CE#, ADV#, and WE#
must be at a logic LOW level (VIL), and OE# and RST#
must be at logic HIGH (VIH). The second operation, when
needed, can be a WRITE or a READ depending upon the
command. During a READ operation, control signals
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored by
toggling OE# and CE# and reading the resulting status
code on I/Os DQ0–DQ7. The high-order I/Os (DQ8–DQ15)
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7
40h/10h
20h
CODE ON DEVICE MODE
Program setup/alternate program setup
Block erase setup
50h
60h
60h
70h
90h
Clear status register
Protection configuration setup
Set read configuration register
Read status register
Read protection configuration register
98h
B0h
C0h
D0h
FFh
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase confirm
Read array
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
other modes of operation, a new command must be
issued to the CSM.
are set to 00h internally, so only the low-order I/Os
(DQ0–DQ7) need to be interpreted. Address lines select
the status register pertinent to the selected memory
partition.
Register data is updated and latched on the falling
edge of ADV# or rising (falling) CLK when ADV# is LOW
during synchronous burst mode or on the falling edge of
OE# or CE#, whichever occurs last. Latching the data
prevents errors from occurring if the register input
changes during a status register monitoring.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the status
register bits.
After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
COMMAND STATE MACHINE
OPERATIONS
The CSM decodes instructions for read array, read
protection configuration register, read query, read status
register, clear status register, program, erase, erase suspend, erase resume, program suspend, program resume,
lock block, unlock block and lock down block, chip protection program, and set read configuration register. The
8-bit command code is input to the device on DQ0–DQ7
(see Table 3 for CSM codes and Table 4 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM
SUSPEND command only.
Table 4
Command Definitions
COMMAND
READ ARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME – ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
SET READ CONFIGURATION REGISTER
NOTE: 1. BA:
IA:
ID:
LPA:
PA:
PD:
QA:
QD:
RCD:
SRD:
WA:
WD:
X:
FIRST BUS CYCLE
OPERATION ADDRESS1 DATA
WRITE
WA
FFh
WRITE
IA
90h
WRITE
BA
70h
WRITE
BA
50h
WRITE
QA
98h
WRITE
BA
20h
WRITE
WA
40h/10h
WRITE
BA
B0h
WRITE
BA
D0h
WRITE
BA
60h
WRITE
BA
60h
WRITE
BA
60h
WRITE
PA
C0h
WRITE
LPA
C0h
WRITE
RCD
60h
SECOND BUS CYCLE
OPERATION ADDRESS1 DATA1
READ
READ
IA
X
ID
SRD
READ
WRITE
WRITE
QA
BA
WA
QD
D0h
WD
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
BA
BA
BA
PA
LPA
RCD
01h
D0h
2Fh
PD
FFFDh
03h
Address within the block
Identification code address
Identification code data
Lock protection register address
Protection register address
Data to be written at the location PA
Query code address
Query code data
Data to be written in the read configuration register
Data read from the status register
Word address of memory location to be written, or read
Data to be written at the location WA
“Don’t Care”
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 5
Command Descriptions
CODE DEVICE MODE
BUS CYCLE
DESCRIPTION
10h
Alt. Program Setup
First
Operates the same as PROGRAM SETUP command
20h
Erase Setup
First
Prepares the CSM for the ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will be
ignored, and the bank will go to read status mode and wait for
another command.
40h
Program Setup
First
A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. The flash outputs
status register data on the rising edge of ADV#, or on the rising clock
edge when ADV# is LOW during synchronous burst mode, or on the
falling edge of OE# or CE#, whichever occurs first.
50h
Clear Status
Register
First
The WSM can set the block lock status (SR1), VPP status (SR3), program
status (SR4), and erase status (SR5) bits in the status register to “1,” but
it cannot clear them to “0.” Issuing this command clears those bits to
“0.”
60h
Protection
Configuration
Setup
First
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN
the command will be ignored, and the device will go to read status
mode.
Set Read
Configuration
Register
First
Puts the device into the set read configuration mode so that it will
be possible to set the option bits related to burst read mode.
70h
Read Status
Register
First
This command places the device into a read status register mode.
Reading the device will output the contents of the status register for
the addressed bank. The device will automatically enter this mode for
the addressed bank after a PROGRAM or ERASE operation has been
initiated.
90h
Read Protection
Configuration
First
Puts the device into the read protection configuration mode so that
reading the device will output the manufacturer/device codes, block
lock status, protection register, or protection register lock status.
98h
Read Query
First
Puts the device into the read query mode so that reading the device
will output common flash interface information.
B0h
Program/Erase
Suspend
First
Issuing this command will suspend the currently executing PROGRAM/
ERASE operation. The status register will indicate when the
operation has been successfully suspended by setting either the
program suspend (SR2) or erase suspend (SR6), and the WSM status bit
(SR7) to a “1” (ready). The WSM will continue to idle in the suspend
state, regardless of the state of all input control signals except RST#,
which will immediately shut down the WSM and the remainder of the
chip if RST# is driven to VIL.
C0h
Program Device
Protection Register
First
Writes a specific code into the device protection register.
Lock Device
Protection Register
First
Locks the device protection register; data can no longer be changed.
(continued on next page)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
11
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 5
Command Descriptions (continued)
CODE DEVICE MODE
D0h
BUS CYCLE
DESCRIPTION
Erase Confirm
Second
If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address pins. During programming/erase,
the device will respond only to the READ STATUS REGISTER, PROGRAM
SUSPEND, or ERASE SUSPEND commands. It will output status register
data on the rising edge of ADV#, or on the rising clock edge when
ADV# is LOW during synchronous burst mode, or on the falling edge
of OE# or CE#, whichever occurs last.
Program/Erase
Resume
First
If a PROGRAM or ERASE operation was previously suspended, this
command will resume the operation.
FFh
Read Array
First
During read array mode, array data will be output on the data bus.
01h
Lock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock the block indicated on the
address bus.
03h
Read Configuration
Register Data
Second
If the previous command was SET READ CONFIGURATION REGISTER,
the configuration bits presented on the address bus will be stored into
the read configuration register.
2Fh
Lock Down
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock down the block indicated on
the address bus.
D0h
Unlock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and unlock the block indicated on the
address bus. If the block had been previously set to lock down, this
operation will have no effect.
00h
Invalid/Reserved
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
Unassigned command that should not be used.
12
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During an ERASE cycle, the CSM responds to an ERASE
SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
ister, the protection register, and PR lock status. Two bus
cycles are required for this operation: the chip identification data is read by entering the command code 90h on
DQ0–DQ7 to the bank containing address 00h and the
identification code address on the address lines. Control
signals CE#, ADV#, and OE# must be at a logic LOW level
(VIL), and WE# and RST# must be at a logic HIGH level
(VIH) to read data from the protection configuration register. Data is available on DQ0–DQ15. After data is read
from the protection configuration register, the READ
ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See
Table 12 for further details.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the program
status bit (SR4), and the erase status bit (SR5) of the status
register. The CLEAR STATUS REGISTER command (50h)
allows the external microprocessor to clear these status
bits and synchronize to the internal operations. When
the status bits are cleared, the device returns to the read
array mode.
READ QUERY
The read query mode outputs common flash interface
(CFI) data when the device is read (see Table 16). Two bus
cycles are required for this operation. It is possible to
access the query by writing the read query command
code 98h on DQ0–DQ7 to the bank containing address
0h. Control signals CE#, ADV#, and OE# must be at a logic
LOW level (VIL) and WE# and RST# must be at a logic
HIGH level (VIH) to read data from the query. The CFI data
structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command
code FFh on DQ0–DQ7.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code FFh
on DQ0–DQ7. Control signals CE#, ADV#, and OE# must
be at a logic LOW level (VIL) and WE# and RST# must be
at a logic HIGH level (VIH) to read data from the array.
Data is available on DQ0–DQ15. Any valid address within
any of the blocks selects that address and allows data to
be read from that address. Upon initial power-up or
device reset, the device defaults to the read array mode.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. The address for both
cycles must be in the same partition. In a READ cycle, the
address is latched on the rising edge of the ADV# signal.
Register data is updated and latched on the falling edge of
ADV# or rising (falling) CLK when ADV# is LOW during
burst mode, or on the falling edge of OE# or CE#, whichever occurs last.
READ PROTECTION CONFIGURATION DATA
The read protection configuration mode outputs five
types of information: the manufacturer/device identifier, the block locking status, the read configuration reg-
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
13
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 6
Bus Operations
MODE
RST#
CE#
ADV#
OE#
WE#
VIH
VIL
VIL
VIL
VIH
X
DOUT
Standby
VIH
VIH
X
X
X
X
High-Z
Output disable
VIH
VIH
X
X
X
X
High-Z
Reset
VIL
X
X
X
X
X
High-Z
Write
VIH
VIL
VIL
VIH
VIL
X
DIN
Read (array, status registers,
device identification register, or
query)
ADDRESS DQ0–DQ15
Table 7
Status Register Bit Definitions
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
STATUS
BIT # STATUS REGISTER BIT
DESCRIPTION
SR7
WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word
1 = Ready
program or block erase completion, before checking program
0 = Busy
or erase status bits.
SR6
ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in
Progress/Completed
When ERASE SUSPEND is issued, WSM halts execution and
sets both WSMS and ESS bits to “1.” ESS bit remains set to “1”
until an ERASE RESUME command is issued.
SR5
ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful BLOCK ERASE
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.
SR4
PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM
When this bit is set to “1,” WSM has attempted but failed to
program a word.
SR3
VPP STATUS (VPPS)
1 = VPP Low Detect, Operation
Abort
0 = VPP = OK
The VPP status bit does not provide continuous indication of
the VPP level. The WSM interrogates the VPP level only after
the program or erase command sequences have been entered
and informs the system if VPP < 0.9V. The VPP level is also
checked before the PROGRAM/ERASE is verified by the WSM.
SR2
PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
When PROGRAM SUSPEND is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a PROGRAM RESUME command is issued.
SR1
BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No Operation to Locked Blocks
If a PROGRAM or ERASE operation is attempted to one of the
locked blocks, this is set by the WSM. The operation specified
is aborted and the device is returned to read status mode.
SR0
RESERVED FOR FUTURE ENHANCEMENT This bit is reserved for future use.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
PROGRAMMING OPERATIONS
There are two CSM commands for programming:
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 3).
After the desired command code is entered (10h or
40h command code on DQ0–DQ7), the WSM takes over
and correctly sequences the device to complete the PROGRAM operation. Monitoring of the WRITE operation is
possible through the status register (see the Status Register section). During this time, the CSM responds only to
a PROGRAM SUSPEND command until the PROGRAM
operation has been completed, after which all commands
to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND
command (B0h). Once the WSM has reached the suspend state, it allows the CSM to respond only to READ
ARRAY, READ STATUS REGISTER, READ PROTECTION
CONFIGURATION, READ QUERY, PROGRAM SETUP, or
PROGRAM RESUME. During the PROGRAM SUSPEND
operation, array data should be read from an address
other than the one being programmed. To resume the
PROGRAM operation, a PROGRAM RESUME command
(D0h) must be issued to cause the CSM to clear the
suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and
program resume).
Taking RST# to VIL during programming aborts the
PROGRAM operation. During programming, VPP must
remain in the appropriate VPP voltage range as shown in
the recommended operating conditions table.
Block erasure inside the memory array sets all bits
within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations
within the array cannot be erased individually. The block
to be erased is selected by using any valid address within
that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE SETUP (20h) followed
by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A twocommand erase sequence protects against accidental
erasure of memory contents.
When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of
events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is
verified, all bits in the block are erased to logic 1 state, and
finally verification is performed to ensure that all bits are
correctly erased. The ERASE operation may be monitored through the status register (see the Status Register
section).
During the execution of an ERASE operation, the
ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the
WSM has reached the suspend state, it allows the CSM to
respond only to the READ ARRAY, READ STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME,
ERASE RESUME and LOCK SETUP (see the Block Locking
section). During the ERASE SUSPEND operation, array
data must be read from a block other than the one being
erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM
to clear the suspend state previously set (see Figure 7). It
is also possible to suspend an ERASE in any bank and
initiate a WRITE to another block in the same bank. After
the completion of a WRITE, an ERASE can be resumed by
writing an ERASE RESUME command.
ERASE OPERATIONS
An ERASE operation must be used to initialize all bits
in an array block to “1s.” After BLOCK ERASE CONFIRM
is issued, the CSM responds only to an ERASE SUSPEND
command until the WSM completes its task.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
15
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 4
Automated Word Programming
Flowchart
BUS
OPERATION COMMAND
WRITE
PROGRAM
SETUP
Data = 40h or 10h
Addr = Address of word to be
programmed
WRITE
WRITE
DATA
Data = Word to be
programmed
Addr = Address of word to be
programmed
Start
Issue PROGRAM SETUP
Command and
Word Address
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Issue Word Address
and Word Data
PROGRAM
SUSPEND Loop
Read Status Register
Bits
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
NO
NO
PROGRAM
SUSPEND?
SR7 = 1?
COMMENTS
WRITE
YES
YES
Full Status Register
Check (optional)1
Word Program
Completed
BUS
OPERATION COMMAND
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
SR1 = 0?
NO PROGRAM Attempted
on a Locked Block
YES
NO
SR3 = 0?
COMMENTS
Standby
Check SR1
1 = Detect locked block
Standby
Check SR32
1 = Detect VPP LOW
Standby
Check SR43
1 = Word program error
VPP Range Error
YES
NO
SR4 = 0?
Word Program Failed
YES
Word Program Passed
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
attempts.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 5
PROGRAM SUSPEND/
PROGRAM RESUME Flowchart
Start
Issue PROGRAM
SUSPEND Command
BUS
OPERATION COMMAND
COMMENTS
WRITE
Data = B0h
READ
Status register data
Toggle OE# or CE# to update
status register.
Standby
Check SR7
1 = Ready
Standby
Check SR2
1 = Suspended
WRITE
Read Status Register
Bits
PROGRAM
SUSPEND
READ
ARRAY
READ
WRITE
NO
SR7 = 1?
Data = FFh
Read data from block other
than that being programmed
PROGRAM
RESUME
Data = D0h
YES
NO
SR2 = 1?
PROGRAM
Complete
YES
Issue READ ARRAY
Command
Finished
Reading
?
NO
YES
Issue PROGRAM
RESUME Command
PROGRAM Resumed
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 6
BLOCK ERASE Flowchart
BUS
OPERATION COMMAND
WRITE
WRITE
ERASE
SETUP
Data = 20h
Block Addr = Address
within block to be erased
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
Start
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
ERASE
SUSPEND Loop
Read Status Register
Bits
COMMENTS
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
NO
NO
ERASE
SUSPEND?
SR 7 = 1?
YES
YES
Full Status Register
Check (optional)1
BLOCK ERASE
Completed
BUS
OPERATION COMMAND
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
NO
SR1 = 0?
ERASE Attempted
on a Locked Block
COMMENTS
Standby
Check SR1
1 = Detect locked block
Standby
Check SR32
1 = Detect VPP block
Standby
Check SR53
1 = BLOCK ERASE error
YES
NO
SR3 = 0?
VPP Range Error
YES
NO
SR5 = 0?
BLOCK ERASE Failed
YES
BLOCK ERASE Passed
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 7
ERASE SUSPEND/ERASE RESUME
Flowchart
Start
Issue ERASE
SUSPEND Command
Read Status Register
Bits
BUS
OPERATION COMMAND
COMMENTS
WRITE
Data = B0h
ERASE
SUSPEND
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready
Standby
Check SR6
1 = Suspended
WRITE
READ
ARRAY
READ
Read data from block
other than that being
erased.
NO
SR7 = 1?
WRITE
YES
Data = FFh
ERASE
RESUME
Data = D0h
NO
SR6 = 1?
YES
READ or
PROGRAM?
ERASE
Complete
PROGRAM
READ
Issue READ ARRAY
Command
PROGRAM
Loop
(Note 1)
NO
READ or
PROGRAM
Complete?
YES
Issue ERASE
RESUME Command
ERASE Continued2
NOTE: 1. See Word Programming Flowchart for complete programming procedure.
2. See BLOCK ERASE Flowchart for complete erasure procedure.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
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READ-WHILE-WRITE/ERASE
CONCURRENCY
It is possible for the device to read from one bank
while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a
READ CONCURRENCY operation, if a PROGRAM/ERASE
command is issued in bank a, then bank a changes to the
read status mode and bank b defaults to the read array
mode. The device will read from bank b if the latched
address resides in bank b (see Figure 8). Similarly, if a
PROGRAM/ERASE command is issued in bank b, then
bank b changes to read status mode and bank a defaults
to read array mode. When returning to bank a, the device
will read PROGRAM/ERASE status if the latched address
resides in bank a. A correct bank address must be
specified to read status register after returning from concurrent read in the other bank.
When reading the CFI or the chip protection register,
concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI table
or the chip protection register is only allowed if bank b is
in read array mode. For a top boot device, reading of the
CFI table or the chip protection register is only allowed if
bank a is in read array mode.
provides the read mode (burst, synchronous, or asynchronous), burst order, latency counter, and burst length.
After executing this command, the device returns to read
array mode.
READ CONFIGURATION
The device supports three read configurations: asynchronous, synchronous burst mode, and page mode. The
bit RCR15 (see Table 9) in the read configuration register
sets the read configuration. Asynchronous random mode
is the default read mode.
At power-up, the RCR is set to BBCFh.
Status registers and the device identification register
support asynchronous and single synchronous READ
operations only.
Figure 8
READ-While-WRITE Concurrency
READ CONFIGURATION REGISTER (RCR)
MODE
The SET READ CONFIGURATION REGISTER command is a WRITE operation to the read configuration
register (RCR). It is a two-cycle command sequence. Read
configuration setup is written, followed by a second write
that specifies the data to be written to the read configuration register. The data is placed on the address bus
A0–A15, and it is latched on the rising edge of ADV#, CE#,
or WE#, whichever occurs first. The read configuration
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
20
Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
suspended, and a WRITE to
another block in bank a
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
Bank b
1 - Reading bank a
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
suspended, and a WRITE to
another block in bank b
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
1 - Reading from bank b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 8
Read Configuration Register
RM
R
LC2
LC1
LC0
R
HDO
WC
15
14
13
12
11
10
9
8
BS
CC
R
R
BW
BL2
BL1
BL0
7
6
5
4
3
2
1
0
BIT #
15
14
DESCRIPTION
FUNCTION
Read Mode (RM)
0 = Synchronous Burst Access Mode
1 = Asynchronous/Page Access Mode (Default)
Reserved
Default = 0
Latency Counter (LC)
Sets the number of clock cycles before valid data out:
000 = Code 0 - reserved
001 = Code 1 - reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5 - reserved
110 = Code 6 - reserved
111 = Code 7 - reserved (Default)
10
Reserved
Default = 0
9
Hold Data Out (HDO)
Sets the data output configuration:
0 = Hold data for one clock
1 = Hold data for two clocks (Default)
8
Wait Configuration (WC)
Controls the behavior of the WAIT# output signal:
0 = WAIT# asserted during delay
1 = WAIT# asserted one data cycle before delay (Default)
7
Burst Sequence (BS)
Specifies the order in which data is addressed in synchronous burst
mode:
0 = Interleaved
1 = Linear (Default)
6
Clock Configuration (CC)
Defines the clock edge on which the BURST operation starts and
data is referenced:
0 = Falling edge
1 = Rising edge (Default)
Reserved
Default = 0
3
Burst Wrap (BW)
0 = Burst wraps within the burst length
1 = Burst no wrap (Default)
2-0
Burst Length (BL)
Sets the number of words the device will output in burst mode:
001 = 4 words
010 = 8 words
111 = Continuous burst (Default)
13-11
5-4
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
21
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
LATENCY COUNTER
The latency counter provides the number of clocks
that must elapse after ADV# is set active before data will
be available. This value depends on the input clock fre-
quency. See Table 9 for the specific input clock frequency
configuration code. See Figure 9 also.
Table 9
Clock Frequency vs. First Access Latency
MAX
LATENCY
CLK CYCLES
FREQUENCY PERIOD CONFIGURATION FOR FIRST
(MHz)
(ns)
COUNTER
DATA
-705
20
50
2
3
30
33
3
4
1
54
18.5
4
5
-804
20
50
2
3
30
33
3
4
40
25
4
5
SYNC
ACCESS
TIME (ns)
150
132
92.5
150
132
125
NOTE: 1. Maximum frequency for the MT28F322D18FH-705 device is 52 MHz.
Figure 9
Latency Counter
VIH
CLK
VIL
VIH
A0–A20
VALID
ADDRESS
VIL
VIH
ADV#
VIL
Code 2
VOH
VALID
OUTPUT
DQ0–DQ15
VO L
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 3
VOH
DQ0–DQ15
VO L
Code 4
VOH
DQ0–DQ15
VO L
UNDEFINED
Figure 10
Hold Data Output Configuration
Figure 11
Wired OR WAIT# Configuration
Wired OR
CLK
Hold
Data
1 CLK
Hold
Data
2 CLK
DQ0–DQ15
VALID
OUTPUT
DQ0–DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Burst CPU/
Wait State Logic
VALID
OUTPUT
Bus data
DATA
VALID
OUTPUT
WAIT#
READY #
MT28F322D18
DQ0–DQ15
.
.
WAIT#
MT28F322D18
DQ0–DQ15
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
22
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
HOLD DATA OUTPUT CONFIGURATION
The hold data output configuration specifies for how
many clocks data will be held valid. (See Figure 10.)
A Flash controller (CPU) is able to use this output
signal to drive banks of the devices. An internal 1MΩ
pull-up resistor holds WAIT# = 1 and allows wired OR’ing
multiple bank configurations, as shown in Figure 11.
WAIT# CONFIGURATION
The wait configuration bit, RCR8, sets the behavior of
the WAIT# output signal. The WAIT# signal can be active
during an output delay or one data cycle before delay
when continuous burst length is enabled. WAIT# = 1
indicates valid data when RCR8 = 0. WAIT# = 0 indicates
invalid data when RCR8 = 0. The setting of wait before or
wait during RCR8 will depend on the system and CPU
characteristic. If RCR3 = 1 (no wrap mode), then WAIT#
can also be enabled in a four- or eight-word burst if the
no-wrap burst crosses the first eight-word boundary.
BURST SEQUENCE
The burst sequence specifies the address order of the
data in synchronous burst mode. It can be programmed
as either linear or interleaved burst order. Continuous
burst length only supports linear burst order. See Table
10 for more details.
Table 10
Sequence and Burst Length
STARTING
ADDRESS
.
(DEC)
0
1
2
3
4
5
6
7
...
14
15
...
0
1
2
3
4
5
6
7
...
14
15
WRAP
NO
WRAP
RCR3
0
0
0
0
0
0
0
0
...
0
0
...
...
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
4-WORD
BURST LENGTH
8-WORD
BURST LENGTH
RCR3
LINEAR
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
INTERLEAVED
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
...
...
...
...
1
1
1
1
1
1
1
1
...
1
1
...
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
...
NA
NA
NA
NA
…
...
...
...
23
LINEAR
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
...
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
...
...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
...
...
NA
NA
NA
NA
NA
NA
NA
NA
...
CONTINUOUS
BURST
LINEAR
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-12-…
6-7-8-9-10-11-12-13-…
...
14-15-16-17-18-19-20-..
15-16-17-18-19-20-21-..
...
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
...
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
CLOCK CONFIGURATION
The clock configuration configures the starting burst
cycle, output data, and WAIT# signal to be asserted on the
rising or falling edge of the clock.
is the maximum delay, equal to the latency counter
setting.
The delay happens only once during a continuous
burst access. If the burst never crosses an eight-word
boundary, the WAIT# is not asserted. The WAIT# informs
the system if this output delay occurs.
BURST WRAP
The burst wrap option, RCR3, signals if a four- or an
eight-word linear burst access wraps within the burst
length or whether it crosses the eight-word boundary. In
wrap mode (RCR3 = 0) the four- or eight-word access will
wrap within the four or eight words, respectively. In nowrap mode (RCR3 = 1), the device operates similarly to a
continuous burst. For example, in a four-word burst, nowrap mode, the possible linear burst sequences that do
not assert WAIT# are:
0-1-2-3
8-9-10-11
1-2-3-4
9-10-11-12
2-3-4-5
10-11-12-13
3-4-5-6
11-12-13-14
4-5-6-7
12-13-14-15
The worst-case delay is seen at the end of the eightword boundary: 7-8-9-10 and 15-16-17-18. In a fourword burst, wrap mode, no WAIT# is asserted, and the
possible wrap sequences are:
0-1-2-3
5-6-7-4
1-2-3-0
6-7-4-5
2-3-0-1
7-4-5-6
3-0-1-2
8-9-10-11
4-5-6-7
9-10-11-8
etc.
When the continuous burst option is selected, the internal address wraps to 000000h if the device is read past the
last address.
WAIT# SIGNAL IN BURST MODE
In the continuous burst mode or in the four- or eightword burst mode with no wrap (RCR3 = 1), the output
WAIT# informs the system when data is valid. When
WAIT# is asserted during delay (RCR8 = 0), WAIT# = 1
indicates valid data, and WAIT# = 0 indicates invalid
data. If RCR8 = 0, WAIT# is asserted on the same cycle on
which the delay occurs. If RCR8 = 1, WAIT# is asserted one
cycle before the delay occurs.
BLOCK LOCKING
The Flash devices provide a flexible locking scheme
that allows each block to be individually locked or unlocked with no latency.
The devices offer two-level protection for the blocks.
The first level allows software-only control of block locking (for data, which needs to be changed frequently),
while the second level requires hardware interaction before locking can be changed (code which does not require
frequent updates).
Control signals WP#, DQ1, and DQ0 define the state
of a block; for example, state [001] means WP# = 0, DQ1 =
0 and DQ0 = 1.
Table 11 defines all of the possible locking states.
BURST LENGTH
The burst length defines the number of words the
device outputs. The device supports a burst length of four
or eight words. The device can also be set in continuous
burst mode. In this mode the device linearly outputs data
until the internal burst counter reaches the end of the
burstable address space. RCR2 sets the burst length.
NOTE: All blocks are software-locked upon completion of a power-up sequence.
LOCKED STATE
After a power-up sequence completion, or after a
reset sequence, all blocks are locked (states [001] or [101]).
This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block
will return an error on bit SR1 of the status register. The
status of a locked block can be changed to unlocked or
lock down using the appropriate software commands.
Writing the lock command sequence, 60h followed by
01h, can lock an unlocked block.
CONTINUOUS BURST LENGTH
During continuous burst mode operation, the Flash
memory may have an output delay when the burst sequence crosses the first eight-word boundary. Also, in
four- or eight-word bursts with the burst wrap set to no
wrap (RCR3 = 1), the Flash memory may have an output
delay when the burst sequence crosses the first eightword boundary. The starting address dictates whether or
not a delay occurs. If the starting address is aligned with
an eight-word boundary, the delay is not seen. For a fourword burst, if the starting address is aligned with a fourword boundary, a delay is not seen. If the starting address
is at the end of an eight-word boundary, the output delay
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to the
locked state when the device is reset or powered down.
An unlocked block can be locked or locked down using
the appropriate software command sequence, 60h followed by D0h (see Table 4).
24
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
LOCKED DOWN STATE
Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but their
protection status cannot be changed using software commands alone. A locked or unlocked block can be locked
down by writing the lock down command sequence, 60h
followed by 2Fh. Locked down blocks revert to the locked
state when the device is reset or powered down.
The LOCK DOWN function is dependent on the WP#
input. When WP# = 0, blocks in lock down [011] are
protected from program, erase, and lock status changes.
When WP# = 1, the lock down function is disabled ([111]),
and locked down blocks can be individually unlocked by
a software command to the [110] state, where they can be
erased and programmed. These blocks can then be
relocked [111] and unlocked [110] as desired while WP#
remains HIGH. When WP# goes LOW, blocks that were
previously locked down return to the locked down state
[011] regardless of any changes made while WP# was
HIGH. Device reset or power-down resets all locks, including those in lock down, to locked state (see Table 12).
UNLOCK command. It is also automatically set when
entering lock down. DQ1 indicates lock down status and
is set by the LOCK DOWN command. It can only be
cleared by reset or power-down, not by software. Table
11 shows the locking state transition scheme. The READ
ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands.
LOCKING OPERATIONS DURING ERASE SUSPEND
Changes to block lock status can be performed during
an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is
useful in the case when another block needs to be updated while an ERASE operation is in progress.
To change block locking during an ERASE operation,
first write the ERASE SUSPEND command (B0h), then
check the status register until it indicates that the ERASE
operation has been suspended. Next, write the desired
lock command sequence to block lock, and the lock status will be changed. After completing any desired LOCK,
READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME command (D0h).
If a block is locked or locked down during an
ERASE SUSPEND operation on the same block, the locking status bits will be changed immediately. Then, when
the ERASE is resumed, the ERASE operation will complete.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
READING A BLOCK’S LOCK STATUS
The lock status of every block can be read in the read
device identification mode. To enter this mode, write 90h
to the bank containing address 00h. Subsequent READs
at block address +00002 will output the lock status of that
block. The lowest two outputs, DQ0 and DQ1, represent
the lock status. DQ0 indicates the block lock/unlock status and is set by the LOCK command and cleared by the
Table 11
Block Locking State Transition
WP#
DQ1
DQ0
NAME
ERASE/PROG
ALLOWED
LOCK
UNLOCK
LOCK
DOWN
0
0
0
Unlocked
Yes
To [001]
No Change
To [011]
0
0
1
Locked (Default)
No
No Change
To [000]
To [011]
0
1
1
Lock Down
No
No Change
No Change
No Change
1
0
0
Unlocked
Yes
To [101]
No Change
To [111]
1
0
1
Locked
No
No Change
To [100]
To [111]
1
1
0
Lock Down
Disabled
Yes
To [111]
No Change
To [111]
1
1
1
Lock Down
Disabled
No
No Change
To [110]
No Change
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
25
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
CHIP PROTECTION REGISTER
unprogrammed. After DQ1 of the PR lock register is
programmed, no further programming is allowed on PR2.
The programming sequence is similar to array programming except that the PROTECTION REGISTER PROGRAMMING SETUP command (C0h) is issued instead of
an ARRAY PROGRAMMING SETUP command (40h), followed by the data to be programmed at addresses 85h–
88h.
To program the PR lock bit for PR2 (to prevent further
programming), use the above sequence on address 80h,
with data of FFFDh (DQ1 = 0).
A 128-bit chip protection register can be used to fulfill
the security considerations in the system (preventing the
device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to
program as desired. (See Figure 12).
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this
mode, READ cycles from addresses shown in Table 12
retrieve the specified information. To return to the read
array mode, write the READ ARRAY command (FFh). The
READ ARRAY command, FFh, must be issued to the bank
containing address 00h prior to issuing other commands.
Figure 12
Protection Register Memory Map
88h
PROGRAMMING THE CHIP PROTECTION REGISTER
The first 64 bits (PR1) of the protection register (addresses 81h–84h) are programmed with a unique identifier at the factory. DQ0 of the PR lock register (address
80h) is programmed to a “0” state, locking the first 64 bits
and preventing any further programming.
The second 64 bits (PR2) is a user area (addresses 85h–
88h), where the user can program any information into
this area as long as DQ1 of the PR lock register remains
85h
4 Words
User-Programmed
84h
4 Words
Factory-Programmed
81h
80h
PR Lock
0
Table 12
Chip Configuration Addressing1
ADDRESS2
DATA
Manufacturer Code (x16)
00000h
002Ch
Device Code
Top boot configuration
Bottom boot configuration
00001h
Block Lock Configuration
Block is unlocked
Block is locked
Block is locked down
XX002h
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 1
Read Configuration Register
00005h
RCR
Chip Protection Register Lock
80h
PR Lock
Chip Protection Register 1
81h–84h
Factory Data
Chip Protection Register 2
85h–88h
User Data
ITEM
·
·
·
·
·
44B4h
44B5h
NOTE: 1. Other locations within the configuration address space are reserved by
Micron for future use.
2. “XX” specifies the block address of lock configuration.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
26
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
2. If one bank is in program or erase mode and the
application starts burst access in that bank, then the
status register data is returned. The internal address
counter is incremented at every clock pulse.
ASYNCHRONOUS READ MODE
The asynchronous read mode is the default read configuration state. To use the device in an asynchronousonly application, ADV# and CLK must be tied to VSS and
WAIT# should be floated.
Toggling the address lines from A0 to A20, the access
is purely random (tAA).
The ADV# signal needs to be toggled to latch the
address, the CE# signal needs to go LOW, and the OE#
signal needs to go LOW. In this case the data is placed on
the data bus and the processor is ready to receive the
data.
3. If burst is started in one bank and the bank boundary
is crossed, and the other bank is in program or erase
mode, then the status register data is returned as the
first location of the bank. If the application keeps
clocking, the internal address counter gets
incremented at every clock cycle. If bank end is
crossed, then data from the other bank is returned as
shown in Figure 13.
SYNCHRONOUS BURST READ MODE
The burst read mode is used to achieve a faster data
rate than is possible with asynchronous read mode. The
rising edge of the clock CLK is used to latch the address
with CE# and ADV# LOW (see timing diagram: Single
Synchronous READ Operation). The burst read configuration is set in the read configuration register, where
frequency, data output, WAIT# signal, burst sequence,
clock, and burst length are configured setting the related
bits.
All blocks in both banks are burstable.
The BURST READ works across the bank boundary in
the following way:
Figure 13
Bank Boundary Wrapping
(Bottom Boot Example)
1. In READ operation there is no bank boundary as far as
burst access is concerned. If, for example, burst starts
in bank a, the application can keep clocking until
bank boundary is reached and then read from bank b.
If the application keeps clocking beyond bank b last
location, then the internal counter restarts from bank
a first address. (See Figure 13.)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
27
Bank a start address
0 00000h
Bank a end address
0 7FFFFh
Bank b start address
0 80000h
Bank b end address
1 FFFFFh
Bank a
bank boundary
Bank b
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©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ASYNCHRONOUS PAGE READ MODE
STANDBY MODE
After power-up or reset, the device operates in page
mode over the whole memory array. The page size can be
customized at the factory to four or eight words as required; but if no specification is made, the normal size is
eight words. The initial portion of the page mode cycle is
the same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A2 allows random access of other words in the page.
ICC supply current is reduced by applying a logic HIGH
level on CE# and RST# to enter the standby mode. In the
standby mode, the outputs are High-Z. Applying a CMOS
logic HIGH level on CE# and RST# reduces the current to
ICC4 (MAX). If the device is deselected during an ERASE
operation or during programming, the device continues
to draw current until the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
VPP/VCC PROGRAM AND ERASE
VOLTAGES
Substantial power savings are realized during periods
when the array is not being read and the device is in the
active mode. During this time the device switches to the
automatic power save mode. When the device switches
to this mode, ICC is reduced to a level comparable to ICC4.
Further power savings can be realized by applying a logic
HIGH level to CE# to place the device in standby mode.
The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data
from the last memory address read until a new address is
read. This mode is entered automatically if no address or
control signals toggle.
The Flash devices provide in-system programming
and erase with VPP in the 0.9V–2.2V range (VPP1). The 12V
VPP (VPP2) mode programming is offered for compatibility with existing programming equipment.
The device can withstand 100,000 WRITE/ERASE operations when VPP = VPP1 or 100 WRITE/ERASE operations
and 10 cumulative hours when VPP = VPP2.
In addition to the flexible block locking, the VPP
programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device.
When VPP is below VPPLK, any PROGRAM or ERASE operation will result in an error, prompting the corresponding
status register bit (SR3) to be set.
During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations are
allowed only when VPP is within the ranges specified in
Table 13.
When VCC is below VLKO or VPP is below VPPLK, any
WRITE/ERASE operation will be prevented.
DEVICE RESET
To correctly reset the Flash devices, the RST# signal
must be asserted (RST# = VIL) for a minimum of tRP. After
reset, the devices can be accessed for a READ operation
with a delayed access time of tRWH from the rising edge
of RST#. The circuitry used for generating the RST# signal
needs to be common with the rest of the system reset to
ensure that correct system initialization occurs. Please
refer to the timing diagram for further details.
POWER-UP SEQUENCE
Table 13
VPP Range (V)
In System (VPP1)
In Factory (VPP2)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
MIN
0.9
11.4
The following power-up sequence is recommended
to properly initialize internal chip operations:
• At power-up, RST# should be kept at VIL for 2µs after
VCC reaches VCC (MIN).
• VCCQ should not come up before VCC.
• VPP should be kept at VIL to maximize data integrity.
When the power-up sequence is completed, RST#
should be brought to VIH. To ensure a proper power-up,
the rise time of RST (10%–90%) should be < 10µs.
MAX
2.25
12.6
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
**Maximum DC voltage on VPP may overshoot to +13.5V
for periods < 20ns.
ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Ball Except VCC and VPP
with Respect to VSS ........................ -0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) .................... -0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ........................ -0.3V to +2.45V
Output Short Circuit Current ................................ 100mA
Operating Temperature Range ................ -40oC to +85oC
Storage Temperature Range .................. -55oC to +125oC
Soldering Cycle ............................................. 260oC for 10s
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
Operating temperature
VCC supply voltage (MT28F322D20)
MIN
MAX
UNITS
tA
-40
+85
o
VCC
1.80
2.20
V
NOTES
C
VCC supply voltage (MT28F322D18)
VCC
1.70
1.90
V
I/O supply voltage (MT28F322D20)
VCCQ
1.80
2.25
V
I/O supply voltage (MT28F322D18)
VCCQ
1.70
1.90
V
VPP voltage
VPP1
0.9
2.25
V
VPP in-factory programming voltage
VPP2
11.4
12.6
V
Block erase cycling (VPP = VPP1)
–
100,000
Cycles
Block erase cycling (VPP = VPP2)
–
100
Cycles
1
NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.
Figure 14
AC Input/Output Reference Waveform
VCC
Input
VCC/2
VCCQ/2
Test Points
Output
VSS
AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends
at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 15
Output Load Circuit
VCC
14.5K
I/O
14.5K
30pF
VSS
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
CAPACITANCE
(TA = +25ºC; f = 1 MHz)
PARAMETER/CONDITION
SYMBOL
TYP
MAX
UNITS
C
7
12
pF
COUT
9
12
pF
Input Capacitance
Output Capacitance
DC CHARACTERISTICS1
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Input Low Voltage
VIL
0
0.4
V
2
Input High Voltage
VIH
VCCQ - 0.4V
VCCQ
V
2
Output Low Voltage
IOL = 100µA
VOL
–
0.10
V
Output High Voltage
IOH = -100µA
VOH
VCCQ - 0.1V
–
V
VPP Lockout Voltage
VPPLK
–
0.4
V
VPP During PROGRAM/ERASE Operations
VPP1
0.9
2.2
V
VPP2
11.4
12.6
V
VCC Program/Erase Lock Voltage
VLKO
1
–
V
Input Leakage Current
IL
–
1
µA
Output Leakage Current
IOZ
–
1
µA
VCC Asynchronous Random Read, 70ns cycle
ICC1
–
15
mA
3, 4
VCC Page Mode Read Current, 70ns/30ns cycle
ICC2
–
5
mA
3, 4
VCC Burst Mode Read Current , 18.5ns cycle
ICC3
–
10
mA
4
VCC Standby Current
ICC4
–
50
µA
VCC Program Current
ICC5
–
55
mA
VCC Erase Current
ICC6
–
65
mA
VCC Erase Suspend Current
ICC7
–
50
µA
5
VCC Program Suspend Current
ICC8
–
50
µA
5
Read-While-Write Current
ICC9
–
80
mA
VPP Current
(Read, Standby, Erase Suspend, Program Suspend)
VPP ≤ VCC
VPP ≥ VCC
IPP1
–
–
1
200
µA
µA
NOTE: 1.
2.
3.
4.
5.
All currents are in RMS unless otherwise noted.
VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.
APS mode reduces ICC to approximately ICC4 levels.
Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.
ICC7 and ICC8 values are valid when the device is deselected. Any READ operation performed while in suspend mode
will have an additional current draw of suspend current (ICC7 or ICC8).
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ASYNCHRONOUS READ CYCLE TIMING REQUIREMENTS1
MT28F322D20 (VCC = 1.80V–2.25V) and MT28F322D18 (VCC = 1.70V–1.90V)
-70
PARAMETER
Address setup to ADV# HIGH
CE# LOW to ADV# HIGH
READ cycle time
Address to output delay
CE# LOW to output delay
ADV# LOW to output delay
ADV# pulse width LOW
ADV# pulse width HIGH
Address hold from ADV# HIGH
Page address access
OE# LOW to output delay
RST# HIGH to output delay
CE# or OE# HIGH to output High-Z
Output hold from address, CE# or OE# change
SYMBOL
tAVS
tCVS
tRC
tAA
tACE
tAADV
tVP
tVPH
tAVH
tAPA
tAOE
tRWH
tOD
tOH
MIN
10
10
-80
MAX
MIN
10
10
70
70
70
70
10
10
3
80
80
80
80
10
10
3
30
25
200
15
0
MAX
30
30
200
25
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
BURST READ CYCLE TIMING REQUIREMENTS1
(MT28F322D20)
-705
PARAMETER
CLK period
CLK HIGH (LOW) time
CLK fall (rise) time
Address valid setup to CLK
ADV# LOW setup to CLK
CE# LOW setup to CLK
CLK to output delay
Output hold from CLK
Address hold from CLK
CLK to WAIT# delay
CE# HIGH between subsequent synchronous READs
SYMBOL
tCLK
tKP
tKHKL
tAKS
tVKS
tCKS
tACLK
tKOH
tAKH
tKHTL
tCBPH
MIN
18.5
5
-804
MAX
MIN
25
7.5
MAX
3
7
7
9
5
7
7
13
15
3.5
10
20
5
10
15
20
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BURST READ CYCLE TIMING REQUIREMENTS1
(MT28F322D18)
-705
PARAMETER
CLK period
CLK HIGH (LOW) time
CLK fall (rise) time
Address valid setup to CLK
ADV# LOW setup to CLK
CE# LOW setup to CLK
CLK to output delay
Output hold from CLK
Address hold from CLK
CLK to WAIT# delay
CE# HIGH between subsequent synchronous READs
SYMBOL
tCLK
tKP
tKHKL
tAKS
tVKS
tCKS
tACLK
tKOH
tAKH
tKHTL
tCBPH
MIN
19.2
5
-804
MAX
MIN
25
7.5
3
7
7
9
5
7
7
13
17
3.5
10
20
5
10
15
20
MAX
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
WRITE CYCLE TIMING REQUIREMENTS
-70/-80
PARAMETER
HIGH recovery to WE# going LOW
CE# setup to WE# going LOW
Write pulse width
ADV# pulse width
Data setup to WE# going HIGH
Address setup to WE# going HIGH
ADV# setup to WE# going HIGH
Address setup to ADV# going HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
Address hold from ADV# going HIGH
Write pulse width HIGH
RST# pulse width
WP# setup to WE# going HIGH
VPP setup to WE# going HIGH
Write recovery before READ
WP# hold from valid SRD
VPP hold from valid SRD
WE# HIGH to data valid
SYMBOL
tRS
tCS
tWP
tVP
tDS
tAS
tVS
tAVS
tCH
tDH
tAH
tAVH
tWPH
tRP
tRHS
tVPS
tWOS
tRHH
tVPPH
tWB
MIN
150
0
50
10
50
50
50
10
0
0
1.5
3
30
100
0
200
50
0
0
MAX
tAA
+ 50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ERASE AND PROGRAM TIMING REQUIREMENTS
-70/-80
PARAMETER
4KW block program time
32KW block program time
Word program time
4KW block erase time
32KW block erase time
Program suspend latency
Erase suspend latency
Chip programming time (APA)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
TYP
40
320
8
0.3
0.5
5
5
33
MAX
800
6,400
10,000
6
6
10
20
20
UNITS
ms
ms
µs
s
s
µs
µs
s
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
SINGLE ASYNCHRONOUS READ OPERATION
A0–A20
VIH
VALID ADDRESS
VIL
tAA
tRC
tOD
VIH
ADV#
VIL
VIH
CE#
VIL
tACE
VIH
OE#
VIL
tOH
VIH
WE#
VIL
VOH
WAIT#
VOL
tAOE
VOH
DQ0–DQ15
RST#
High-Z
VALID OUTPUT
VOL
tRWH
VIH
VIL
UNDEFINED
READ TIMING PARAMETERS
MT28F322D20 (VCC = 1.80V–2.25V)
MT28F322D18 (VCC = 1.70V–1.90V)
-70
SYMBOL
MIN
-80
UNITS
tAOE
70
70
25
80
80
30
ns
ns
ns
tRC
70
80
ns
tACE
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
MIN
-70
MAX
tAA
MAX
SYMBOL
tRWH
tOD
tOH
34
MIN
0
-80
MAX
200
15
MIN
0
MAX
200
25
UNITS
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ASYNCHRONOUS PAGE MODE READ OPERATION
A3–A20
VIH
VALID ADDRESS
VIL
tRC
A0–A2
VIH
VALID
ADDRESS
VALID ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
tAA
VIH
ADV#
VIL
tOD
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
WAIT#
VIL
VOH
VOL
tAOE
VOH
DQ0–DQ15
tAPA
VALID
OUTPUT
High-Z
VOL
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
tRWH
VIH
RST#
VIL
UNDEFINED
READ TIMING PARAMETERS
MT28F322D20 (VCC = 1.80V–2.25V)
MT28F322D18 (VCC = 1.70V–1.90V)
-70
SYMBOL
tAA
MIN
-80
MAX
70
MIN
-70
MAX
80
UNITS
ns
tAPA
70
30
80
30
ns
ns
SYMBOL
tRC
tRWH
tOD
tAOE
25
30
ns
tOH
tACE
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
35
MIN
0
-80
MAX
70
200
15
MIN
0
MAX
80
200
25
UNITS
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
SINGLE SYNCHRONOUS READ OPERATION
CLK
VIH
VIL
tAKS
A0–A20
VIH
tAKH
VALID
ADDRESS
VIL
tAA
tAVH
ADV#
tVPH
VIH
VIL
tAADV
tVP
tVKS
CE#
tOD
VIH
VIL
tACE
tCVS
tCKS
OE#
VIH
VIL
WE#
VIH
VIL
WAIT#
VOH
DQ0–DQ15
tKOH
tAOE
VOL
tOH
VOH
VALID
OUTPUT
High-Z
VO L
tACLK
UNDEFINED
READ TIMING PARAMETERS
MT28F322D20 (VCC = 1.80V–2.25V)
READ TIMING PARAMETERS
MT28F322D18 (VCC = 1.70V–1.90V)
-705
SYMBOL
tAKS
tVKS
tCKS
MIN
7
7
9
tACLK
tKOH
tAKH
tCVS
MIN
7
7
3
10
10
tAADV
70
tVPH
10
10
tAVH
3
3
tAOE
25
tOD
tOH
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
tKOH
80
80
ns
ns
tAA
80
ns
ns
ns
tAADV
tVPH
10
10
ns
ns
tAVH
3
ns
ns
tOD
25
0
MIN
7
7
ns
ns
ns
30
15
0
SYMBOL
tAKS
tVKS
tCKS
5
10
10
10
10
UNITS
ns
ns
ns
ns
20
70
70
tACE
-705
MAX
13
15
tAA
tVP
-804
MAX
9
tACLK
tAKH
tCVS
tVP
20
5
10
10
70
70
70
ns
ns
80
ns
ns
ns
30
25
0
ns
ns
80
80
3
15
UNITS
ns
ns
ns
ns
ns
10
10
25
0
MAX
13
3
10
10
tAOE
36
MIN
7
7
17
tACE
tOH
-804
MAX
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
4-WORD SYNCHRONOUS BURST OPERATION
CLK
VIH
VIL
tAKS
A0–A20
VIH
tAKH
VALID
ADDRESS
VIL
tAA
tAVH
ADV#
tVPH
VIH
VIL
tAADV
tVP
tVKS
CE#
tOD
VIH
VIL
tACE
tCVS
tCKS
OE#
VIH
VIL
WE#
VIH
VIL
WAIT#
VOH
DQ0–DQ15
tKOH
tAOE
VOL
VOH
VALID
OUTPUT
High-Z
VO L
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
tACLK
UNDEFINED
READ TIMING PARAMETERS
MT28F322D20 (VCC = 1.80V–2.25V)
READ TIMING PARAMETERS
MT28F322D18 (VCC = 1.70V–1.90V)
-705
SYMBOL
tAKS
MIN
tVKS
7
7
tCKS
9
-804
MAX
MIN
-705
MAX
7
7
SYMBOL
MIN
ns
ns
tAKS
tVKS
7
7
tCKS
9
-804
MAX
MIN
MAX
7
7
UNITS
ns
ns
tKOH
3
5
ns
ns
ns
tKOH
3
5
ns
ns
ns
tAKH
10
10
10
10
ns
ns
tAKH
10
10
10
10
ns
ns
ns
ns
ns
tAA
ns
ns
tVP
tVPH
10
10
ns
ns
ns
tAVH
3
ns
tOH
tACLK
tCVS
15
tAA
tAADV
tVPH
10
10
tAVH
3
tAOE
80
80
80
10
10
3
25
15
tOD
tOH
20
70
70
70
tACE
tVP
13
UNITS
0
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
30
25
0
tACLK
tCVS
20
70
70
70
tACE
tAADV
tAOE
80
80
80
10
10
0
30
25
0
ns
ns
ns
ns
ns
3
25
15
tOD
37
13
17
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
CONTINUOUS BURST READ
SHOWING AN OUTPUT DELAY WITH RCR8 = 0(1)
CLK
VIH
VIL
tKP
tCLK
A0–A20
tKHKL
VIH
VIL
ADV#
VIH
VIL
CE#
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
WAIT#
tKHTL
tKHTL
VOH
VOL
DQ0–DQ15
VOH
VALID
OUTPUT
VO L
VALID
OUTPUT
INVALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tKOH
tACLK
UNDEFINED
READ TIMING PARAMETERS
MT28F322D20 (VCC = 1.80V–2.25V)
READ TIMING PARAMETERS
MT28F322D18 (VCC = 1.70V–1.90V)
-705
SYMBOL
tCLK
tKP
MIN
18.5
5
tKHKL
MIN
25
3.5
tKHTL
-705
MAX
SYMBOL
tCLK
ns
ns
ns
tKP
tKOH
20
ns
ns
5
15
UNITS
ns
5
20
7.5
3
15
tACLK
tKOH
-804
MAX
MIN
19.2
-804
MAX
5
tKHKL
MAX
7.5
3
17
tACLK
tKHTL
MIN
25
3.5
5
20
ns
ns
ns
20
ns
ns
5
15
UNITS
ns
NOTE: 1. tCLK = 19.2ns (MIN) for the MT28F322D18 device.
2. tACLK = 17ns (MAX) for the MT28F322D18 device.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
A0–A20
VIH
VALID ADDRESS
VIL
tAVS
tAVH
tAS
VALID ADDRESS
tAH
tVPH
VIH
ADV#
VALID ADDRESS
VIL
tVP
tVS
VIH
CE#
VIL
tCS
VIH
OE#
tWOS
tCH
tWPH
VIL
tWP
VIH
WE#
VIL
VIH
DQ0–DQ15
High-Z
VIL
CMD/
DATA
CMD/
DATA
tRS
STATUS
tDS
tCH
VIH
RST#
tWB
CMD
VIL
tRHS
tRHH
tVPS
tVPPH
VIH
WP#
VIL
VIPPH
VIPPLK
VPP V
IL
UNDEFINED
WRITE TIMING PARAMETERS
-70/-80
-70/-80
SYMBOL
MIN
tRS
150
0
ns
ns
70
10
70
ns
ns
ns
tWPH
70
70
ns
ns
tVPS
ns
ns
tRHH
tCH
10
0
tDH
0
ns
tWB
tCS
tWP
tVP
tDS
tAS
tVS
tAVS
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
MAX
UNITS
SYMBOL
tAH
tAVH
tVPH
tRHS
tWOS
tVPPH
39
MIN
1.5
3
MAX
UNITS
ns
ns
30
10
ns
ns
0
200
50
ns
ns
ns
0
0
ns
ns
tAA
+ 50
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
RESET OPERATION
CE#
VIH
VIL
RST#
VIH
VIL
tRP
OE#
VIH
VIL
DQ0–DQ15
VOH
VOL
tRWH
READ AND WRITE TIMING PARAMETERS
SYMBOL
tRWH
tRP
-70/-80
1.80V–2.25V
MIN
MAX
200
100
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
-70/-80
1.70V–1.90V
MIN
MAX
200
100
UNITS
ns
ns
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 15
CFI
OFFSET
DATA
DESCRIPTION
00
2Ch
Manufacturer code
01
B4h
Top boot block device code
B5h
Bottom boot block device code
02 – 0F
reserved
10, 11
0051, 0052
12
0059
13, 14
0003, 0000
Primary OEM command set
15, 16
0039, 0000
Address for primary extended table
17, 18
0000, 0000
Alternate OEM command set
19, 1A
0000, 0000
Address for OEM extended table
1B
0017
VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
Reserved
“QR”
“Y”
1C
0022
VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
1D
00B4
VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1E
00C6
VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1F
0003
Typical timeout for single byte/word program, 2n µs, 0000 = not supported
20
0000
Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
21
0009
Typical timeout for individual block erase, 2n ms, 0000 = not supported
22
0000
Typical timeout for full chip erase, 2n ms, 0000 = not supported
23
000C
Maximum timeout for single byte/word program, 2n µs, 0000 = not supported
24
0000
Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
25
0003
Maximum timeout for individual block erase, 2n ms, 0000 = not supported
26
0000
Maximum timeout for full chip erase, 2n ms, 0000 = not supported
27
0016
Device size, 2n bytes
28
0001
Bus Interface x16 = 1
29
0000
Flash device interface description 0000 = async
2A, 2B
0000, 0000
2C
0003
2D, 2E
002F, 0000
Top boot block device erase block region information 1, 8 blocks …
0007, 0000
Bottom boot block device erase block region information 1, 8 blocks …
0000, 0001
Top boot block device …..of 8KB
0020, 0000
Bottom boot block device …..of 8KB
000E, 0000
Top boot block 15 blocks of ….
000E, 0000
Bottom boot block 15 blocks of ….
2F, 30
31, 32
Maximum number of bytes in multi-byte program or page, 2n
Number of erase block regions within device (4K words and 32K words)
33, 34
0000, 0001
……64KB
35, 36
0007, 0000
Top boot block device …..48 blocks of
002F, 0000
Bottom boot block device …..48 blocks of
(continued on next page)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 15
CFI (continued)
OFFSET
DATA
DESCRIPTION
37, 38
0020, 0000
Top boot block device ……64KB
0000, 0001
Bottom boot block device ……64KB
39, 3A
0050, 0052
3B
0049
“I”
3C
0030
Major version number, ASCII
3D
0031
Minor version number, ASCII
3E
3F
40
41
00E6
0003
0000
0000
Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = no = 0
Bit 9 Simultaneous operation supported = yes = 1
42
0001
Program supported after erase suspend = yes
43, 44
0003, 0000
45
0018
46
00C0
VPP supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
47
0001
Number of protection register fields in JEDEC ID space
48, 49
0080, 0000
Lock bytes LOW address, lock bytes HIGH address
4A, 4B
0003, 0003
2n factory programmed bytes, 2n user programmable bytes
4C
0003
Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 50% block split
4D
0072
Burst Mode Type
0000 = No burst mode
00x1 = 4 words MAX
00x2 = 8 words MAX
00x3 = 16 words MAX
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst
4E
0002
Page Mode Type
0000 = No page mode
0001 = 4-word page
0002 = 8-word page
0003 = 16-word page
0004 = 32-word page
4F
0000
Not used
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
“PR”
Bit 0 block lock status active = yes; Bit 1 block lock down active = yes
VCC supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
58-BALL FBGA
0.80 ±0.075
SEATING PLANE
C
.10 C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .27mm
BALL A8
58X Ø 0.35 TYP
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.33
7.00 ±0.10
5.25
SUBSTRATE: PLASTIC LAMINATE
BALL #1 ID
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
0.75
TYP
BALL #1 ID
BALL A1
0.75
TYP
6.00 ±0.05
CL
12.00 ± .10
4.50
2.25 ±0.05
1.50 (4X)
CL
2.625 ±0.05
3.50 ±0.05
SUPPORT BALLS
(4X)
1.20 MAX
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
DATA SHEET DESIGNATION
No Mark:
This data sheet contains minimum and maximum limits specified over the complete power supply and
temperature range for production devices. Although considered final, these specifications are subject
to change, as further product development and data characterization sometimes occur.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
REVISION HISTORY
Rev. 4 .................................................................................................................................................................................... 7/02
• Removed PRELIMINARY DESIGNATION
• Updated Status Register section
• Updated command descriptions
• Updated Read-While-Write/EraseConcurrency section
• Updated timing diagrams
• Changed interpage read access voltage from 1.70V to 1.80V
• Changed intrapage read access voltage from 1.90V to 2.20V
Rev. 3, PRELIMINARY ........................................................................................................................................................ 3/02
• Added Note 4 to DC Characteristics table
Rev. 2, PRELIMINARY ........................................................................................................................................................ 1/02
• Added -70 and -80 speed grades for the MT28F322D18
• Removed -90 speed grade
• Updated DC Characteristics Table
• Updated CFI Table
• Updated tAH and tRWH specifications
• Changed data sheet from Advance to Preliminary
Original document, Rev. 1, ADVANCE ............................................................................................................................ 7/01
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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