Micron MT32LD3264AG-5X Dram module Datasheet

8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
DRAM
MODULE
MT8LD864A X, MT16LD1664A X,
MT32LD3264A X
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(H-14; 64MB)
(H-17; 128MB)
(H-30; 256MB)
• Eight-CAS# ECC pinout in a 168-pin, dual in-line
memory module (DIMM)
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
256MB (32 Meg x 64)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are LVTTLcompatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• Extended Data-Out (EDO) PAGE MODE access cycle
• Serial presence-detect (SPD)
OPTIONS
PIN SYMBOL PIN
1
VSS
43
2
DQ0
44
3
DQ1
45
4
DQ2
46
5
DQ3
47
6
VDD
48
7
DQ4
49
8
DQ5
50
9
DQ6
51
10
DQ7
52
11
DQ8
53
12
VSS
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
VDD
60
19
DQ14
61
20
DQ15
62
21
NC
63
22
NC
64
23
VSS
65
24
NC
66
25
NC
67
26
VDD
68
27
WE0#
69
28
CAS0#
70
29
CAS1#
71
30
RAS0#
72
31
OE0#
73
32
VSS
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10
80
39 NC (A12) 81
40
VDD
82
41
VDD
83
42
RFU
84
** 256MB version only
MARKING
• Package
168-pin DIMM (gold)
G
• Timing
50ns access
60ns access
-5
-6
• Access Cycle
EDO PAGE MODE
X
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
tRAC
tPC
tAA
tCAC
tCAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
PART NUMBERS
PART NUMBER
MT8LD864AG-5 X
MT8LD864AG-6 X
MT16LD1664AG-5 X
MT16LD1664AG-6 X
MT32LD3264AG-5 X*
MT32LD3264AG-6 X*
CONFIGURATION
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
32 Meg x 64
32 Meg x 64
SPEED
50ns
60ns
50ns
60ns
50ns
60ns
*Contact factory for availability
NOTE:
Pin symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They are
for reference only.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
1
SYMBOL
VSS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
VDD
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
RFU
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
NC
NC
NC
SDA
SCL
VDD
PIN SYMBOL PIN SYMBOL
85
VSS
127
VSS
86
DQ32
128
RFU
87
DQ33
129 NC/RAS3#**
88
DQ34
130
CAS6#
89
DQ35
131
CAS7#
90
VDD
132
RFU
91
DQ36
133
VDD
92
DQ37
134
NC
93
DQ38
135
NC
94
DQ39
136
NC
95
DQ40
137
NC
96
VSS
138
VSS
97
DQ41
139
DQ48
98
DQ42
140
DQ49
99
DQ43
141
DQ50
100
DQ44
142
DQ51
101
DQ45
143
VDD
102
VDD
144
DQ52
103
DQ46
145
NC
104
DQ47
146
RFU
105
NC
147
NC
106
NC
148
VSS
107
VSS
149
DQ53
108
NC
150
DQ54
109
NC
151
DQ55
110
VDD
152
VSS
111
RFU
153
DQ56
112
CAS4#
154
DQ57
113
CAS5#
155
DQ58
114 NC/RAS1#** 156
DQ59
115
RFU
157
VDD
116
VSS
158
DQ60
117
A1
159
DQ61
118
A3
160
DQ62
119
A5
161
DQ63
120
A7
162
VSS
121
A9
163
NC
122
A11
164
NC
123 NC (A13) 165
SA0
124
VDD
166
SA1
125
RFU
167
SA2
126
RFU
168
VDD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
GENERAL DESCRIPTION
The Micron® MT8LD864A X, MT16LD1664A X
and MT32LD3264A X are randomly accessed 64MB,
128MB and 256MB memories organized in a x64 configuration. They are specially processed to operate
from 3V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22/23 address bits, which are
entered 12 bits (A0-A11) at RAS# time and 11/12 bits
(A0-A11) at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE#
must be taken HIGH to disable the data-outputs prior
to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
toggle from valid data to High-Z and back to the same
valid data. If OE# is toggled or pulsed after CAS# goes
HIGH while RAS# remains LOW, data will transition
to and remain High-Z.
During an application, if the DQ outputs are wire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Independent of OE# control, the outputs will disable after
tOFF, which is referenced from the rising edge of RAS#
or CAS#, whichever occurs last. (Refer to the 16 Meg x
4 [MT4LC16M4H9] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (A0-A10/A11) are
executed at least every tREF, regardless of sequence. The
CBR REFRESH cycle will invoke the internal refresh
counter for automatic RAS# addressing.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGEMODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back
HIGH. EDO provides for CAS# precharge time (tCP) to
occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE#
is pulsed while RAS# and CAS# are LOW, data will
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presencedetect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide 8 unique DIMM/EEPROM
addresses.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LD864A X (64MB)
DQ0-DQ7
DQ8-DQ15
DQ0-DQ7
WE0#
WE#
OE0#
OE#
RAS0#
RAS#
CAS0#
CAS#
DQ16-DQ23
DQ0-DQ7
DQ0-DQ7
WE#
U1
WE#
U2
OE#
RAS#
CAS1#
CAS#
DQ0-DQ7
WE#
U3
OE#
A0ÐA11
DQ24-DQ31
RAS#
A0ÐA11
CAS#
U4
OE#
RAS#
A0ÐA11
12
12
12
DQ32-DQ39
DQ40-DQ47
DQ48-DQ55
CAS#
A0ÐA11
12
CAS2#
CAS3#
A0-A11
DQ0-DQ7
WE2#
WE#
OE2#
OE#
RAS2#
RAS#
CAS4#
CAS#
DQ0-DQ7
DQ0-DQ7
WE#
U5
WE#
U6
OE#
RAS#
CAS#
DQ0-DQ7
WE#
U7
OE#
A0ÐA11
DQ56-DQ63
RAS#
A0ÐA11
CAS#
U8
OE#
RAS#
A0ÐA11
CAS#
A0ÐA11
CAS5#
12
CAS6#
12
12
12
CAS7#
SPD
U1-U8 = MT4LC8M8C2
SCL
SDA
A0
A1
A2
SA0
SA1
SA2
VDD
U1-U8
VSS
U1-U8
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT16LD1664A X (128MB)
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
WE0#
WE#
DQ0-DQ3
WE#
U1
DQ8-DQ11
DQ0-DQ3
WE#
U2
DQ12-DQ15
DQ0-DQ3
WE#
U3
DQ16-DQ19
DQ0-DQ3
WE#
U4
DQ20-DQ23
DQ0-DQ3
WE#
U5
DQ24-DQ27
DQ0-DQ3
WE#
U6
DQ28-DQ31
DQ0-DQ3
WE#
U7
U8
OE0#
OE#
RAS0#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS0#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
12
12
12
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
OE#
OE#
OE#
OE#
OE#
OE#
OE#
CAS1#
CAS2#
CAS3#
A0-A11
DQ0-DQ3
WE2#
WE#
DQ0-DQ3
WE#
U9
DQ0-DQ3
WE#
U10
DQ0-DQ3
WE#
U11
DQ0-DQ3
WE#
U12
DQ0-DQ3
WE#
U13
DQ0-DQ3
WE#
U14
DQ0-DQ3
WE#
U15
U16
OE2#
OE#
RAS2#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS4#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
12
12
12
CAS5#
CAS6#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
CAS7#
SPD
U1-U16 = MT4LC16M4H9
SCL
SDA
A0
A1
A2
SA0
SA1
SA2
VDD
U1-U16
VSS
U1-U16
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT32LD3264A X (256MB)
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
WE0#
DQ0-DQ3
WE#
WE#
DQ0-DQ3
WE#
DQ12-DQ15
DQ0-DQ3
DQ16-DQ19
DQ0-DQ3
WE#
U2
U1
OE0#
DQ8-DQ11
WE#
U3
DQ20-DQ23
DQ0-DQ3
WE#
U4
DQ24-DQ27
DQ0-DQ3
WE#
U5
DQ28-DQ31
DQ0-DQ3
WE#
U6
U7
U8
OE#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
RAS0#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS0#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
CAS1#
CAS2#
12
12
12
CAS3#
A0-A11
DQ32-DQ35
DQ36-DQ39
DQ0-DQ3
DQ0-DQ3
DQ40-DQ43
DQ0-DQ3
DQ44-DQ47
DQ0-DQ3
DQ48-DQ51
DQ0-DQ3
DQ52-DQ55
DQ0-DQ3
DQ56-DQ59
DQ0-DQ3
DQ60-DQ63
DQ0-DQ3
WE2#
WE#
OE2#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
RAS2#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS4#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
12
WE#
WE#
U9
CAS5#
CAS6#
U10
WE#
U11
WE#
U12
WE#
U13
WE#
U14
12
WE#
U15
U16
12
12
CAS7#
DQ0-DQ3
DQ4-DQ7
DQ0-DQ3
DQ0-DQ3
WE#
WE#
U18
DQ0-DQ3
DQ0-DQ3
WE#
U19
DQ16-DQ19
WE#
U20
DQ20-DQ23
DQ0-DQ3
WE#
U21
DQ24-DQ27
DQ0-DQ3
WE#
U22
DQ28-DQ31
DQ0-DQ3
WE#
U23
U24
OE#
OE#
OE#
OE#
OE#
OE#
OE#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
DQ36-DQ39
DQ0-DQ3
DQ0-DQ3
WE#
WE#
DQ40-DQ43
DQ0-DQ3
WE#
U25
U26
12
DQ44-DQ47
DQ0-DQ3
DQ0-DQ3
WE#
U27
DQ48-DQ51
WE#
U28
12
DQ52-DQ55
DQ0-DQ3
WE#
U29
12
DQ56-DQ59
DQ0-DQ3
WE#
U30
12
DQ60-DQ63
DQ0-DQ3
WE#
U31
U32
OE#
OE#
OE#
OE#
OE#
OE#
OE#
OE#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
RAS#
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
CAS# A0ÐA11
12
12
12
12
SPD
12
12
12
12
U1-U32 = MT4LC16M4H9
SCL
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
DQ12-DQ15
OE#
DQ32-DQ35
RAS3#
DQ0-DQ3
WE#
U17
RAS1#
DQ8-DQ11
SDA
A0
A1
A2
SA0
SA1
SA2
VDD
U1-U32
VSS
U1-U32
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
30, 45, 114, 129
SYMBOL
RAS0#-RAS3#
TYPE
Input
28, 29, 46, 47, 112,
113, 130, 131
CAS0#-CAS7#
Input
27, 48
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-122
A0-A11
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
DQ0-DQ63
Input/
Output
RFU
–
VDD
Supply
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the
row-address bits. Two RAS# inputs allow for one x64
bank or two x32 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output
buffers and strobe the data inputs on WRITE cycles.
Eight CAS# inputs allow byte access control for any
memory bank configuration.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ31. WE2# controls
DQ32-DQ63. If WE# is LOW prior to CAS# going
LOW, the access is an EARLY WRITE cycle. If WE# is
HIGH while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
Output Enable: OE# is the input/output control for
the DQ pins. OE0# controls DQ0-DQ31. OE2# controls
DQ32-DQ63. These signals may be driven, allowing
LATE WRITE cycles.
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs
to the addressed DRAM location. BYTE WRITEs may
be performed by using the corresponding CAS#
select (x64 mode only). For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ±0.3V.
VSS
Supply
Ground.
82
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
83
SCL
Input
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs. These pins are used
to configure the presence-detect device.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an acknowledge after recognition of a start condition and
its slave address. If both the device and a write operation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by
the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
START
BIT
DATA STABLE
Figure 1
Data Validity
STOP
BIT
Figure 2
Definition of Start and Stop
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
Acknowledge Response From Receiver
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
0
1
2
3
4
DESCRIPTION
ENTRY (VERSION) BIT7
NUMBER OF BYTES USED BY MICRON
128
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
0
MEMORY TYPE
EDO PAGE MODE
0
NUMBER OF ROW ADDRESSES
12
0
NUMBER OF COLUMN ADDRESSES
11 (64MB)
0
12 (128MB, 256MB)
0
5
NUMBER OF BANKS
6
7
8
9
BIT6
0
0
0
0
0
0
BIT5
0
0
0
0
0
0
BIT4
0
0
0
0
0
0
BIT3
0
1
0
1
1
1
BIT2
0
0
0
1
0
1
BIT1
0
0
1
0
1
0
BIT0
0
0
0
0
1
0
HEX
80
08
02
0C
0B
0C
1 (64MB, 128MB)
2 (256MB)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
01
02
DATA WIDTH
DATA WIDTH (continued)
VOLTAGE INTERFACE
RAS# ACCESS TIME (tRAC)
x64
NONE
LVTTL
50ns (-5)
60ns (-6)
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
40
00
01
32
3C
10
CAS# ACCESS TIME (tCAC)
13ns (-5)
15ns (-6)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0D
0F
11
12
13
MODULE CONFIGURATION TYPE
REFRESH RATES
DRAM WIDTH (PRIMARY DRAM)
NONPARITY
15.625µs/NORMAL
x8 (64MB)
x4 (128MB, 256MB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
08
10
NONE
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
x
0
0
0
0
0
x
x
x
–
0
0
0
0
1
0
1
1
0
1
1
0
0
0
1
x
0
0
0
1
0
x
x
x
–
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
x
0
1
1
0
0
x
x
x
–
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
x
1
0
1
0
0
x
x
x
–
00
00
00
2A
36
33
3F
34
40
2C
FF
01
02
03
04
xx
01
02
03
04
00
xx
xx
xx
–
14
15-61
62
63
ERROR CHECKING DRAM DATA WIDTH
RESERVED
SPD REVISION
CHECKSUM FOR BYTES 0-62
64
65-71
72
MANUFACTURER’S JEDEC ID CODE
MANUFACTURER’S JEDEC CODE (CONT.)
MANUFACTURING LOCATION
73-90
91
MODULE PART NUMBER (ASCII)
PCB IDENTIFICATION CODE
92
93
94
95-98
99-125
IDENTIFICATION CODE (CONT.)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
MANUFACTURE SPECIFIC DATA (RSVD)
REV. 0
64MB -5
64MB -6
128MB -5
128MB -6
256MB -5
256MB -6
MICRON
1
2
3
4
0
NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”
2. x = Variable Data.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Voltage on VDD Pin Relative to VSS ........ -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to VSS ................................. -1V to +4.6V
Operating Temperature, TA (ambient) .. 0°C to +70°C
Storage Temperature (plastic) ........... -55°C to +125°C
Power Dissipation ................................................... 8W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
SIZE
MIN
MAX
SUPPLY VOLTAGE
VDD
ALL
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
ALL
2
VDD + 0.3
V
30
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
ALL
-0.5
0.8
V
30
64MB
128MB
256MB
64MB
128MB
256MB
64MB
128MB
256MB
64MB
128MB
256MB
-2
-4
-8
-16
-32
-64
-8
-16
-32
-8
-16
-16
2
4
8
16
32
64
8
16
32
8
16
16
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD + 0.3V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT:
DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V
CAS0#-CAS7#
II1
A0-A11
II2
WE0#, WE2#,
OE0#, OE2#
II3
RAS0#-RAS3#
II4
DQ0-DQ63
IOZ
64MB
128MB
256MB
-5
-5
-10
5
5
10
µA
VOH
ALL
2.4
–
V
VOL
ALL
–
0.4
V
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
UNITS NOTES
9
µA
µA
µA
µA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (VDD = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
-5
-6
ICC1
64MB
128MB
256MB
8
16
32
8
16
32
mA
ICC2
64MB
128MB
256MB
4
8
16
4
8
16
mA
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC3
64MB 1,400
128MB 2,720
256MB 2,736
1,320
2,560
2,576
mA
3, 24
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
ICC4
64MB 1,240
128MB 2,400
256MB 2,416
1,000
1,920
1,936
mA
3, 24
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
ICC5
64MB 1,400
128MB 2,720
256MB 2,736
1,320
2,560
2,576
mA
3, 24
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
ICC6
64MB 1,320
128MB 2,560
256MB 2,576
1,240
2,400
2,416
mA
3, 4
STANDBY CURRENT: TTL
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS
(RAS# = CAS# = VDD - 0.2V)
SYMBOL SIZE
CAPACITANCE
UNITS NOTES
MAX
PARAMETER
SYMBOL 64MB 128MB 256MB UNITS NOTES
Input Capacitance: A0-A11
CI1
46
86
168
pF
2
Input Capacitance: WE0#, WE2#, OE0#, OE2#
CI2
32
60
118
pF
2
Input Capacitance: RAS0#-RAS3#
CI3
32
60
60
pF
2
Input Capacitance: CAS0#-CAS7#
CI4
10
18
32
pF
2
Input Capacitance: SCL, SA0-SA2
CI5
6
6
6
pF
2
Input/Output Capacitance: DQ0-DQ63, SDA
CIO
12
12
22
pF
2
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column-address setup to CAS#
precharge during writes
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
-5
-6
SYMBOL
tAA
tACH
MIN
MAX
25
MIN
12
15
tAR
38
0
0
42
45
0
0
49
MAX
30
UNITS
ns
ns
tOEH
8
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEHC
5
5
4
0
0
10
5
5
0
0
ns
ns
ns
ns
ns
tASC
tASR
tAWD
tCAC
13
tCAH
8
8
8
0
3
8
tCAS
tCHR
tCLZ
tCOH
tCP
tCPA
10,000
15
10
10
10
0
3
10
28
tCRP
5
38
5
30
8
8
0
0
tCSH
tCSR
tCWD
tCWL
tDH
tDS
tOD
tOE
tOEP
tOES
tOFF
tORD
tPC
12
12
12
20
47
tPRWC
tRAC
35
5
45
5
35
10
10
0
0
9
9
50
50
84
11
0
0
tRAH
tRAS
tRASP
tRC
tRCD
tRCH
tRCS
11
15
15
15
25
56
50
tRAD
10,000
10,000
125,000
60
12
10
60
60
104
14
0
0
10,000
125,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
23
14
4
15
4
23
22
22
19, 27
19
13
17
16
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Refresh period (4,096 cycles)
RAS# precharge time
RAS# to CAS# precharge time
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
Output disable delay from WE# (CAS# HIGH)
WRITE command pulse width
WE# pulse width for output
disable when CAS# HIGH
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
-5
-6
SYMBOL
tREF
tRP
tRPC
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWHZ
tWP
tWPZ
MIN
5
10
5
10
UNITS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWRH
8
8
10
10
ns
ns
tWRP
12
30
5
0
13
116
67
13
2
8
38
0
MAX
64
50
MIN
40
5
0
15
140
79
15
2
10
45
0
12
MAX
64
50
15
NOTES
18
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
VDD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
INPUT LOW VOLTAGE: Logic 0; All inputs
V IL
-1
VDD x 0.3
OUTPUT LOW VOLTAGE: IOUT = 3mA
VDD x 0.7 VDD + 0.5
NOTES
V
V
VOL
–
0.4
V
INPUT LEAKAGE CURRENT: VIN = GND to VDD
I LI
–
10
µA
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
I LO
–
10
µA
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%
I SB
–
30
µA
POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz
ICC
–
2
mA
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (VDD = +3.3V ±0.3V)
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
tSCL
tSU:DAT
tSU:STA
tSU:STO
tWR
13
MIN
0.3
4.7
300
MAX
3.5
300
0
4
4
100
4.7
1
100
250
4.7
4.7
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
NOTES
19. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32
mode.
22.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
23. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. If tWCS > tWCS (MIN), the cycle is
an EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. tRWD, tAWD and tCWD define READMODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
design.
26.Measured with the specified current load and
100pF.
27. tOFF on an EDO module is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
28.The SPD EEPROM WRITE cycle time (tWR) is the
time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
29.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
30. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse
width ≤ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL
undershoot: VIL (MIN) = -2V for a pulse width ≤
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = +3.3V; f = 1 MHz.
3. ICC is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100µs is required after powerup, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 2ns for -5 and 2.5ns
for -6.
8. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
9. In addition to meeting the transition rate
specification, all input signals must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
10.If CAS# and RAS# = VIH, data output is High-Z.
11.If CAS# = VIL, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8V and VOH = 2V.
13.Requires that tAA and tCAC are not violated.
14.Requires that tAA and tRAC are not violated.
15.If CAS# is LOW at the falling edge of RAS#,
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP.
16.The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively
by tCAC (tRAC [MIN] no longer applied). With or
without the tRCD (MAX) limit, tAA and tCAC
must always be met.
17.The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively
by tAA (tRAC and tCAC no longer applied). With
or without the tRAD (MAX) limit, tAA, tRAC and
tCAC must always be met.
18.Either tRCH or tRRH must be satisfied for a READ
cycle.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ CYCLE
tRC
tRP
tRAS
RAS#
V IH
V IL
tCSH
tRSH
tCRP
CAS#
tCAS
tAR
tASC
tCAH
tRRH
V IH
V IL
tRAD
tRAH
tASR
ADDR
tRCD
V IH
V IL
tACH
ROW
ROW
COLUMN
tRCH
tRCS
WE#
V IH
V IL
tAA
tRAC
NOTE 1
tOFF
tCAC
tCLZ
DQ
V OH
V OL
OPEN
OE#
OPEN
VALID DATA
tOE
tOD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tACH
tAR
tASC
tASR
MIN
tCAS
tCLZ
tCRP
tCSH
tOD
MIN
-5
12
38
15
45
UNITS
ns
ns
ns
0
0
0
0
ns
ns
tRAH
ns
ns
ns
tRC
ns
ns
tRCS
ns
ns
tRRH
15
15
ns
tCAC
tCAH
-6
MAX
25
13
8
8
10,000
0
5
38
0
tOE
MAX
30
15
10
10
10,000
0
5
12
12
45
0
SYMBOL
tOFF
tRAC
tRAD
MIN
0
-6
MAX
12
50
9
9
50
tRAS
tRCD
tRCH
tRP
tRSH
MIN
0
MAX
15
60
12
10,000
10
60
10,000
UNITS
ns
ns
ns
ns
ns
84
11
0
104
14
0
ns
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EARLY WRITE CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tCSH
tRSH
tCRP
CAS#
tRCD
tCAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
tACH
ROW
COLUMN
tCWL
tRWL
tWCR
tWCH
tWCS
tWP
WE#
V IH
V IL
tDH
tDS
V
DQ V IOH
IOL
OE#
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCRP
tCSH
tCWL
tDH
tDS
tRAD
MIN
12
-6
MAX
MIN
15
-5
MAX
UNITS
ns
SYMBOL
tRAH
38
0
45
0
ns
ns
tRAS
0
8
8
0
10
10
ns
ns
ns
tRCD
10,000
10,000
tRC
tRP
tRSH
5
38
5
45
ns
ns
tRWL
8
8
10
10
ns
ns
tWCR
0
9
0
12
ns
ns
tWP
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
tWCH
tWCS
16
-6
MIN
9
MAX
MIN
10
MAX
UNITS
ns
50
84
10,000
60
104
10,000
ns
ns
11
30
13
14
40
15
ns
ns
ns
13
8
15
10
ns
ns
38
0
45
0
ns
ns
5
5
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
V IH
V IL
RAS#
tCSH
tCRP
tRCD
tPC
tCP
tCAS
tCAS
tRSH
tCAS
tCP
tCP
V IH
V IL
CAS#
tAR
tRAD
tRAH
tASR
V IH
V IL
ADDR
ROW
tACH
tACH
tACH
tASC
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRCS
tRCH
V IH
V IL
WE#
tAA
tRAC
tAA
tCPA
tCAC
tCAC
DQ
V OH
V OL
VALID
DATA
OPEN
tOFF
tOEHC
VALID
DATA
tOE
OE#
tCAC
tCLZ
tCOH
tCLZ
VALID
DATA
OPEN
tOE
tOD
tOES
V IH
V IL
tRRH
tAA
tCPA
tOD
tOES
tOEP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tACH
-6
MAX
MIN
25
tASC
12
38
0
15
45
0
tASR
0
0
tAR
tCAC
tCAH
tCAS
tCLZ
tCOH
tCP
13
8
8
0
3
8
tCPA
5
tCSH
38
0
tOE
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
UNITS
30
ns
ns
ns
ns
tOEHC
ns
ns
tPC
ns
ns
ns
tRAD
ns
ns
tRCD
ns
ns
tRCS
ns
ns
ns
tRRH
15
10
10
0
10,000
3
10
28
tCRP
tOD
10,000
-5
MAX
35
5
12
12
45
0
15
15
SYMBOL
tOEP
tOES
tOFF
MIN
5
5
4
0
tRASP
tRCH
tRP
tRSH
17
MIN
12
10
5
5
0
20
tRAC
tRAH
-6
MAX
UNITS
15
ns
ns
ns
ns
60
ns
ns
125,000
ns
ns
ns
25
50
9
9
50
MAX
125,000
12
10
60
11
0
14
0
ns
ns
0
30
0
40
ns
ns
0
13
0
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE EARLY WRITE CYCLE
tRP
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CAS#
tRCD
tPC
tCP
tCAS
tCAS
tRSH
tCAS
tCP
V IH
V IL
tAR
tACH
tRAD
tASR
ADDR
V IH
V IL
tRAH
tACH
tASC
ROW
tCAH
tACH
tCAH
tASC
COLUMN
tASC
COLUMN
tCWL
tWCH
tWCS
tCAH
COLUMN
tCWL
tWCH
tWCS
tWP
WE#
tWCS
tWP
ROW
tCWL
tWCH
tWP
V IH
V IL
tRWL
tWCR
tDS
V
DQ V IOH
IOL
OE#
tCP
tDH
tDS
VALID DATA
tDH
tDS
VALID DATA
tDH
VALID DATA
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCP
MIN
12
-6
MAX
MIN
15
-5
MAX
UNITS
ns
SYMBOL
tPC
45
ns
tRAD
9
12
0
0
10
10
ns
ns
ns
ns
tRAH
9
50
11
30
10
60
14
40
10,000
10,000
tRASP
tRCD
tRP
ns
ns
tRSH
45
10
10
ns
ns
ns
tWCH
tDH
38
8
8
tDS
0
0
ns
tWP
tCWL
MIN
25
0
0
8
8
10
5
tCSH
-6
MAX
38
8
5
tCRP
MIN
20
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
tRWL
tWCR
tWCS
18
125,000
MAX
UNITS
ns
ns
125,000
ns
ns
ns
ns
13
13
15
15
ns
ns
8
38
0
10
45
0
ns
ns
ns
5
5
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t RWC
t RAS
RAS#
t RP
V IH
V IL
t CSH
t RSH
t CRP
CAS#
t RCD
V IH
V IL
t AR
t RAD
t ASR
ADDR
t CAS
V IH
V IL
t ASC
t CAH
t ACH
t RAH
ROW
COLUMN
t RCS
WE#
ROW
t RWD
t CWL
t CWD
t RWL
t AWD
t WP
V IH
V IL
t AA
t RAC
t CAC
t DS
t CLZ
V
DQ V IOH
IOL
VALID D OUT
OPEN
t OE
OE#
t DH
VALID D IN
t OD
OPEN
t OEH
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tACH
tAR
tASC
tASR
tAWD
tCAS
tCLZ
tCRP
tCSH
tCWD
tCWL
tDH
tDS
MIN
25
-5
MAX
UNITS
SYMBOL
30
tOD
12
38
0
15
45
0
ns
ns
ns
ns
0
42
0
49
ns
ns
tRAD
ns
ns
ns
tRAS
tCAC
tCAH
-6
MAX
13
8
8
10,000
15
10
10
10,000
MIN
MAX
UNITS
0
12
12
0
15
15
ns
ns
ns
ns
8
tRAC
tRAH
tRCD
tRCS
0
5
0
5
ns
ns
tRP
38
30
45
35
ns
ns
tRWC
8
8
0
10
10
0
ns
ns
ns
tRWL
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MAX
tOE
tOEH
tRSH
tRWD
tWP
19
-6
MIN
10
50
9
9
50
11
0
60
12
10
10,000
60
14
0
ns
ns
10,000
ns
ns
ns
30
13
40
15
ns
ns
116
67
140
79
ns
ns
13
5
15
5
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRASP
RAS#
V IH
V IL
tCSH
tCRP
CAS#
tPRWC NOTE 1
tPC
tRCD
tCAS
tCP
tCAS
tRSH
tCP
tCAS
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
tRP
V IH
V IL
tASC
ROW
tCAH
tASC
COLUMN
tCAH
tASC
COLUMN
tCAH
COLUMN
ROW
tRWD
tRCS
WE#
tRWL
tCWL
tWP
tAWD
tCWD
tCWL
tWP
tAWD
tCWD
tAA
tAA
tDH
tCAC
tCLZ
V IOH
V IOL
tAA
tDH
tCPA
tDS
tCAC
tCLZ
VALID
D OUT
OPEN
tDH
tCPA
tDS
tDS
tCAC
tCLZ
VALID
DIN
VALID
D OUT
tOD
VALID
D IN
VALID
D OUT
tOD
tOE
OE#
tAWD
tCWD
V IH
V IL
tRAC
DQ
tCWL
tWP
tOE
VALID
D IN
OPEN
tOD
tOEH
tOE
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
MIN
-6
MAX
25
MIN
-5
MAX
30
UNITS
ns
SYMBOL
tOD
tAR
38
45
ns
tOE
tASC
0
0
42
0
0
49
tOEH
15
ns
ns
ns
ns
tRAD
10,000
ns
ns
tRASP
35
ns
ns
ns
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCP
13
8
8
0
8
tCPA
tCRP
tCSH
tCWD
tCWL
tDH
tDS
10,000
10
10
0
10
28
tPC
tPRWC
MAX
MIN
MAX
UNITS
0
12
12
0
15
15
8
10
ns
ns
ns
20
47
25
56
ns
ns
tRAC
tRAH
tRCD
tRCS
5
38
5
45
ns
ns
tRP
30
8
35
10
ns
ns
tRWD
8
0
10
0
ns
ns
tWP
tRSH
tRWL
-6
MIN
50
9
9
50
11
60
ns
ns
ns
125,000
ns
ns
12
10
125,000
60
14
0
30
13
0
40
15
ns
ns
ns
67
13
79
15
ns
ns
5
5
ns
NOTE: 1. tPC is for LATE WRITE cycles only.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t RP
t RASP
RAS#
V IH
V IL
t CSH
tPC
tCRP
CAS#
t RCD
tRSH
tPC
t CP
t CAS
t CP
t CAS
t CP
t CAS
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
t ACH
tRAH
tASC
ROW
tCAH
t ASC
COLUMN (A)
t CAH
COLUMN (B)
V IH
V IL
ROW
tWCS
tWCH
tAA
tAA
tCPA
tRAC
tCAC
tCAC
tCOH
DQ V IOH
V IOL
t CAH
COLUMN (N)
tRCH
tRCS
WE#
tASC
OPEN
VALID DATA (A)
t DS
t DH
t WHZ
VALID
DATA (B)
VALID DATA
IN
tOE
OE#
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
MIN
tAA
tACH
tASC
tASR
0
tCAC
tCAH
tCOH
tCP
8
tCPA
tCRP
tCSH
tDH
tDS
-5
MAX
UNITS
30
ns
ns
ns
ns
tOE
tRAD
9
ns
ns
tRAH
9
50
ns
ns
ns
tRCD
ns
ns
tRP
15
45
0
0
13
8
8
3
tCAS
MIN
25
12
38
0
tAR
-6
MAX
10,000
15
10
10
3
10,000
10
28
35
SYMBOL
tPC
tRASP
tRCH
tRCS
tRSH
5
45
ns
ns
tWCH
8
0
10
0
ns
ns
tWHZ
tWCS
21
-6
MAX
MIN
12
20
tRAC
5
38
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MIN
MAX
UNITS
15
ns
ns
ns
ns
25
50
60
12
125,000
10
60
125,000
ns
ns
11
0
0
14
0
0
ns
ns
ns
30
13
40
15
ns
ns
8
0
10
0
ns
ns
12
15
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(with WE#-controlled disable)
RAS#
V IH
V IL
tCSH
tRCD
tCRP
CAS#
tCAS
tCP
V IH
V IL
tAR
tRAD
tRAH
tASR
ADDR
V IH
V IL
tASC
ROW
tCAH
tASC
COLUMN
COLUMN
tRCS
WE#
tRCH
tWPZ
tRCS
V IH
V IL
tAA
tRAC
tCAC
tCLZ
DQ
V OH
V OL
tWHZ
OPEN
OPEN
VALID DATA
tOE
OE#
tCLZ
tOD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
tASC
tASR
MIN
38
0
0
tCAC
8
tCAS
8
0
8
tCP
tCRP
tCSH
MIN
5
38
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
-5
MAX
30
45
0
0
13
tCAH
tCLZ
-6
MAX
25
15
10
10,000
10
0
10
5
45
10,000
UNITS
ns
SYMBOL
tOD
MIN
0
-6
MAX
12
MIN
0
MAX
15
UNITS
ns
15
60
ns
ns
ns
tOE
tRAD
9
12
ns
ns
ns
ns
ns
tRAH
9
11
10
14
ns
ns
ns
ns
ns
tRCH
0
0
0
0
ns
ns
ns
ns
ns
tWPZ
12
50
tRAC
tRCD
tRCS
tWHZ
22
12
10
15
10
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
RAS#-ONLY REFRESH CYCLE
tRC
tRAS
RAS#
tRP
V IH
V IL
tRPC
tCRP
CAS#
V IH
V IL
tASR
ADDR
tRAH
V IH
V IL
ROW
ROW
V
DQ V OH
OL
WE#
OPEN
V IH
V IL
CBR REFRESH CYCLE
(Addresses, OE# = DON’T CARE)
tRP
RAS#
tRAS
tRP
NOTE 1
tRAS
V IH
V IL
tRPC
tCP
CAS#
V IH
V IL
DQ
V OH
V OL
tCSR
tCHR
OPEN
tWRP
WE#
tRPC
tCHR
tCSR
tWRH
tWRP
tWRH
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tASR
tCHR
tCP
tCRP
tCSR
tRAH
MIN
-6
MAX
MIN
-5
MAX
UNITS
SYMBOL
0
8
0
10
ns
ns
tRAS
8
5
10
5
ns
ns
tRP
5
9
5
10
ns
ns
tWRH
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
tRC
tRPC
tWRP
23
-6
MIN
MAX
MIN
MAX
UNITS
50
84
10,000
60
104
10,000
ns
ns
30
5
40
5
ns
ns
8
8
10
10
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
HIDDEN REFRESH CYCLE 20
(WE# = HIGH; OE# = LOW)
tRC
tRAS
RAS#
tRAS
V IH
V IL
tCRP
CAS#
tRP
tRSH
tRCD
tCHR
V IH
V IL
tAR
tRAD
tASR
ADDR
V IH
V IL
tRAH
tASC
ROW
tCAH
COLUMN
tAA
tRAC
tOFF
tCAC
tCLZ
V
DQ V IOH
IOL
OPEN
VALID DATA
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
SYMBOL
tAA
tAR
MIN
tASC
38
0
tASR
0
-6
MAX
25
MIN
-5
MAX
30
45
0
SYMBOL
tOFF
ns
ns
tORD
tRAD
tCAH
8
10
tCHR
8
0
10
0
ns
ns
tRC
ns
ns
ns
tRP
tCLZ
tCRP
tOD
13
5
0
tOE
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
12
12
15
5
0
15
15
MIN
0
tRAH
tRAS
tRCD
tRSH
24
-6
MAX
12
0
tRAC
ns
ns
ns
tCAC
0
UNITS
ns
MIN
0
UNITS
ns
60
ns
ns
10,000
ns
ns
ns
0
50
9
9
50
MAX
15
10,000
12
10
60
84
11
104
14
ns
ns
30
13
40
15
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
SPD EEPROM
tF
t HIGH
tR
t LOW
SCL
t HD:STA
t SU:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
tAA
tBUF
tDH
tF
tHD:DAT
tHD:STA
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
MIN
0.3
4.7
300
MAX
3.5
300
0
4
UNITS
µs
µs
ns
ns
µs
µs
SYMBOL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
tSU:STO
25
MIN
4
4.7
MAX
1
250
4.7
4.7
UNITS
µs
µs
µs
ns
µs
µs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
168-PIN DIMM
DF-16 (64MB)
FRONT VIEW
.200 (5.08)
MAX
5.256 (133.50)
5.244 (133.20)
.079 (2.00) R
(2X)
1.105 (28.07)
1.095 (27.81)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.250 (6.35) TYP
.118 (3.00)
TYP
1.661 (42.18)
.039 (1.00)R (2X)
2.625 (66.68)
.128 (3.25)
(2X)
.118 (3.00)
.039 (1.00)
TYP
.050 (1.27)
TYP
PIN 1 (PIN 85 ON BACKSIDE)
.054 (1.37)
.046 (1.17)
PIN 84 (PIN 168 ON BACKSIDE)
4.550 (115.57)
168-PIN DIMM
DF-27 (128MB)
FRONT VIEW
.350 (8.89)
MAX
5.256 (133.50)
5.244 (133.20)
.079 (2.00) R
(2X)
1.255 (31.88)
1.245 (31.62)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.250 (6.35) TYP
.118 (3.00)
TYP
1.661 (42.18)
.039 (1.00)R (2X)
2.625 (66.68)
.128 (3.25)
(2X)
.118 (3.00)
.039 (1.00)
TYP
PIN 1 (PIN 85 ON BACKSIDE)
.050 (1.27)
TYP
.054 (1.37)
.046 (1.17)
PIN 84 (PIN 168 ON BACKSIDE)
4.550 (115.57)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
8, 16, 32 MEG x 64
NONBUFFERED DRAM DIMMs
168-PIN DIMM
DF-41 (256MB)
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
.350 (8.89)
MAX
2.005 (51.93)
1.995 (50.67)
.079 (2.00) R
(2X)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.250 (6.35) TYP
.118 (3.00)
TYP
1.661 (42.18)
.039 (1.00)R (2X)
2.625 (66.68)
.128 (3.25)
(2X)
.118 (3.00)
.039 (1.00)
TYP
PIN 1 (PIN 85 ON BACKSIDE)
.050 (1.27)
TYP
.054 (1.37)
.046 (1.17)
PIN 84 (PIN 168 ON BACKSIDE)
4.550 (115.57)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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