Micron MT46V32M4TG-8 Double data rate ddr sdram Datasheet

PRELIMINARY‡
128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
FEATURES
PIN ASSIGNMENT (TOP VIEW)
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
66-Pin TSOP
x4
x8
x16
VDD
VDD
VDD
NC
DQ0
DQ0
VDDQ VDDQ VDDQ
NC
DQ1
NC
DQ0
DQ1
DQ2
VSSQ
VSSQ
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
VDDQ VDDQ VDDQ
NC
DQ5
NC
DQ1
DQ3
DQ6
VSSQ
VSSQ
VssQ
NC
DQ7
NC
NC
NC
NC
VDDQ VDDQ VDDQ
NC
NC LDQS
NC
NC
NC
VDD
VDD
VDD
NC
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
MARKING
32M4
16M8
8M16
TG
Configuration
Refresh Count
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)1
7.5ns @ CL = 2.5 (DDR266B)2
10ns @ CL = 2 (DDR200)3
-75Z
-75
-8
• Self Refresh
Standard
Low Power
none
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
32 Meg x 4
8 Meg x 4 x 4 banks
4K
Row Addressing
Bank Addressing
Column Addressing
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
16 Meg x 8
8 Meg x 16
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
1K (A0–A9)
512(A0–A8)
KEY TIMING PARAMETERS
SPEED
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
CLOCK RATE
GRADE
CL = 2**
CL = 2.5**
-75Z
-75
-8
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
125 MHz
DATA-OUT
ACCESS
WINDOW* WINDOW
2.5ns
2.5ns
3.4ns
±0.75ns
±0.75ns
±0.8ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.6ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
128MB DDR SDRAM PART NUMBERS
(Note: xx= -75, -75Z, or -8)
PART NUMBER
MT46V32M4TG-xx
MT46V32M4TG-xxL
MT46V16M8TG-xx
MT46V16M8TG-xxL
MT46V8M16TG-xx
MT46V8M16TG-xxL
CONFIGURATION
32 Meg x 4
32 Meg x 4
I/O DRIVE LEVEL
Full Drive
Full Drive
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
GENERAL DESCRIPTION
Full Drive
Full Drive
Standard
Low Power
Programmable Drive
Programmable Drive
Standard
Low Power
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compatible.
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quadbank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
REFRESH OPTION
Standard
Low Power
NOTE 1:
NOTE 2:
2
The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
Additionally, the x16 is divided in to two bytes —
the lower byte and upper byte. For the lower byte
(DQ0 through DQ7) DM refers to LDM and DQS
refers to LDQS; and for the upper byte (DQ8 through
DQ15) DM refers to UDM and DQS refers to UDQS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 32 Meg x 4 ...............
Functional Block Diagram – 16 Meg x 8 ...............
Functional Block Diagram – 8 Meg x 16 .............
Pin Descriptions ......................................................
4
5
6
7
Functional Description .........................................
Initialization ......................................................
Register Definition .............................................
Mode Register ...............................................
Burst Length ............................................
Burst Type ................................................
Read Latency ...........................................
Operating Mode ......................................
Extended Mode Register ...............................
DLL Enable/Disable .................................
9
9
9
9
9
10
11
11
12
12
Commands ............................................................
Truth Table 1 (Commands) ........................................
Truth Table 1A (DM Operation) ..................................
Deselect ..............................................................
No Operation (NOP) ........................................
Load Mode Register ..........................................
Active ................................................................
Read ................................................................
Write ................................................................
Precharge ...........................................................
Auto Precharge ..................................................
Burst Terminate .................................................
Auto Refresh ......................................................
Self Refresh ........................................................
13
13
13
14
14
14
14
14
14
14
14
14
15
15
Operation ..............................................................
Bank/Row Activation .......................................
Reads ................................................................
Read Burst ....................................................
Consecutive Read Bursts ..............................
Nonconsecutive Read Bursts .......................
Random Read Accesses ................................
Terminating a Read Burst ............................
Read to Write ...............................................
Read to Precharge .........................................
Writes ................................................................
Write Burst ...................................................
Consecutive Write to Write .........................
Nonconsecutive Write to Write ..................
16
16
17
18
19
20
21
23
24
25
26
27
28
29
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
Random Writes ............................................
Write to Read – Uninterrupting ..................
Write to Read – Interrupting .......................
Write to Read – Odd, Interrupting .............
Write to Precharge – Uninterrupting ..........
Write to Precharge – Interrupting ...............
Write to Precharge – Odd, Interrupting ......
Precharge ...........................................................
Power-Down .....................................................
Truth Table 2 (CKE) .................................................
Truth Table 3 (Current State, Same Bank) .....................
Truth Table 4 (Current State, Different Bank) .................
30
31
32
33
34
35
36
37
37
38
39
41
Operating Conditions
Absolute Maximum Ratings ....................................
DC Electrical and Operating Conditions ...................
AC Input Operating Conditions ...........................
Clock Input Operating Conditions .......................
Input Voltage .........................................................
Capacitance – x4, x8 ..............................................
IDD Specifications and Conditions – x4, x8 ...........
Capacitance – x16 ..................................................
IDD Specifications and Conditions – x16 ...............
AC Electrical Characteristics (Timing Table) ..........
Slew Rate Derating Tables ......................................
Derating Data Valid Window ...............................
43
43
43
44
45
46
46
47
47
48
49
51
Voltage and Timing Waveforms
Normal Output Drive Curves ...........................
Reduced Output Drive Curves (x16 only) ........
Output Timing – tDQSQ and tQH – x4, x8 .....
Output Timing – tDQSQ and tQH – x16 .........
Output Timing – tAC and tDQSCK .................
Input Timing .....................................................
Initialize and Load Mode Registers ..................
Power-Down Mode ..........................................
Auto Refresh Mode ...........................................
Self Refresh Mode .............................................
Reads
Bank Read – Without Auto Precharge ........
Bank Read – With Auto Precharge ..............
Writes
Bank Write – Without Auto Precharge .......
Bank Write – With Auto Precharge .............
Write – DM Operation ................................
66-pin TSOP dimensions ........................................
3
54
55
56
57
58
58
59
60
61
62
63
64
65
66
67
68
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 4
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
CK
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 8)
DLL
DATA
4
8
READ
LATCH
SENSE AMPLIFIERS
4
MUX
DRVRS
4
1
DQS
GENERATOR
8192
DQ0 DQ3, DM
COL0
I/O GATING
DM MASK LOGIC
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
1
DQS
1
MASK
1024
(x8)
COLUMN
DECODER
11
8
BANK
CONTROL
LOGIC
COLUMNADDRESS
COUNTER/
LATCH
DQS
INPUT
REGISTERS
10
8
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
1
1
1
4
4
4
4
2
8
RCVRS
4
DATA
CK
1
COL0
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 8
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
CK
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
DLL
DATA
8
16
READ
LATCH
SENSE AMPLIFIERS
8
MUX
DRVRS
8
1
DQS
GENERATOR
8192
DQ0 DQ7, DM
COL0
I/O GATING
DM MASK LOGIC
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
1
DQS
1
MASK
512
(x16)
COLUMN
DECODER
10
16
BANK
CONTROL
LOGIC
COLUMNADDRESS
COUNTER/
LATCH
DQS
INPUT
REGISTERS
9
16
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
1
1
1
8
8
8
8
2
16
RCVRS
8
DATA
CK
1
COL0
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 16
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
REFRESH
COUNTER
12
MODE REGISTERS
ROWADDRESS
MUX
12
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
CK
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
READ
LATCH
SENSE AMPLIFIERS
16
MUX
DRVRS
16
2
DQS
GENERATOR
8192
COL0
I/O GATING
DM MASK LOGIC
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
2
COLUMN
DECODER
COLUMNADDRESS
COUNTER/
LATCH
8
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
LDQS
UDQS
2
MASK
32
DQ0 DQ15,
LDM,
UDM
DQS
INPUT
REGISTERS
32
BANK
CONTROL
LOGIC
256
(x32)
9
DLL
DATA
16
32
2
2
2
16
16
4
32
RCVRS
16
16
16
DATA
CK
2
COL0
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
PIN DESCRIPTIONS
TSOP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
44
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.
24
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
23, 22, 21
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
47
20, 47
DM
LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. For the x16 , LDM is DM for DQ0DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8
26, 27
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
29-32, 35-40,
28, 41
A0–A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address
inputs also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE
REGISTER command.
2, 4, 5, 7, 8, 10,11, 13, 54
56, 57, 59, 60, 62, 63,65
DQ0–15
I/O
2, 5, 8, 11, 56, 59, 62, 65
5, 11, 56, 62
DQ0–7
DQ0–3
I/O
I/O
Data Input/Output: Data bus for x16 (4, 7, 10, 13, 54, 57, 60, and 63
are NC for x8), (2, 4, 7, 8,10, 13, 54, 57, 59, 60, 63, and 65 are NC
for x4).
Data Input/Output: Data bus for x8 (2, 8, 59, and 65 are NC for x4).
Data Input/Output: Data bus for x4.
(continued on next page)
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
PIN DESCRIPTIONS (continued)
TSOP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
51
16, 51
DQS
LDQS, UDQS
I/O
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS is
DQS for DQ8-DQ15. Pin 16 is NC on x4 and x8.
3, 9, 15, 55, 61
VDDQ
Supply
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved
noise immunity.
6, 12, 52, 58, 64
VSSQ
Supply
DQ Ground. Isolated on the die for improved noise immunity.
1, 18, 33
VDD
Supply
Power Supply: +2.5V ±0.2V.
34, 48, 66
VSS
Supply
Ground.
49
VREF
Supply
SSTL_2 reference voltage.
14, 17, 19, 25,
42, 43, 53
50
NC
–
No Connect: These pins should be left unconnected.
DNU
–
Do Not Use: Must float to minimize noise.
RESERVED NC PINS1
TSOP PIN NUMBERS
42
17
SYMBOL
A12
A13
TYPE
I
I
DESCRIPTION
Address input for 256Mb and 512Mb devices.
Address input for 1Gb devices.
NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. The 128Mb DDR SDRAM is internally
configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE
command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must
be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
mand, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by
another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL
and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset
and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the
all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the
mode register with the reset DLL bit deactivated (i.e., to
program operating parameters without resetting the
DLL) is required. Following these requirements, the
DDR SDRAM is ready for normal operation.
REGISTER DEFINITION
MODE REGISTER
The mode register is used to define the specific mode
of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 1. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed
correctly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A11 specify the
operating mode.
Initialization
DDR SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ
simultaneously, and then to VREF (and to the system
VTT). VTT must be applied after VDDQ to avoid device
latch-up, which may cause permanent damage to the
device. VREF can be applied any time after VDDQ but is
expected to be nominally coincident with VTT. Except
for CKE, inputs are not recognized as valid until after
VREF is applied. CKE is an SSTL_2 input but will detect
an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up
is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until
driven in normal operation (by a read access). After all
power supply and reference voltages are stable, and the
clock is stable, the DDR SDRAM requires a 200µs delay
prior to applying an executable command.
Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP com128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
9
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operating Mode CAS Latency BT Burst Length
0* 0*
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 1.
TABLE 1
BURST DEFINITION
Address Bus
Mode Register (Mx)
Burst
Length
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0 0
Reserved
Reserved
0
0 1
2
2
0
1 0
4
4
0
1 1
8
8
1
0 0
Reserved
Reserved
1
0 1
Reserved
Reserved
1
1 0
Reserved
Reserved
1
1 1
Reserved
Reserved
2
4
Burst Type
M3
0
Sequential
1
Interleaved
8
CAS Latency
M6 M5 M4
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
0
0
0
0
Valid
Normal Operation
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTE: 1. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access
within the block.
2. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access
within the block.
3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
M11 M10 M9 M8 M7 M6-M0 Operating Mode
0
Starting Column
Address
All other states reserved
Figure 1
Mode Register Definition
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 2.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
T0
T1
T2
READ
NOP
NOP
T2n
T3
TABLE 2
CAS LATENCY (CL)
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
-75Z
-75
-8
T3n
CK
NOP
CL = 2
DQS
DQ
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK
COMMAND
CL = 2.5
75 ≤ f ≤133
75 ≤ f ≤133
75 ≤ f ≤125
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A11
each set to zero, and bits A0-A6 set to the desired values.
A DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9-A11 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD MODE
REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A7-A11 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because unknown operation or incompatibility with future versions may result.
CK#
COMMAND
CL = 2
75 ≤ f ≤ 133
75 ≤ f ≤ 100
75 ≤ f ≤ 100
NOP
CL = 2.5
DQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
TRANSITIONING DATA
DON’T CARE
Figure 2
CAS Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
EXTENDED MODE REGISTER
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output
drive strength, and QFC#. These functions are controlled via the bits shown in Figure 3. The extended
mode register is programmed via the LOAD MODE
REGISTER command to the mode register (with
BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses
power. The enabling of the DLL should always be
followed by a LOAD MODE REGISTER command to
the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12 11 10 9
01 11
3
1
2
0
E23
E11 E10 E9 E8 E7 E6 E5 E4 E3
E2, E1, E0
0
0
0
0
0
0
0
0
0
Valid
–
–
–
–
–
–
–
–
–
–
Extended Mode
Register (Ex)
QFC DS DLL
E12
Output Drive Strength
The normal full drive strength for all outputs are
specified to be SSTL2, Class II. The x16 supports an
option for reduced drive. This option is intended for
the support of the lighter load and/or point-to-point
environments. The selection of the reduced drive
strength will alter the DQs and DQSs from SSTL2, Class
II drive strength to a reduced drive strength, which is
approximately 54 percent of the SSTL2, Class II drive
strength.
The Micron 128Mb (8 Meg x16) device supports a
programmable drive strength option.
E0
DLL
0
Enable
1
Disable
Drive Strength
0
Normal
1
Reduced
QFC Function
0
Disabled
–
Reserved
Operating Mode
Normal Operation
All other states reserved
Notes: 1. E13 and E12 (BA0 and BA1) must be “1, 0” to select the
Extended Mode Register (vs. the base Mode Register).
2. The reduced drive strength option is not supported on
the x4 and x8 versions and is only available on the D3
version of the x16 device.
3. The QFC option is not supported.
Figure 3
Extended Mode Register Definition
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
8 7 6 5 4
Operating Mode
Address Bus
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables
appear following the Operation section; these tables
provide current state/next state information.
TRUTH TABLE 1 – COMMANDS
(Note: 1)
NAME (FUNCTION)
ADDR
NOTES
DESELECT (NOP)
CS# RAS# CAS# WE#
H
X
X
X
X
9
NO OPERATION (NOP)
L
H
H
H
X
9
ACTIVE (Select bank and activate row)
L
L
H
H
Bank/Row
3
READ (Select bank and column, and start READ burst)
L
H
L
H
Bank/Col
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
Bank/Col
4
BURST TERMINATE
L
H
H
L
X
8
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
L
L
H
X
6, 7
LOAD MODE REGISTER
L
L
L
L
Op-Code
2
TRUTH TABLE 1A – DM OPERATION
NAME (FUNCTION)
DM
DQs
NOTES
Write Enable
L
Valid
10
Write Inhibit
H
X
10
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the
op-code to be written to the selected mode register.
3. BA0-BA1 provide bank address and A0-A11 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, 9 for x8, and 9, 11 for x4); A10 HIGH
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0-BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
DESELECT
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.
the memory array subject to the DM input logic level
appearing coincident with the data. If a given DM signal
is registered LOW, the corresponding data will be written
to memory; if the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
instruct the selected DDR SDRAM to perform a NOP
(CS# LOW). This prevents unwanted commands from
being registered during idle or wait states. Operations
already in progress are not affected.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A
PRECHARGE command will be treated as a NOP if
there is no open row in that bank (idle state), or if the
previously open row is already in the process of
precharging.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A11.
See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until
tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the
same individual-bank precharge function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it
is either enabled or disabled for each individual READ
or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, without violating tRAS(MIN), as described
for each burst type in the Operation section of this data
sheet. The user must not issue another command to the
same bank until the precharge time (tRP) is completed.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-Ai (where i = 8 for x16, 9 for x8, or 9, 11 for
x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst;
if auto precharge is not selected, the row will remain
open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0Ai (where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the
starting column location. The value on input A10 determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto precharge
is not selected, the row will remain open for subsequent
accesses. Input data appearing on the DQs is written to
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.
14
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation
of the DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs.
This command is nonpersistent, so it must be issued
each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 128Mb
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 15.625µs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum
absolute interval between any AUTO REFRESH
command and the next AUTO REFRESH command is
9 x 15.6µs (140.6µs). This maximum absolute interval
is to allow future support for DLL updates internal
to the DDR SDRAM to be restricted to AUTO
REFRESH cycles, without allowing excessive drift in
tAC between updates.
Although not a JEDEC requirement, to provide for
future functionality features, CKE must be active (High)
during the AUTO REFRESH period. The AUTO RE-
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
FRESH period begins when the AUTO REFRESH command is registered and ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled upon exiting
SELF REFRESH (200 clock cycles must then occur before
a READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a
sequence of commands. First, CK must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
tXSNR because time is required for the completion
of any internal refresh in progress. A simple algorithm
for meeting both refresh and DLL requirements is to
apply NOPs for 200 clock cycles before applying any
other command.
15
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
Operations
CK#
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be
issued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.
After a row is opened with an ACTIVE command,
a READ or WRITE command may be issued to that
row, subject to the tRCD specification. tRCD (MIN)
should be divided by the clock period and rounded up
to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a
READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz
clock (7.5ns period) results in 2.7 clocks rounded to 3.
This is reflected in Figure 5, which covers any case where
2 < tRCD (MIN)/tCK ≤ 3. (Figure 5 also shows the same
case for tRCD; the same procedure is used to convert
other specification limits from time units to clock
cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A11
RA
BA0,1
BA
RA = Row Address
BA = Bank Address
Figure 4
Activating a Specific Row in
a Specific Bank
T0
T1
T2
T3
T4
T5
T6
T7
ACT
NOP
NOP
ACT
NOP
NOP
RD/WR
NOP
CK#
CK
COMMAND
A0-A11
BA0, BA1
Row
Row
Bank x
Col
Bank y
tRRD
Bank y
tRCD
DON’T CARE
Figure 5
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK < 3
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
READS
READ bursts are initiated with a READ command,
as shown in Figure 6.
The starting column and bank addresses are provided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 7 shows
general timing for each possible CAS latency setting.
DQS is driven by the DDR SDRAM along with output
data. The initial LOW state on DQS is known as the
read preamble; the LOW state coincident with the last
data-out element is known as the read postamble.
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go
High-Z. A detailed explanation of tDQSQ (valid dataout skew), tQH (data-out window hold), the valid
data window are depicted in Figure 27. A detailed
explanation of tDQSCK (DQS transition skew to CK)
and tAC (data-out transition skew to CK) is depicted in
Figure 28.
Data from any READ burst may be concatenated
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued x cycles after the first READ command,
where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 8. A READ command can
be initiated on any clock cycle following a previous
READ command. Nonconsecutive read data is shown
for illustration in Figure 9. Full-speed random read
accesses within a page (or pages) can be performed as
shown in Figure 10.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
x4: A0–A9, A11
x8: A0–A9
x16: A0–A8
CA
x8: A11
x16: A9, A11
EN AP
A10
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
Figure 6
READ Command
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 2.5
DQS
DO
n
DQ
NOTE: 1. DO n = data-out from column n.
DON’T CARE
TRANSITIONING DATA
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 7
READ Burst
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
T2n
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
DO
b
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
DO
b
DON’T CARE
NOTE: 1.
2.
3.
4.
5.
6.
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b).
Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
Three subsequent elements of data-out appear in the programmed order following DO n.
Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies only when READ commands are issued to same device.
Figure 8
Consecutive READ Bursts
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
Bank,
Col n
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
Bank,
Col n
DO
b
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK#
CK
READ
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
NOTE: 1.
2.
3.
4.
5.
6.
DO
b
DON’T CARE
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b).
Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
Three subsequent elements of data-out appear in the programmed order following DO n.
Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutive READs.
Figure 9
Nonconsecutive READ Bursts
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
T2n
T3
T3n
T4
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
NOP
CL = 2
DQS
DO
n
DQ
DO
n'
T2n
DO
x
T0
T1
T2
T3
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
DO
x'
T3n
DO
b
T4
DO
b'
T4n
DO
g
T5
T5n
CK#
CK
NOP
NOP
CL = 2.5
DQS
DO
n
DQ
DO
n'
DO
x
DON’T CARE
NOTE: 1.
2.
3.
4.
5.
DO
x'
DO
b
DO
b'
TRANSITIONING DATA
DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).
n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.
READs are to an active row in any bank.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 10
Random READ Accesses
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
has a longer bus idle time. (tDQSS [MIN] and tDQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank
provided that auto precharge was not activated. The
PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of
desired data element pairs (pairs are required by the 2nprefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP
is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
READs (continued)
Data from any READ burst may be truncated with
a BURST TERMINATE command, as shown in Figure
11. The BURST TERMINATE latency is equal to the
READ (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12.
The tDQSS (MIN) case is shown; the tDQSS (MAX) case
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
READ
BST5
NOP
T2n
T3
T4
T5
NOP
NOP
NOP
T3
T4
T5
NOP
NOP
NOP
CK#
CK
COMMAND
ADDRESS
Bank a,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
READ
BST5
NOP
T2n
CK#
CK
COMMAND
ADDRESS
Bank a,
Col n
CL = 2.5
DQS
DO
n
DQ
NOTE: 1.
2.
3.
4.
5.
DO n = data-out from column n.
DON’T CARE
TRANSITIONING DATA
Burst length = 4.
Subsequent element of data-out appears in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
BST = BURST TERMINATE command, page remains open.
Figure 11
Terminating a READ Burst
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
T2n
COMMAND
READ
BST7
NOP
ADDRESS
Bank,
Col n
T3
T4
T4n
T5
T5n
CK#
CK
WRITE
NOP
NOP
Bank,
Col b
tDQSS
(MIN)
CL = 2
DQS
DO
n
DQ
DI
b
DM
T0
T1
T2
T2n
READ
BST7
NOP
T3
T4
T5
T5n
CK#
CK
COMMAND
ADDRESS
NOP
WRITE
NOP
Bank a,
Col n
tDQSS
(MIN)
CL = 2.5
DQS
DO
n
DQ
DI
b
DM
NOTE: 1. DO n = data-out from column n.
DON’T CARE
TRANSITIONING DATA
2. DI b = data-in from column b.
3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2,
the BST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC, tDQSCK, and tDQSQ.
7. BST = BURST TERMINATE command, page remains open.
Figure 12
READ to WRITE
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
T2n
READ
NOP
PRE
T3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND6
Bank a,
Col n
ADDRESS
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DO
n
DQ
T0
T1
T2
T2n
READ
NOP
PRE
T3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND6
Bank a,
(a or all)
Bank a,
Col n
ADDRESS
NOP
Bank a,
Row
tRP
CL = 2.5
DQS
DO
n
DQ
DON’T CARE
TRANSITIONING DATA
DO n = data-out from column n.
Burst length = 4, or an interrupted burst of 8.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.
A READ command with AUTO-PRECHARGE enabled would cause a precharge to be performed
at x number of clock cycles after the READ command, where x = BL / 2.
7. PRE = PRECHARGE command; ACT = ACTIVE command.
NOTE: 1.
2.
3.
4.
5.
6.
Figure 13
READ to PRECHARGE
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
WRITES
WRITE bursts are initiated with a WRITE command, as shown in Figure 14.
The starting column and bank addresses are provided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and
the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element
is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 percent
to 125 percent of one clock cycle). All of the WRITE
diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX])
might not be intuitive, they have also been included.
Figure 15 shows the nominal case and the extremes of
tDQSS for a burst of 4. Upon completion of a burst,
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data
will be ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the
previous WRITE command. The first data element
from the new burst is applied after either the last
element of a completed burst or the last desired data
element of a longer burst which is being truncated. The
new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number
of desired data element pairs (pairs are required by the
2n-prefetch architecture).
Figure 16 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.
Data for any WRITE burst may be followed by a
subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met
as shown in Figure 19.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
x4: A0–A9, A11
x8: A0–A9
x16: A0–A8
CA
x8: A11
x16: A9, A11
EN AP
A10
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
Figure 14
WRITE Command
array, and any subsequent data-in should be masked
with DM as shown in Figure 21.
Data for any WRITE burst may be followed by a
subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst, tWR
should be met as shown in Figure 22.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in Figures 23 and 24. Note that only the data-in pairs that are
registered prior to the tWR period are written to the
internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until tRP is met.
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T2
COMMAND
WRITE
NOP
NOP
ADDRESS
Bank a,
Col b
T2n
T3
CK#
CK
NOP
tDQSS (NOM)
DQS
tDQSS
DI
b
DQ
DM
tDQSS (MIN)
DQS
DQ
tDQSS
DI
b
DM
tDQSS (MAX)
DQS
DQ
tDQSS
DI
b
DM
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed
order following DI b.
3. An uninterrupted burst of 4 is shown.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
Figure 15
WRITE Burst
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
tDQSS (NOM)
WRITE
NOP
NOP
NOP
Bank,
Col n
tDQSS
DQS
DI
b
DQ
DI
n
DM
DON’T CARE
NOTE: 1.
2.
3.
4.
5.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc.
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
Figure 16
Consecutive WRITE to WRITE
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
tDQSS (NOM)
NOP
WRITE
NOP
NOP
Bank,
Col n
tDQSS
DQS
DI
n
DI
b
DQ
DM
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Figure 17
Nonconsecutive WRITE to WRITE
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
T1n
T2
T2n
T3
T3n
T4
COMMAND
WRITE
WRITE
WRITE
WRITE
WRITE
ADDRESS
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
tDQSS (NOM)
DQS
DI
b
DQ
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DM
DON’T CARE
NOTE: 1.
2.
3.
4.
TRANSITIONING DATA
DI b, etc. = data-in for column b, etc.
b', etc. = the next data-in following DI b, etc., according to the programmed burst order.
Programmed burst length = 2, 4, or 8 in cases shown.
Each WRITE command may be to any bank.
Figure 18
Random WRITE Cycles
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
NOP
READ
NOP
NOP
T6n
CK#
CK
COMMAND
NOP
tWTR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
DON’T CARE
TRANSITIONING DATA
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
tWTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to same device. However, the READ and WRITE commands may be
to different devices, in which case tWTR is not required and the READ command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
NOTE: 1.
2.
3.
4.
5.
Figure 19
WRITE to READ – Uninterrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
NOP
T5n
T6
CK#
CK
COMMAND
NOP
NOP
tWTR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
NOTE: 1.
2.
3.
4.
5.
6.
7.
DON’T CARE
TRANSITIONING DATA
DI b = data-in for column b.
An interrupted burst of 4 or 8 is shown; two data elements are written.
One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would
mask the last two data elements.
Figure 20
WRITE to READ – Interrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
NOP
tWTR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
Bank a,
Col n
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DI
b
DQ
DI
n
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DQ
DI
b
DI
n
DM
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last
four data elements.
Figure 21
WRITE to READ – Odd Number of Data, Interrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
NOP
NOP
PRE7
NOP
CK#
CK
COMMAND
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE
commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be
applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
NOTE: 1.
2.
3.
4.
5.
Figure 22
WRITE to PRECHARGE – Uninterrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
PRE9
NOP
T6
CK#
CK
COMMAND
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
NOP
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DI
b
DM
DON’T CARE
TRANSITIONING DATA
DI b = data-in for column b.
Subsequent element of data-in is applied in the programmed order following DI b.
An interrupted burst of 4 is shown; two data elements are written.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same bank.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
Figure 23
WRITE to Precharge – Interrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
PRE9
NOP
T6
CK#
CK
COMMAND
NOP
NOP
tWR
ADDRESS
tDQSS (NOM)
Bank a,
Col b
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DI
b
DQ
DM
DON’T CARE
TRANSITIONING DATA
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
DI b = data-in for column b.
Subsequent element of data-in is applied in the programmed order following DI b.
An interrupted burst of 4 is shown; one data element is written.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same bank.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T1n, T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
command would mask the last two data elements.
9. PRE = PRECHARGE command.
Figure 24
WRITE to PRECHARGE – Odd Number of Data, Interrupting
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
PRECHARGE
The PRECHARGE command (Figure 25) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP) after
the PRECHARGE command is issued. Input A10 deter-
mines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or
WRITE commands being issued to that bank.
CK#
POWER-DOWN (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress: from the
issuing of a READ or WRITE command until completion of the burst. Thus a clock suspend is not supported. For READs, a burst completion is defined when
the Read Postamble is satisfied; For WRITEs, a burst
completion is defined when the Write Postamble is
satisfied.
Power-down (Figure 26) is entered when CKE is
registered LOW. If power-down occurs when all banks
are idle, this mode is referred to as precharge powerdown; if power-down occurs when there is a row active
in any bank, this mode is referred to as active powerdown. Entering power-down deactivates the input
and output buffers, excluding CK, CK#, and CKE.
For maximum power savings, the DLL is frozen during
a precharge power-down. Exiting power-down requires the device to be at the same voltage and frequency as when it entered power-down. However,
power-down duration is limited by the refresh requirements of the device (tREFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11
ALL BANKS
A10
ONE BANK
BA0,1
BA
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
Figure 25
PRECHARGE Command
T0
T1
CK#
T2 ( (
Ta0
CK
CKE
((
))
VALID
No READ/WRITE
access in progress
NOP
((
))
((
))
NOP
Enter power-down mode
Figure 26
Power-Down
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
Ta2
tIS
tIS
COMMAND
Ta1
))
((
))
37
VALID
Exit power-down mode
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
H
NOTE: 1.
2.
3.
4.
5.
L
H
L
CURRENT STATE
COMMAND n
ACTION n
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Power-Down
DESELECT or NOP
Exit Power-Down
Self Refresh
DESELECT or NOP
Exit Self Refresh
All Banks Idle
DESELECT or NOP
Precharge Power-Down Entry
Bank(s) Active
DESELECT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFRESH
NOTES
5
Self Refresh Entry
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n – COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
Idle
Row Active
COMMAND/ACTION
NOTES
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
H
L
H
READ (select column and start READ burst)
10
L
H
L
L
WRITE (select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
8
Read
L
H
L
H
READ (select column and start new READ burst)
(Auto-
L
H
L
L
WRITE (select column and start WRITE burst)
Precharge
L
L
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (select column and start READ burst)
(Auto-
L
H
L
L
WRITE (select column and start new WRITE burst)
Precharge
L
L
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
10
10, 12
10, 11
10
8, 11
Disabled)
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in
the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT
or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
Truth Table 3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once
tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the “row active” state.
Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP
commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for
precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n – COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
COMMAND/ACTION
NOTES
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
Idle
X
X
X
X
Any Command Otherwise Allowed to Bank m
Row
L
L
H
H
ACTIVE (select and activate row)
Activating,
L
H
L
H
READ (select column and start READ burst)
7
Active, or
L
H
L
L
WRITE (select column and start WRITE burst)
7
Precharging
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (select and activate row)
(Auto-
L
H
L
H
READ (select column and start new READ burst)
Precharge
L
H
L
L
WRITE (select column and start WRITE burst)
Disabled)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (select and activate row)
7
7, 9
(Auto-
L
H
L
H
READ (select column and start READ burst)
Precharge
L
H
L
L
WRITE (select column and start new WRITE burst)
7,8
Disabled)
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (select and activate row)
(With Auto-
L
H
L
H
READ (select column and start new READ burst)
Precharge)
L
H
L
L
WRITE (select column and start WRITE burst)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (select and activate row)
(With Auto-
L
H
L
H
READ (select column and start READ burst)
7, 3a
Precharge)
L
H
L
L
WRITE (select column and start new WRITE burst)
7, 3a
L
L
H
L
PRECHARGE
7
7, 3a
7, 9, 3a
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and
the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state
that the given command is allowable). Exceptions are covered in the notes below.
(Notes continue on next page)
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
41
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©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTE (continued):
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read with Auto
Precharge Enabled: See following text – 3a
Write with Auto
Precharge Enabled: See following text – 3a
3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be
broken into two parts: the access period and the precharge period. For read with auto precharge,
the precharge period is defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR
measured as if auto precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or tRP) begins.
During the precharge period of the READ with auto precharge enabled or WRITE with auto
precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may
be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank
may be applied. In either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
This means concurrent auto precharge is not supported.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by
the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
VDD Supply Voltage
Relative to VSS ...................................... -1V to +3.6V
VDDQ Supply
Voltage Relative to VSS ........................ -1V to +3.6V
VREF and Inputs Voltage
Relative to VSS ....................................... -1V to +3.6V
I/O Pins Voltage
Relative to VSS ......................... -0.5V to VDDQ +0.5V
Operating Temperature, TA (ambient) .. 0°C to +70°C
Storage Temperature (plastic) ........... -55°C to +150°C
Power Dissipation ................................................... 1W
Short Circuit Output Current ............................ 50mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1–5, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)
PARAMETER/CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
MIN
MAX
UNITS NOTES
VDD
2.3
2.7
V
36, 41
VDDQ
2.3
2.7
V
36, 41,
44
V
6, 44
I/O Reference Voltage
VREF
I/O Termination Voltage (system)
VTT
VREF - 0.04
VREF + 0.04
V
7, 44
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.15
VDD + 0.3
V
28
Input Low (Logic 0) Voltage
VIL(DC)
-0.3
VREF - 0.15
V
28
II
-2
2
µA
IOZ
-5
5
µA
OUTPUT LEVELS: Full drive option - x4 , x8, x16
High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF,maximum VTT)
IOH
IOL
-16.8
16.8
–
–
mA
mA
OUTPUT LEVELS: Reduced drive option - x16 only
High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF,maximum VTT)
IOHR
IOLR
-9
9
–
–
mA 38, 39
mA
INPUT LEAKAGE CURRENT
Any input, 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
0.49 x VDDQ 0.51 x VDDQ
37, 39
AC INPUT OPERATING CONDITIONS
(Notes: 1–5, 14, 16; notes appear on pages 50–53) (0°C ≤ TA ≤ + 70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
VIH(AC)
VREF + 0.310
–
V
14, 28, 40
Input Low (Logic 0) Voltage
VIL(AC)
–
VREF - 0.310
V
14, 28, 40
I/O Reference Voltage
VREF(AC)
0.49 x VDDQ
0.51 x VDDQ
V
6
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
VDDQ (2.3V minimum)
1
VOH(MIN) (1.670V for SSTL2 termination)
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)
1.560V
VIHAC
1.400V
VIHDC
1.300V
1.275V
1.250V
1.225V
1.200V
VREF
VREF
VREF
VREF
1.100V
VILDC
0.940V
VINAC - Provides margin
between VOL (MAX) and VILAC
+AC Noise
+DC Error
-DC Error
-AC Noise
VILAC
Receiver
VOL (MAX) (0.83V2 for
SSTL2 termination)
NOTE: 1. VOH (MIN) with test load is 1.927V
2. VOL (MAX) with test load is 0.373V
3. Numbers in diagram reflect nomimal
values utilizing circuit below.
VSSQ
VTT
Transmitter
25Ω
25Ω
Reference
Point
Figure 27
Input Voltage Waveform
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
CLOCK INPUT OPERATING CONDITIONS
(Notes: 1–5, 15, 16, 30; notes appear on pages 50–53) (0°C ≤ TA ≤ + 70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Clock Input Mid-Point Voltage; CK and CK#
VMP(DC)
1.15
1.35
V
6, 9
Clock Input Voltage Level; CK and CK#
VIN(DC)
-0.3
VDDQ + 0.3
V
6
Clock Input Differential Voltage; CK and CK#
VID(DC)
0.36
VDDQ + 0.6
V
6, 8
Clock Input Differential Voltage; CK and CK#
VID(AC)
0.7
VDDQ + 0.6
V
8
Clock Input Crossing Point Voltage; CK and CK#
VIX(AC) 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2
V
9
2.80v
Maximum Clock Level
5
CK
X
1.45v
1.05v
3
1
VMP (DC)
1.25v
VIX (AC)
2
VID (DC)
4
VID (AC)
X
CK#
Minimum Clock Level
- 0.30v
NOTE:
5
1. This provides a minimum of 1.15v to a maximum of 1.35v, and is always half of VDDQ.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC)
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than VDDQ + 0.3v or more negative than Vss - 0.3v.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
Figure 28 – SSTL_2 Clock Input
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
CAPACITANCE (x4, x8)
(Note: 13; notes appear on pages 50–53)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Delta Input/Output Capacitance: DQs, DQS, DM
DCIO
–
0.50
pF
24
Delta Input Capacitance: Command and Address
DCI 1
–
0.50
pF
29
Delta Input Capacitance: CK, CK#
29
DCI 2
–
0.25
pF
Input/Output Capacitance: DQs, DQS, DM
CIO
4.0
5.0
pF
Input Capacitance: Command and Address
CI1
2.0
3.0
pF
Input Capacitance: CK, CK#
CI2
2.0
3.0
pF
Input Capacitance: CKE
CI3
2.0
3.0
pF
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
MAX
SYMBOL -75/-75Z
-8
PARAMETER/CONDITION
tRC
tRC
UNITS
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
=
(MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cyle; Address and control inputs changing once every two clock cycles;
IDD0
105
100
mA
22, 48
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
IDD1
120
110
mA
22,48
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDD2P
3
3
mA
23, 32, 50
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
45
35
mA
51
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
18
18
mA
23, 32, 50
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
IDD3N
45
35
mA
47
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R
110
90
mA
22, 48
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
110
90
mA
22
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
tRC = 15.625µs
IDD5
IDD6
220
5
205
5
mA
mA
22, 50
27, 50
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
Low power (L)
IDD7
IDD7
2
1
3
1
mA
mA
11
11
IDD8
325
260
mA
22,49
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
CAPACITANCE (x16)
(Note: 13; notes appear on pages 50–53)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM
DCIOL
–
0.50
pF
24
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
DCIOU
–
0.50
pF
24
Delta Input Capacitance: Command and Address
DCI 1
–
0.50
pF
29
Delta Input Capacitance: CK, CK#
29
DCI 2
–
0.25
pF
Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM
CIO
4.0
5.0
pF
Input Capacitance: Command and Address
CI1
2.0
3.0
pF
Input Capacitance: CK, CK#
CI2
2.0
3.0
pF
Input Capacitance: CKE
CI3
2.0
3.0
pF
IDD SPECIFICATIONS AND CONDITIONS (x16)
(Notes: 1–5, 10, 12, 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
MAX
SYMBOL -75/-75Z
-8
PARAMETER/CONDITION
tRC
tRC
OPERATING CURRENT: One bank; Active-Precharge;
=
(MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
cyle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
tRC = tRFC (MIN)
AUTO REFRESH CURRENT
tRC = 15.625µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
Low power (L)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge, tRC =tRC (MIN); tCK =tCK (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
47
UNITS
NOTES
IDD0
TBD
TBD
mA
22, 48
IDD1
TBD
TBD
mA
22,48
IDD2P
3
3
mA
23, 32, 50
IDD2F
TBD
TBD
mA
51
IDD3P
TBD
TBD
mA
23, 32, 50
IDD3N
TBD
TBD
mA
47
IDD4R
TBD
TBD
mA
22, 48
IDD4W
TBD
TBD
mA
22
IDD5
IDD6
IDD7
IDD7
IDD8
250
5
2
1
TBD
220
5
3
1
TBD
mA
mA
mA
mA
mA
22, 50
27, 50
11
11
22,49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1–5, 14–17, 33; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
AC CHARACTERISTICS
PARAMETER
-75Z
MAX
MIN
-75
MAX
+0.75
-0.75
-0.45
+0.55
tCL
0.45
0.55
CL = 2.5 tCK (2.5) 7.5
13
tCK (2)
CL = 2
7.5
13
tDH
DQ and DM input hold time relative to DQS
0.5
tDS
DQ and DM input setup time relative to DQS
0.5
tDIPW
DQ and DM input pulse width (for each input)
1.75
t
Access window of DQS from CK/CK#
DQSCK -0.75
+0.75
tDQSH
DQS input high pulse width
0.35
tDQSL
DQS input low pulse width
0.35
t
DQS-DQ skew, DQS to last DQ valid, per group, per access DQSQ
0.5
tDQSS
Write command to first DQS latching transition
0.75
1.25
tDSS
DQS falling edge to CK rising - setup time
0.2
t
DQS falling edge from CK rising - hold time
DSH
0.2
tHP
tCH,tCL
Half clock period
tHZ
Data-out high-impedance window from CK/CK#
+0.75
tLZ
Data-out low-impedance window from CK/CK#
-0.75
tIH
Address and control input hold time (fast slew rate)
.90
F
t IS
Address and control input setup time (fast slew rate)
.90
F
tIH
Address and control input hold time (slow slew rate)
1
S
t IS
Address and control input setup time (slow slew rate)
1
S
tMRD
LOAD MODE REGISTER command cycle time
15
tQH
tHP -tQHS
DQ-DQS hold, DQS to first DQ to go non-valid, per access
0.45
0.45
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
SYMBOL MIN
Access window of DQs from CK/CK#
tAC
CK high-level width
CK low-level width
Clock cycle time
tCH
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
-0.75
tQHS
tRAS
40
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFI
tVTD
tXSNR
tXSRD
0.75
0.2
0.2
tCH,tCL
-8
MIN
MAX
+0.75
-0.8
+0.8
ns
0.55
0.55
13
13
0.45
0.45
8
10
0.6
0.6
2
-0.8
0.35
0.35
0.55
0.55
13
13
tCK
+0.75
0.5
1.25
0.75
0.2
0.2
tCH,tCL
+0.75
-0.75
.90
.90
1
1
15
tHP -tQHS
0.75
120,000
40
0.75
120,000
+0.8
0.6
1.25
+0.8
-0.8
1.1
1.1
1.1
1.1
16
tHP-tQHS
40
1
120,000
tRAS(MIN) - (burst length
t
* CK/2)
65
75
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
140.6
15.6
0
75
200
48
65
75
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
140.6
15.6
0
75
200
70
80
20
20
0.9
1.1
0.4
0.6
15
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
140.6
15.6
0
80
200
UNITS
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
ns
ns
tCK
NOTES
30
30
45, 52
45, 52
26, 31
26, 31
31
25, 26
34
18, 42
18, 43
14
14
14
14
25, 26
35
46
50
42
20, 21
19
25
23
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
SLEW RATE DERATING VALUES
(Note: 14; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
ADDRESS / COMMAND
SPEED
-75/-75Z
-75/-75Z
-75/-75Z
-75/-75Z
-8
-8
-8
-8
SLEW RATE
0.500V / ns
0.400V / ns
0.300V / ns
0.200V / ns
0.500V / ns
0.400V / ns
0.300V / ns
0.200V / ns
t IS
t IH
1
1.05
1.10
1.15
1.1
1.15
1.20
1.25
1
1
1
1
1.1
1.1
1.1
1.1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
14
14
14
14
14
14
14
14
SLEW RATE DERATING VALUES
(Note: 31; notes appear on pages 50–53) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
DQ, DQS, DM
SPEED
-75/-75Z
-75/-75Z
-75/-75Z
-75/-75Z
-8
-8
-8
-8
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
SLEW RATE
0.500V / ns
0.400V / ns
0.300V / ns
0.200V / ns
0.500V / ns
0.400V / ns
0.300V / ns
0.200V / ns
t DS
t DH
0.50
0.55
0.60
0.65
0.60
0.65
0.70
0.75
0.50
0.55
0.60
0.65
0.60
0.65
0.70
0.75
49
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
31
31
31
31
31
31
31
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTES
1.
2.
3.
12. IDD specifications are tested after the device is
properly initialized, and is averaged at the
defined cycle rate.
13. This parameter is sampled. VDD = +2.5V ±0.2V,
VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz,
TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to
peak) = 0.2V. DM input is grouped with I/O
pins, reflecting the fact that they are matched in
loading.
14. Command/Address input slew rate = 0.5V/ns.
For -75 with slew rates 1V/ns and faster, tIS and
tIH are reduced to 900ps. If the slew rate is less
than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns. tIH has 0ps added,
that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing
referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for
signals other than CK/CK# is VREF.
16. Inputs are not recognized as valid until VREF
stabilizes. Exception: during the period before
VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as
LOW.
17. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
VTT.
18. tHZ and tLZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific
voltage level, but specify when the device output
is no longer driving (HZ) or begins driving (LZ).
19. The maximum limit for this parameter is not a
device limit. The device will operate with a
greater value for this parameter, but system
performance (bus turnaround) will degrade
accordingly.
20. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously
in progress on the bus. If a previous WRITE was
in progress, DQS could be HIGH during this
time, depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest
multiple of tCK that meets the maximum
absolute value for tRAS.
All voltages referenced to VSS.
Tests for AC timing, IDD, and electrical AC and
DC characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
Outputs measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
4.
AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter
specifications are guaranteed for the specified
AC input levels under normal use conditions.
The minimum slew rate for the input signals
used to test the device is 1V/ns in the range
between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC
level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed ±2
percent of the DC value. Thus, from VDDQ/2,
VREF is allowed ±25mV for DC error and an
additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass
capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between
the input level on CK and the input level on CK#.
9. The value of VIX and VMP are expected to equal
VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
10. IDD is dependent on output loading and cycle
rates. Specified values are obtained with
minimum cycle time at CL = 2 for -75Z and -8,
CL = 2.5 for -75 with the outputs open.
11. Enables on-chip refresh and address counters.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTES (continued)
27. This limit is actually a nominal value and does
not result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge
of the input must:
a) Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
to maintain at least the target DC level, VIL(DC)
or VIH(DC).
29. The Input capacitance per pin group will not
differ by more than this maximum amount for
any given device..
30. JEDEC specifies CK and CK# input slew rate must
be ≥ 1V/ns (2V/ns differentially).
31. DQ and DM input slew rates must not deviate
from DQS by more than 10%. If the DQ/DM/
DQS slew rate is less than 0.5V/ns, timing must
be derated: 50ps must be added to tDS and tDH
for each 100mv/ns reduction in slew rate. If slew
rate exceeds 4V/ns, functionality is uncertain.
23. The refresh period 64ms. This equates to an
average refresh rate of 15.625µs. However, an
AUTO REFRESH command must be asserted at
least once every 140.6µs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/
group will not differ by more than this maximum amount for any given device.
25. The valid data window is derived by achieving
other specifications - tHP (tCK/2), tDQSQ, and
tQH (tQH = tHP - tQHS). The data valid window
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is
uncertain when operating beyond a 45/55 ratio.
The data valid window derating curves are
provided below for duty cycles ranging between
50/50 and 45/55.
26. Referenced to each output group: x4 = DQS with
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 =
LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15.
DERATING DATA VALID WINDOW
(tQH - tDQSQ)
3.8
3.750
3.6
3.400
3.4
3.700
3.650
3.600
3.550
3.500
3.350
3.450
3.300
3.400
3.250
3.200
ns
3.0
3.350
3.150
3.2
3.100
t
——
u -75 @ CK = 10ns
3.300
3.250
3.050
3.000
#
—— -8 @ tCK = 10ns
2.950
2.900
——
n -75 @ tCK = 7.5ns
2.8
2.6
——
l -8 @ tCK = 8ns
2.500
2.463
2.425
2.388
2.4
2.350
2.313
2.275
2.238
2.200
2.2
2.163
2.125
2.0
1.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTES (continued)
32. VDD must not vary more than 4% if CKE is not
active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
34. tHP min is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS(MIN) can be
satisfied prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the
clock and not more than +400mV or 2.9 volts,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either
-300mV or 2.2 volts, whichever is more positive.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure A.
b) The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure A.
c) The full variation in driver pull-up current
from minimum to maximum process,
temperature and voltage will lie within the
outer bounding lines of the V-I curve of
Figure B.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure B.
e) The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0 Volt,
and at the same voltage and temperature.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages
from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure C.
b) The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure C.
c) The full variation in driver pull-up current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure D.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figure D.
e) The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between .71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0 V,
and at the same voltage.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages
from 0.1V to 1.0 V.
Figure A
Pull-Down Characteristics
Figure B
Pull-Up Characteristics
160
0
-20
140
-40
120
-60
IOUT (mA)
IOUT (mA)
100
80
60
-80
-100
-120
-140
40
-160
20
-180
0
-200
0.0
0.5
1.0
1.5
2.0
2.5
0.0
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
VOUT (V)
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NOTES (continued)
39. The voltage levels used are derived from a
minimum VDD level and the referenced test load.
In practice, the voltage levels obtained from a
properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a
pulse width ≤ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(MIN) = -1.5V for a pulse width ≤
3ns and the pulse width can not be greater than
1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. This maximum value is derived from the
referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for tHZ(MAX) and the
last DVW. tHZ(MAX) will prevail over
tDQSCK(MAX) + tRPST(MAX) condition.
tLZ(MIN) will prevail over tDQSCK(MIN) +
tRPRE(MAX) condition.
4 3 . For slew rates greater than 1V/ns the (LZ)
transition will start about 310ps earlier.
4 4 . During initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power
up, even if VDD/VDDQ are 0 volts, provided a
minimum of 42 ohms of series resistance is used
between the VTT supply and the input pin.
45. The current Micron part operates below the
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
46. tRAP ≥ tRCD.
47. For the -75 and -75Z, IDD3N is specified to be
35mA at 100 MHz.
48. Random addressing changing 50% of data
changing at every transfer.
49. Random addressing changing 100% of data
changing at every transfer.
50. CKE must be active (high) during the entire time
a refresh command is executed. That is, from
the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock
edge, until tREF later.
51. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q
is similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
-20
-40
IOUT (mA)
Figure C
Pull-Down Characteristics
80
70
-60
-80
60
50
IOUT (mA)
Figure D
Pull-Up Characteristics
0
-100
40
-120
0.0
30
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
NORMAL OUTPUT DRIVE CHARACTERISTICS
PULL-DOWN CURRENT (mA)
PULL-UP CURRENT (mA)
VOLTAGE NOMINAL NOMINAL
NOMINAL NOMINAL
(V)
LOW
HIGH
MINIMUM MAXIMUM
LOW
HIGH
MINIMUM MAXIMUM
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10
0.2
0.3
0.4
0.5
0.6
12.2
18.1
24.1
29.8
34.6
13.5
20.1
26.6
33.0
39.1
9.2
13.8
18.4
23.0
27.7
18.2
26.0
33.9
41.8
49.4
-12.2
-18.1
-24.0
-29.8
-34.3
-14.5
-21.2
-27.7
-34.1
-40.5
-9.2
-13.8
-18.4
-23.0
-27.7
-20
-29.8
-38.8
-46.8
-54.4
0.7
0.8
0.9
1.0
39.4
43.7
47.5
51.3
44.2
49.8
55.2
60.3
32.2
36.8
39.6
42.6
56.8
63.2
69.9
76.3
-38.1
-41.1
-43.8
-46.0
-46.9
-53.1
-59.4
-65.5
-32.2
-36.0
-38.2
-38.7
-61.8
-69.5
-77.3
-85.2
1.1
1.2
54.1
56.2
65.2
69.9
44.8
46.2
82.5
88.3
-47.8
-49.2
-71.6
-77.6
-39.0
-39.2
-93.0
-100.6
1.3
1.4
1.5
57.9
59.3
60.1
74.2
78.4
82.3
47.1
47.4
47.7
93.8
99.1
103.8
-50.0
-50.5
-50.7
-83.6
-89.7
-95.5
-39.4
-39.6
-39.9
-108.1
-115.5
-123.0
1.6
1.7
60.5
61.0
85.9
89.1
48.0
48.4
108.4
112.1
-51.0
-51.1
-101.3
-107.1
-40.1
-40.2
-130.4
-136.7
1.8
1.9
2.0
61.5
62.0
62.5
92.2
95.3
97.2
48.9
49.1
49.4
115.9
119.6
123.3
-51.3
-51.5
-51.6
-112.4
-118.7
-124.0
-40.3
-40.4
-40.5
-144.2
-150.5
-156.9
2.1
2.2
62.8
63.3
99.1
100.9
49.6
49.8
126.5
129.5
-51.8
-52.0
-129.3
-134.6
-40.6
-40.7
-163.2
-169.6
2.3
2.4
2.5
2.6
63.8
64.1
64.6
64.8
101.9
102.8
103.8
104.6
49.9
50.0
50.2
50.4
132.4
135.0
137.3
139.2
-52.2
-52.3
-52.5
-52.7
-139.9
-145.2
-150.5
-155.3
-40.8
-40.9
-41.0
-41.1
-176.0
-181.3
-187.6
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
REDUCED OUTPUT DRIVE CHARACTERISTICS
PULL-DOWN CURRENT (mA)
PULL-UP CURRENT (mA)
VOLTAGE NOMINAL NOMINAL
NOMINAL NOMINAL
(V)
LOW
HIGH
MINIMUM MAXIMUM
LOW
HIGH
MINIMUM MAXIMUM
0.1
3.4
3.8
2.6
5.0
-3.5
-4.3
-2.6
-5.0
0.2
0.3
0.4
0.5
0.6
6.9
10.3
13.6
16.9
19.9
7.6
11.4
15.1
18.7
22.1
5.2
7.8
10.4
13.0
15.7
9.9
14.6
19.2
23.6
28.0
-6.9
-10.3
-13.6
-16.9
-19.4
-7.8
-12.0
-15.7
-19.3
-22.9
-5.2
-7.8
-10.4
-13.0
-15.7
-9.9
-14.6
-19.2
-23.6
-28.0
0.7
0.8
0.9
1.0
22.3
24.7
26.9
29.0
25.0
28.2
31.3
34.1
18.2
20.8
22.4
24.1
32.2
35.8
39.5
43.2
-21.5
-23.3
-24.8
-26.0
-26.5
-30.1
-33.6
-37.1
-18.2
-20.4
-21.6
-21.9
-32.2
-35.8
-39.5
-43.2
1.1
1.2
30.6
31.8
36.9
39.5
25.4
26.2
46.7
50.0
-27.1
-27.8
-40.3
-43.1
-22.1
-22.2
-46.7
-50.0
1.3
1.4
1.5
32.8
33.5
34.0
42.0
44.4
46.6
26.6
26.8
27.0
53.1
56.1
58.7
-28.3
-28.6
-28.7
-45.8
-48.4
-50.7
-22.3
-22.4
-22.6
-53.1
-56.1
-58.7
1.6
1.7
34.3
34.5
48.6
50.5
27.2
27.4
61.4
63.5
-28.9
-28.9
-52.9
-55.0
-22.7
-22.7
-61.4
-63.5
1.8
1.9
2.0
34.8
35.1
35.4
52.2
53.9
55.0
27.7
27.8
28.0
65.6
67.7
69.8
-29.0
-29.2
-29.2
-56.8
-58.7
-60.0
-22.8
-22.9
-22.9
-65.6
-67.7
-69.8
2.1
2.2
35.6
35.8
56.1
57.1
28.1
28.2
71.6
73.3
-29.3
-29.5
-61.2
-62.4
-23.0
-23.0
-71.6
-73.3
2.3
2.4
2.5
2.6
36.1
36.3
36.5
36.7
57.7
58.2
58.7
59.2
28.3
28.3
28.4
28.5
74.9
76.4
77.7
78.8
-29.5
-29.6
-29.7
-29.8
-63.1
-63.8
-64.4
-65.1
-23.1
-23.2
-23.2
-23.3
-74.9
-76.4
-77.7
-78.8
2.7
36.8
59.6
28.6
79.7
-29.9
-65.8
-23.3
-79.7
NOTE: The above characteristics are specified under best, worst, and nominal process variation/conditions.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP5
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
tHP5
tHP5
tDQSQ3
tDQSQ3
DQS1
QFC#
DQ (Last data valid)
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)
tQH4
tQH4
DQ (Last data valid)
T2
T2n
T3
T3n
DQ (First data no longer valid)
T2
T2n
T3
T3n
All DQs and DQS, collectively6
T2
T2n
T3
T3n
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
Earliest signal transition
Latest signal transition
NOTE: 1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,”
at T3 is a “nominal DQS,” and at T3n is a "late DQS"
2. For a x4, only two DQs apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
4. tQH is derived from tHP : tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
Figure 29 – x4, x8
Data Output Timing – tDQSQ, tQH and Data Valid Window
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
CK#
CK
T1
T2
tHP5
tHP5
T2n
T3
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
T3n
tHP5
T4
tHP5
tDQSQ3
tDQSQ3
LDQS1
tQH4
Lower Byte
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
tQH4
valid)2
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ0 - DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
Data Valid
window
Data Valid
window
Data Valid
window
DQ (Last data
Data Valid
window
tDQSQ3
tDQSQ3
tDQSQ3
tDQSQ3
UDQS1
tQH4
tQH4
tQH4
valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
DQ8 - DQ15 and UDQS, collectively6
T2
T2n
Data Valid
window
Data Valid
window
DQ (Last data
NOTE: 1. DQs transitioning after DQS transition define tDQSQ
window. LDQS defines the lower byte and
UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not
cumulative over time and begins with DQS transition
and ends with the last valid transition of DQs .
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH4
T3
T3
T3
T3n
T3n
T3n
Data Valid Data Valid
window
window
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition
collectively when a bank is active.
6. The data valid window is derived for each
DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
Figure 29A - x16
Data Output Timing – tDQSQ, tQH and Data Valid Window
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
T07
T1
T2
T3
T2n
T3n
T4
T4n
T5
T5n
T6
CK#
CK
tDQSCK1(MAX) tHZ(MAX)
tDQSCK1(MIN)
tDQSCK1(MAX)
tDQSCK1(MIN)
tLZ(MIN)
tRPST
tRPRE
DQS, or LDQS/UDQS2
DQ (Last data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
DQ (First data valid)
T2
T2n
T3
T3n
T4
T4n
T5
T5n
All DQs collectively3
T2
T2n
T3
T3n
T4
T4n
T5
T5n
tLZ(MIN)
NOTE: 1.
2.
3.
4.
5.
6.
7.
tAC4(MIN)
tAC4(MAX)
tHZ(MAX)
tDQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.
DQs transitioning after DQS transition define tDQSQ window.
All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.
tAC is the DQ output window relative to CK, and is the“long term” component of DQ skew.
tLZ(MIN) and tAC(MIN) are the first valid signal transition.
tHZ(MAX ,and tAC(MAX) are the latest valid signal transition.
READ command with CL = 2 issued at T0.
Figure 30
Data Output Timing – tAC and tDQSCK
T0
T1
T1n
T2
T2n
T3
CK#
CK
tDQSS
tDSH1 tDSS2
tDSH1 tDSS2
DQS
tWPRES
tWPRE
tDQSL tDQSH tWPST
DI
b
DQ
DM
tDS
tDH
DON’T CARE
NOTE: 1.
2.
TRANSITIONING DATA
tDSH(MIN) generally occurs during tDQSS(MIN).
tDSS(MIN) generally occurs during tDQSS(MAX).
Figure 31
Data Input Timing
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
INITIALIZE AND LOAD MODE REGISTERS
((
))
VDD
((
))
VDDQ
tVTD1
VTT1
((
))
VREF
((
))
T1
T0
T2
CK#
CK
tCH
LVCMOS
LOW LEVEL
((
))
tIS
66
6
COMMAND
Tb0
Tc0
Td0
Te0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
tIS
CKE
tCL
Ta0
((
))
((
))
tIH
NOP
((
))
((
))
PRE
tCK
DM
((
))
((
))
A0-A9,
A11
((
))
((
))
A10
tIS
tIH
tIS
((
))
((
))
AR
((
))
((
))
((
))
((
))
AR
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ACT5
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
CODE
( ( ALL BANKS
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RA
((
))
((
))
BA0 = L,
BA1 = L
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA
tIH
CODE
tIS
((
))
((
))
PRE
tIH
CODE
((
))
((
))
BA0, BA1
((
))
((
))
LMR
((
))
((
))
tIS
ALL BANKS
((
))
((
))
LMR
tIS
tIH
BA0 = H,
BA1 = L
tIH
DQS
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
T = 200µs
tRP
tMRD
Load Extended
Mode Register
Power-up: VDD and CK stable
tMRD
tRP
tRFC
tRFC5
200 cycles of CK3
Load Mode
Register2
NOTE:
DON’T CARE
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.
VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if
VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin.
2. Reset the DLL with A8 = H.
3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row
Address, BA = Bank Address
TIMING PARAMETERS
-75Z
-75
-8
-75Z
SYMBOL
tCH
MIN
0.45
MAX
0.55
MIN
0.45
MAX
0.55
MIN
0.45
MAX
0.55
UNITS
tCK
tCL
0.45
7.5
0.55
13
0.45
7.5
0.55
13
0.45
8
0.55
13
tCK
ns
tRFC
7.5
1
13
10
1
13
10
1.1
13
ns
ns
tRP
tCK (2.5)
tCK (2)
tIH
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
SYMBOL
tIS
tMRD
tVTD
59
MIN
1
MAX
-75
MIN
1
MAX
-8
MIN
1.1
MAX
UNITS
ns
15
75
15
75
16
80
ns
ns
20
0
20
0
20
0
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
POWER-DOWN MODE
T0
T1
T2
CK#
CK
tCK
tIS
tCH
tCL
tIS
ADDR
Ta2
tIS
((
))
tIH
VALID1
COMMAND
Ta1
tIS
tIH
CKE
tIS
Ta0
((
))
((
))
((
))
((
))
NOP
tIH
NOP
VALID
((
))
((
))
VALID
DQS
((
))
((
))
DQ
((
))
((
))
DM
((
))
((
))
VALID
tREFC
Enter 2
Power-Down
Mode
Exit
Power-Down
Mode
DON’T CARE
NOTE: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if
at least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
-75Z
MIN
MAX
0.45
0.55
MIN
0.45
0.45
7.5
0.45
7.5
0.55
13
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
-75
MAX
0.55
0.55
13
-8
-75Z
MIN
0.45
MAX
0.55
UNITS
tCK
0.45
8
0.55
13
tCK
ns
SYMBOL
-8
MAX
MIN
MAX
MIN
MAX
UNITS
13
10
1
13
10
1.1
13
tIH
7.5
1
ns
ns
tIS
1
tCK (2)
60
-75
MIN
1
1.1
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
AUTO REFRESH MODE
T0
T2
T1
T4
T3
CK#
CK
tIS
tCK
tIH
tCH
CKE
tIH
NOP 2
NOP 2
PRE
Ta1
((
))
((
))
VALID
tIS
COMMAND1
tCL
Ta0
((
))
((
))
NOP 2
AR
((
))
((
))
NOP 2
AR 5
Tb0
((
))
((
))
((
))
((
))
VALID
((
))
((
))
NOP2
Tb1
Tb2
NOP2
ACT
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA
DQS4
((
))
((
))
((
))
((
))
DQ4
((
))
((
))
((
))
((
))
DM4
((
))
((
))
((
))
((
))
A0-A9, A111
ALL BANKS
A101
ONE BANK
tIS
BA0, BA11
tIH
Bank(s) 3
tRP
tRFC 5
tRFC
DON’T CARE
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active (high)
during clock positive transitions.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks).
4. QFC, DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
-75Z
MIN
MAX
MIN
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
7.5
7.5
13
10
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
-75
MAX
-8
SYMBOL
-75Z
MIN
MAX
-8
MAX
UNITS
0.55
0.55
13
0.45
0.45
8
0.55
0.55
13
tCK
tIH
1
1
1.1
ns
tCK
tIS
ns
tRFC
1
75
1
75
1.1
80
ns
ns
13
10
13
ns
tRP
20
20
20
ns
61
MIN
-75
MAX
MIN
MIN
MAX
UNITS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
SELF REFRESH MODE
T0
T1
CK1
tCH
tIS
tCL
t IS
CKE1
COMMAND 4
Ta1
tCK
tIS
tIH
tIS
Ta01
((
))
((
))
CK#
NOP
((
))
((
))
AR
Tb0
((
))
((
))
((
))
tIH
((
))
((
))
NOP
((
))
((
))
ADDR
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
VALID
tIS
tIH
VALID
tXSNR/
tXSRD 3
tRP 2
Enter Self Refresh Mode
Exit Self Refresh Mode
DON’T CARE
NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within
specifications by Ta0.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK)
is required before a READ command can be applied.
4. AR = AUTO REFRESH command.
TIMING PARAMETERS
SYMBOL
-75Z
MIN
MAX
tCH
0.45
tCL
tCK (2.5)
tCK (2)
tIH
7.5
7.5
1
MIN
-75
MAX
-8
MIN
MAX
UNITS
SYMBOL
0.55
0.45
0.45
0.550.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tIS
tCK
tRP
13
13
7.5
10
1
13
13
8
10
1.1
13
13
ns
ns
ns
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
62
-75Z
MIN
MAX
MIN
-75
MAX
-8
MIN
MAX
UNITS
tXSNR
1
20
75
1
20
75
1.1
20
80
ns
ns
ns
tXSRD
200
200
200
tCK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
BANK READ – WITHOUT AUTO PRECHARGE
CK#
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP6
ACT
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
RA
x8: A11
x16: A9, A11
RA
READ2
PRE7
NOP6
NOP6
tIH
Col n
RA
RA
tIS
tIH
ALL BANKS
A10
RA
RA
3
ONE BANK
tIS
BA0, BA1
tIH
Bank x
Bank x4
Bank x
tRCD
Bank x
CL = 2
tRP
tRAS7
tRC
DM
tDQSCK(MIN)
Case 1: tAC(MIN) and tDQSCK(MIN)
tRPST
tRPRE
DQS
tLZ(MIN)
DO
n
DQ1
tLZ(MIN)
tAC(MIN)
tDQSCK(MAX)
Case 2: tAC(MAX) and tDQSCK(MAX)
tRPST
tRPRE
DQS
DO
n
DQ1
tAC(MAX)
NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
8. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
63
tHZ(MAX)
TRANSITIONING DATA
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
BANK READ – WITH AUTO PRECHARGE
T1
T0
CK#
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP5
ACT
CK
tIS
tCK
tIH
tCH
tCL
CKE
tIS
COMMAND4
tIH
NOP5
NOP5
ACT
tIS
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
RA
x8: A11
x16: A9, A11
RA
A10
RA
NOP5
NOP5
READ2,6
NOP5
tIH
Col n
RA
RA
3
IS
BA0, BA1
tIS
RA
tIH
IH
Bank x
Bank x
tRAP6
Bank x
CL = 2
tRAS6
tRP
tRC
DM
Case 1: tAC(MIN) and tDQSCK(MIN)
tDQSCK(MIN)
tRPST
tRPRE
DQS
tLZ(MIN)
DO
n
DQ1
tLZ(MIN)
Case 2: tAC(MAX) and tDQSCK(MAX)
tAC(MIN)
tDQSCK(MAX)
tRPST
tRPRE
DQS
DO
n
DQ1
tAC(MAX)
NOTE: 1. DO n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if tRAP minimum is met, tRAP >
_ tRCD.
7. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
64
tHZ(MAX)
TRANSITIONING DATA
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
BANK WRITE – WITHOUT AUTO PRECHARGE
T1
T0
CK#
T2
CK
T3
tCK
tIS
tIH
tIS
tIH
tCH
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
tIH
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
RA
x8: A11
x16: A9, A11
RA
Col n
tIS
A10
RA
tIS
BA0, BA1
NOP6
NOP6
WRITE2
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS(NOM)
tDSH7
tDSS8
tDSH7
tDSS8
tDQSL
tDQSH tWPST
DQS
tWPRES tWPRE
DI
b
DQ1
DM
tDS
tDH
NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.
8. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA
DON’T CARE
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDQSH
tDQSL
tDQSS
tDSS
-75Z
MIN
MAX
MIN
0.45
0.45
0.55
0.55
0.45
0.45
7.5
7.5
0.5
13
13
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
-75
MAX
MAX
UNITS
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tDSH
tCK
tIH
13
13
8
10
0.6
13
13
ns
ns
ns
tIS
0.5
0.35
1.2
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
0.35
0.75
0.2
-8
MIN
0.6
0.35
1.25
0.35
0.75
0.2
1.25
SYMBOL
tRAS
tRCD
ns
tCK
tRP
tCK
tWPRES
tCK
tWPST
tCK
tWR
tWPRE
65
-75Z
MIN
MAX
MIN
-75
MAX
-8
MIN
0.2
1
0.2
1
0.2
1.1
1
45
20
1
45
20
1.1
50
20
120,000
20
0.25
0
0.4
15
120,000
20
0.25
0.6
0
0.4
15
MAX
tCK
ns
120,000
20
0.25
0.6
0
0.4
15
UNITS
ns
ns
ns
ns
tCK
ns
0.6
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
BANK WRITE – WITH AUTO PRECHARGE
T1
T0
CK#
T2
CK
tIS
tIH
tIS
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
NOP5
NOP5
T8
tCL
CKE
COMMAND4
NOP5
NOP5
ACT
tIS
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
RA
x8: A11
x16: A9, A11
RA
NOP5
WRITE2
NOP5
NOP5
tIH
Col n
3
A10
RA
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS(NOM)
tDSH6
tDSS7
tDSH6
tDSS7
tDQSL
tDQSH tWPST
DQS
tWPRES tWPRE
DI
b
DQ1
DM
tDS
tDH
NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.
7. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA
DON’T CARE
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDQSH
tDQSL
tDQSS
tDSS
-75Z
MIN
MAX
MIN
0.45
0.45
0.55
0.55
0.45
0.45
7.5
7.5
0.5
13
13
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
-75
MAX
MAX
UNITS
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tDSH
tCK
tIH
13
13
8
10
0.6
13
13
ns
ns
ns
tIS
0.5
0.35
1.25
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
0.35
0.75
0.2
-8
MIN
0.6
0.35
1.25
0.35
0.75
0.2
1.25
SYMBOL
tRAS
tRCD
ns
tCK
tRP
tCK
tWPRES
tCK
tWPST
tCK
tWR
tWPRE
66
-75Z
MIN
MAX
MIN
-75
MAX
-8
MIN
0.2
1
0.2
1
0.2
1.2
1
45
20
1
45
20
1.2
50
20
120,000
20
0.25
0
0.4
15
120,000
20
0.25
0.6
0
0.4
15
MAX
tCK
ns
120,000
20
0.25
0.6
0
0.4
15
UNITS
ns
ns
ns
ns
tCK
ns
0.6
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
WRITE – DM OPERATION
T1
T0
CK#
T2
CK
tIS
tIH
tIS
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
tCL
CKE
COMMAND5
NOP6
tIS
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
RA
x8: A11
x16: A9, A11
RA
WRITE2
NOP6
ACT
tIH
Col n
tIS
A10
RA
tIS
BA0, BA1
NOP6
NOP6
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS(NOM)
tDSH7
tDSS8
tDSH7
tDSS8
tDQSL
tDQSH tWPST
DQS
tWPRES tWPRE
DI
b
DQ1
DM
tDS
tDH
NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.
8. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA
DON’T CARE
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDQSH
tDQSL
tDQSS
tDSS
-75Z
MIN
MAX
MIN
0.45
0.45
0.55
0.55
0.45
0.45
7.5
7.5
0.5
13
13
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
-75
MAX
MAX
UNITS
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tDSH
tCK
tIH
13
13
8
10
0.6
13
13
ns
ns
ns
tIS
0.5
0.35
1.25
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
0.35
0.75
0.2
-8
MIN
0.6
0.35
1.25
0.35
0.75
0.2
1.25
SYMBOL
tRAS
tRCD
ns
tCK
tRP
tCK
tWPRES
tCK
tWPST
tCK
tWR
tWPRE
67
-75Z
MIN
MAX
MIN
-75
MAX
-8
MIN
0.2
1
0.2
1
0.2
1.1
1
45
20
1
45
20
1.1
50
20
120,000
20
0.25
0
0.4
15
120,000
20
0.25
0.6
0
0.4
15
MAX
tCK
ns
120,000
20
0.25
0.6
0
0.4
15
UNITS
ns
ns
ns
ns
tCK
ns
0.6
tCK
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
66-PIN PLASTIC TSOP (400 mil)
SEE DETAIL A
22.22 ± 0.08
0.71
0.65 TYP
0.10 (2X)
0.32 ± .075 TYP
11.76 ±0.10
10.16 ±0.08
+0.03
0.15 -0.02
PIN #1 ID
GAGE PLANE
0.10
0.25
+0.10
-0.05
0.10
0.80 TYP
1.20 MAX
0.50 ±0.10
DETAIL A
NOTE:
1. All dimensions in millimeters MAX or typical here noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
68
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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