Austin MT5C1001EC-35/883C 1m x 1 sram sram memory array Datasheet

SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
1M x 1 SRAM
PIN ASSIGNMENT
(Top View)
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
Q
WE\
Vss
FEATURES
•
•
•
•
•
•
•
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
28-Pin DIP (C)
(400 MIL)
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
Three-state output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
CE\
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
32-Pin Flat Pack (F)
OPTIONS
MARKING
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C
EC
F
DCJ
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
No. 109
No. 207
No. 303
No. 501
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (ISBC2) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1001
Rev. 2.1 06/05
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GENERAL DESCRIPTION
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
Vss
A6
D
A5
A3
A15
A14
Q
I/O CONTROL
ROW DECODER
A4
1,048,576-BIT
MEMORY ARRAY
512 rows x 2048
columns
CE\
A13
WE\
A8
POWER
DOWN
A7
COLUMN DECODER
A2 A1 A16 A0 A17 A18 A19 A10 A9 A12 A11
TRUTH TABLE
MODE
STANDBY
READ
WRITE
MT5C1001
Rev. 2.1 06/05
CE\
H
L
L
PIN ASSIGNMENTS
WE\
X
H
L
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
PIN
ASSIGNMENT
A0-A19
WE\
CE\
D
Q
NC
Address Inputs
Write Enable
Chip Enable
Data Input
Data Output
No Connection
VCC
+5V Power Supply
VSS
Ground
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
Voltage on Any Input Relative to Vss................................-.5V to +7V
Voltage on Vcc Supply Relative to Vss...............................-.5V to +7V
Voltage Applied to Q............................................................-.5V to +6V
Storage Temperature......................................................-65oC to +150oC
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................20mA
Lead Temperature (soldering 10 seconds)....................................+260oC
Junction Temperature..................................................................+175oC
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
CONDITIONS
SYMBOL
VIH
VIL
ILI
0V ≤ VIN ≤ VCC
Output(s) disabled
0V < VOUT < VCC
IOH = -4.0mA
IOL = 8.0mA
Output Leakage Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
MIN
2.2
-0.5
-5
MAX
VCC+0.5
0.8
5
UNITS
V
V
µA
-5
2.4
5
µA
0.4
V
V
NOTES
1
1, 2
1
1
CONDITIONS
SYM
-20
MAX
-25
-35
Power Supply
Current: Operating
CE\ < VIL; VCC = MAX
f = MAX = 1/tRC (MIN)
Output Open
Icc
125
120
115
110
mA
Power Supply
Current: Standby
CE\ > VIH; VCC = MAX
f = MAX = 1/tRC (MIN)
Output Open
ISBT1
50
45
40
35
mA
ISBT2
25
25
25
25
mA
ISBC2
10
10
10
10
mA
ISBC2
5
5
5
5
mA
PARAMETER
-45
UNITS NOTES
3
CE\ > VIH; All Other Inputs
< VIH or > VIH, VCC = MAX
f = 0 Hz
CE\ > VCC -0.2V; VCC = MAX
VIL < VSS +0.2V
VIH > VCC -0.2V; f = 0 Hz
"L" Version Only
CAPACITANCE
PARAMETER
CONDITIONS
Input Capacitance (A3-A5, A15 -A17)
SYMBOL
MAXIMUM
UNITS
NOTES
CI
10
pF
4
Co
8
pF
4
CI
8
pF
4
o
Output Capactiance (Q)
TA = 25 C, f = 1MHz
VCC = 5V
Input Capacitance: (All Other Inputs)
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
tRC
20
25
35
45
ns
Address access time
tAA
20
25
35
45
ns
Chip Enable access time
tACE
20
25
35
45
ns
Output hold from address change
tOH
3
3
3
3
ns
Chip Enable to output in Low-Z
tLZCE
3
3
3
3
ns
4, 6, 7
Chip disable to output in High-Z
tHZCE
ns
4, 6, 7
ns
4
ns
4
8
10
15
15
Chip Enable to power-up time
tPU
Chip disable to power-down time
WRITE CYCLE
WRITE cycle time
tPD
tWC
20
25
35
45
ns
Chip Enable to end of write
tCW
15
16
20
25
ns
Address valid to end of write
tAW
15
16
20
25
ns
Address setup time
tAS
0
0
0
0
ns
Address hold from end of write
tAH
1
1
1
1
ns
WRITE pulse width
tWP
15
16
20
25
ns
Data setup time
tDS
8
10
13
15
ns
Data hold time
tDH
0
0
0
0
ns
Write disable to output in Low-Z
tLZWE
3
3
3
3
ns
7
Write Enable to output in High-Z
tHZWE
0
ns
4, 6, 7
MT5C1001
Rev. 2.1 06/05
0
0
20
9
0
25
0
10
0
35
0
13
45
0
13
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
AC TEST CONDITIONS
167Ω
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
Q
30pF
167Ω
VTH = 1.73V Q
Fig. 1 Output Load
Equivalent
4.
5.
6.
VTH = 1.73V
Fig. 2 Output Load
Equivalent
allowing for actual tester RC time constant.
At any given temperature and voltage condition,
tHZCE is less than tLZCE, and tHZWE is less than tLZWE and
tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
NOTES
1.
2.
3.
5pF
7.
All voltages referenced to VSS (GND).
-3V for pulse width < 20ns
ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
VCC for Retention Data
CONDITIONS
CE\ > (VCC - 0.2V)
and
VIN > (VCC - 0.2V)
or < 0.2V
Data Retention Current
SYMBOL
VDR
ICCDR
VCC = 2V
MIN
2
VCC = 3V
t
Chip Deselect to Data
Retention Time
Operation Recovery Time
MAX
-1.0
UNITS
V
mA
1.5
mA
0
CDR
NOTES
ns
4
ns
4, 11
-t
t
R
RC
LOW Vcc DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
t CDR
CE\
VIH
VIL
1234
123456789
123
123456789
123
1234
123456789
123
1234
123456789
123
1234
VDR > 2V
4.5V
tR
V DR
12345678
1234
123
12345678
1234
123
12345678
1234
123
12345678
1234
123
123
123
123
123 DON’T CARE
1234
1234
1234
1234UNDEFINED
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
READ CYCLE NO. 1 8, 9
ttRC
RC
ADDRESS
VALID
ttAA
AA
ttOH
OH
DQ
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 2
7, 8, 10
ttRC
RC
CE\
ttLZCE
LZCE
tACE
tACE
t
HZCE
tHZCE
DQ
DATA VALID
ttPU
PU
ttPD
PD
Icc
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
t
WC
tWC
ADDRESS
tAW
tAW
ttAS
AS
t
AH
tAH
tCW
tCW
CE\
t WP
tWP1
123456789012345678901
1
1
WE\ 123456789012345678901
1123456789012345678901234567890121234567890
1123456789012345678901234567890121234567890
t DH
tDH
ttDS
DS
D
DATA VAILD
Q
HIGH Z
WRITE CYCLE NO. 2 7, 12
(Write Enabled Controlled)
tWC
tWC
ADDRESS
tAW
tAW
12345678901234567
12
12
12345678901234567
12345678901234567
121
CE\
ttAS
AS
WE\
ttAH
AH
tCW
tCW
12345678901234567890123
1
1212345678901234567890123
112345678901234567890123
t WP
tWP1
123456789
123456789
123456789
tDS
1234567890123456
11234
1 tHZWE
1234567890123456
11234
1
11234
1
Q 1234567890123456
11234
1
1234567890123456
D
DATA VALID
HIGH-Z
t DH
tDH
12123456
1
tLZWE1234
1234
12123456
1
1234
12123456
1
1234
12123456
1
123
123 DON’T CARE
123
1234
1234
1234
1234 UNDEFINED
NOTE: Output enable (OE\) is inactive (HIGH).
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C)
SMD #5962-92316, Case Outline T
D
A
Q
Pin 1
L
e
b
b1
E
NOTE
0o to 15o
SYMBOL
A
b
b1
c
D
E
E1
e
L
Q
c
E1
SMD SPECIFICATIONS
MIN
MAX
0.075
0.095
0.016
0.020
0.040
0.060
0.008
0.012
1.386
1.414
0.385
0.405
0.390
0.410
0.100 BSC
0.125
0.175
0.040
0.060
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #207 (Package Designator EC)
SMD# 5962-92316, Case Outline Y
A
D1
L1
D
L
e
b
b1
E
b2
SYMBOL
A
b
b1
b2
D
D1
E
e
L
L1
SMD SPECIFICATIONS
MIN
MAX
0.080
0.100
0.022
0.028
0.004
0.014
0.054
0.066
0.815
0.835
0.740
0.760
0.392
0.408
0.050 BSC
0.070
0.080
0.090
0.110
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
MECHANICAL DEFINITIONS*
ASI Case #303 (Package Designator F)
SMD #5962-92316, Case Outline Z
E1
L
Pin 1
Index
e
32
1
17
16
D
b
D1
Bottom View
Top View
A
c
Q
E
SYMBOL
A
b
c
D
D1
E
E1
e
L
Q
SMD SPECIFICATIONS
MIN
MAX
0.097
0.117
0.015
0.019
0.004
0.006
0.812
0.828
0.745
0.755
0.324
0.336
0.405
0.415
0.050 BSC
0.290
0.310
0.032
0.038
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
SMD #5962-92316, Case Outline U
A
D
e
D1
B1
E2
b
E1
E
A2
SYMBOL
A
A2
B1
b
D
D1
E
E1
E2
e
SMD SPECIFICATIONS
MIN
MAX
0.135
0.153
0.026
0.036
0.030
0.040
0.015
0.019
0.812
0.828
0.745
0.760
0.405
0.415
0.435
0.445
0.360
0.380
0.050 BSC
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
ORDERING INFORMATION
EXAMPLE: MT5C1001EC-45/XT
EXAMPLE: MT5C1001C-20L/IT
Device
Package Speed
Options**
Number
Type
ns
MT5C1001
C
-20
L
MT5C1001
C
-25
L
MT5C1001
C
-35
L
MT5C1001
C
-40
L
MT5C1001
C
-55
L
MT5C1001
C
-70
L
Device
Package Speed
Options** Process
Number
Type
ns
MT5C1001
EC
-20
L
/*
MT5C1001
EC
-25
L
/*
MT5C1001
EC
-35
L
/*
MT5C1001
EC
-40
L
/*
MT5C1001
EC
-55
L
/*
MT5C1001
EC
-70
L
/*
Process
/*
/*
/*
/*
/*
/*
EXAMPLE: MT5C1001DCJ-70/XT
EXAMPLE: MT5C1001F-25L/883C
Device
Package Speed
Options**
ns
Number
Type
MT5C1001
F
-20
L
MT5C1001
F
-25
L
MT5C1001
F
-35
L
MT5C1001
F
-40
L
MT5C1001
F
-55
L
MT5C1001
F
-70
L
Device
Package Speed
Options** Process
Number
Type
ns
MT5C1001
DCJ
-20
L
/*
MT5C1001
DCJ
-25
L
/*
MT5C1001
DCJ
-35
L
/*
MT5C1001
DCJ
-40
L
/*
MT5C1001
DCJ
-55
L
/*
MT5C1001
DCJ
-70
L
/*
Process
/*
/*
/*
/*
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
SRAM
Austin Semiconductor, Inc.
MT5C1001
Limited Availability
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator EC
ASI Package Designator C
ASI Part #
MT5C1001C-20L/883C
MT5C1001C-20/883C
MT5C1001C-25L/883C
MT5C1001C-25/883C
MT5C1001C-35L/883C
MT5C1001C-35/883C
MT5C1001C-45L/883C
MT5C1001C-45/883C
ASI Part #
MT5C1001EC-20L/883C
MT5C1001EC-20/883C
MT5C1001EC-25L/883C
MT5C1001EC-25/883C
MT5C1001EC-35L/883C
MT5C1001EC-35/883C
MT5C1001EC-45L/883C
MT5C1001EC-45/883C
SMD Part #
5962-9231608MTA
5962-9231604MTA
5962-9231607MTA
5962-9231603MTA
5962-9231606MTA
5962-9231602MTA
5962-9231605MTA
5962-9231601MTA
ASI Package Designator DCJ
ASI Package Designator F
ASI Part #
MT5C1001F-20L/883C
MT5C1001F-20/883C
MT5C1001F-25L/883C
MT5C1001F-25/883C
MT5C1001F-35L/883C
MT5C1001F-35/883C
MT5C1001F-45L/883C
MT5C1001F-45/883C
SMD Part #
5962-9231608MYA
5962-9231604MYA
5962-9231607MYA
5962-9231603MYA
5962-9231606MYA
5962-9231602MYA
5962-9231605MYA
5962-9231601MYA
ASI Part #
MT5C1001DCJ-20L/883C
MT5C1001DCJ-20/883C
MT5C1001DCJ-25L/883C
MT5C1001DCJ-25/883C
MT5C1001DCJ-35L/883C
MT5C1001DCJ-35/883C
MT5C1001DCJ-45L/883C
MT5C1001DCJ-45/883C
SMD Part #
5962-9231608MZA
5962-9231604MZA
5962-9231607MZA
5962-9231603MZA
5962-9231606MZA
5962-9231602MZA
5962-9231605MZA
5962-9231601MZA
SMD Part #
5962-9231608MUA
5962-9231604MUA
5962-9231607MUA
5962-9231603MUA
5962-9231606MUA
5962-9231602MUA
5962-9231605MUA
5962-9231601MUA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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