MITEL MT8812AP

ISO-CMOS MT8812
8 x 12 Analog Switch Array

Features
ISSUE 5
•
Internal control latches and address decoder
•
Short set-up and hold times
•
Wide operating voltage: 4.5V to 14.5V
•
14Vpp analog signal capability
•
•
R ON 65Ω max. @ V DD=14V, 25°C
∆R ON ≤10Ω @ V DD=14V, 25°C
•
Full CMOS switch for low distortion
•
Minimum feedthrough and crosstalk
•
Low power consumption ISO-CMOS technology
Ordering Information
MT8812AC
40 Pin Ceramic DIP
MT8812AE
40 Pin Plastic DIP
MT8812AP
44 Pin PLCC
0° to 70°C
Description
The Mitel MT8812 is fabricated in MITEL’s ISOCMOS technology providing low power dissipation
and high reliability. The device contains a 8 x12 array
of crosspoint switches along with a 7 to 96 line
decoder and latch circuits. Any one of the 96
switches can be addressed by selecting the
appropriate seven input bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input.
Applications
•
PBX systems
•
Mobile radio
•
Test equipment /instrumentation
•
Analog/digital multiplexers
•
Audio/Video switching
STROBE
DATA RESET
1
VDD
VSS
1
AX1
AX3
8 x 12
7 to 96
Decoder
Switch
Latches
Array
AY0
AY1
96
••••••••••••••••
AX0
AX2
November 1988
Xi I/O
(i=0-11)
96
AY2
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
3-27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
Y2
DATA
Y1
NC
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4
NC
NC
X6
X7
X8
X9
X10
X11
NC
NC
NC
AX3
RESET
AY2
Y3
VDD
Y2
DATA
Y1
Y0
Y3
AY2
RESET
AX3
AX0
NC
NC
X6
X7
X8
X9
X10
X11
NC
Y7
NC
Y6
STROBE
Y5
VSS
NC
AX0
ISO-CMOS
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC
Y7
Y6
STROBE
Y5
VSS
Y4
AX1
AX2
AY0
AY1
NC
MT8812
40 PIN CERDIP/PLASTIC DIP
44 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #*
Name
1
2
3
4,5
6,7
8-13
Y3
AY2
RESET
AX3,AX0
NC
X6-X11
Description
Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array.
Y2 Address Line (Input).
Master RESET (Input): this is used to turn off all switches. Active High.
X3 and X0 Address Lines (Inputs).
No Connection.
X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch
array.
14
NC
No Connection.
15
Y7
Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array.
16
NC
No Connection.
17
Y6
Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array.
18
STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes high and DATA must be stable on the falling edge of the STROBE.
Active High.
19
Y5
Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array.
Ground Reference.
20
VSS
21
Y4
Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array.
22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27
NC
No Connection.
28 - 33 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array.
34
NC
No Connection.
35
Y0
Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array.
36
NC
No Connection.
37
Y1
Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array.
38
DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the
selected switch. Active High.
39
Y2
Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array.
Positive Power Supply.
40
VDD
* Plastic DIP and CERDIP only.
3-28
ISO-CMOS
MT8812
Functional Description
Address Decode
The MT8812 is an analog switch matrix with an array
size of 8 x 12. The switch array is arranged such that
there are 8 columns by 12 rows. The columns are
referred to as the Y input/output lines and the rows
are the X input/output lines. The crosspoint analog
switch array will interconnect any X line with any Y
line when turned on and provide a high degree of
isolation when turned off. The control memory
consists of a 96 bit write only RAM in which the bits
are selected by the address input lines (AY0-AY2,
AX0-AX3). Data is presented to the memory on the
DATA input line. Data is asynchro-nously written into
memory whenever the STROBE input is high and is
latched on the falling edge of STROBE. A logical “1”
written into a memory cell turns the corresponding
crosspoint switch on and a logical “0” turns the
crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous states. Any
combination of X and Y lines can be interconnected
by establishing appropriate patterns in the control
memory. A logical “1” on the RESET input line will
asynchronously return all memory locations to logical
“0” turning off all crosspoint switches.
The seven address lines along with the STROBE
input are logically ANDed to form an enable signal
for the resettable transparent latches. The DATA
input is buffered and is used as the input to all
latches. To write to a location, RESET must be low
while the address and data lines are set up. Then the
STROBE input is set high and then low causing the
data to be latched. The data can be changed while
STROBE is high, however, the corresponding switch
will turn on and off in accordance with the data. Data
must be stable on the falling edge of STROBE in
order for correct data to be written to the latch.
3-29
MT8812
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply Voltage
VDD
VSS
-0.3
-0.3
16.0
VDD+0.3
V
V
2
Analog Input Voltage
VINA
-0.3
VDD+0.3
V
3
Digital Input Voltage
VIN
VSS-0.3
VDD+0.3
V
4
Current on any I/O Pin
I
±15
mA
5
Storage Temperature
TS
+150
°C
6
Package Power Dissipation
0.6
1.0
W
W
PLASTIC DIP
CERDIP
-65
PD
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
TO
0
25
70
°C
1
Operating Temperature
2
Supply Voltage
VDD
4.5
14.5
V
3
Analog Input Voltage
VINA
VSS
VDD
V
4
Digital Input Voltage
VIN
VSS
VDD
V
DC Electrical Characteristics†Characteristics
1
Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated.
Sym
Quiescent Supply Current
Test Conditions
Min
IDD
2
Off-state Leakage Current
(See G.9 in Appendix)
IOFF
3
Input Logic “0” level
VIL
4
Input Logic “1” level
VIH
5
Input Leakage (digital pins)
Typ‡
Max
Units
Test Conditions
1
100
µA
All digital inputs at VIN=VSS or
VDD
7
15
mA
±1
±500
nA
All digital inputs at VIN=2.4V
IVXi - VYjI = VDD - VSS
See Appendix, Fig. A.1
0.8
V
2.4
V
ILEAK
0.1
10
µA
All digital inputs at VIN = VSS
or VDD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym
25°C
Typ
Max
1 On-state
VDD=14V
Resistance VDD=12V
VDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON
45
60
65
145
65
85
95
220
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
∆RON
5
10
3-30
60°C
Typ
Max
10
70°C
Typ
Units
Test Conditions
Max
75
95
110
260
Ω
Ω
Ω
Ω
VSS=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
10
Ω
VDD=14V, VSS=0,
VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
ISO-CMOS
MT8812
AC Electrical Characteristics† - Crosspoint Performance-VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Switch I/O Capacitance
CS
20
pF
f=1 MHz
2
Feedthrough Capacitance
CF
0.2
pF
f=1 MHz
3
Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3dB
F3dB
45
MHz
Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1kΩ
See Appendix, Fig. A.3
4
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
0.01
%
Switch is “ON”; VINA = 2Vpp
sinewave f= 1kHz; RL=1kΩ
5
Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT
-95
dB
All Switches “OFF”; VINA=
2Vpp sinewave f= 1kHz;
RL= 1kΩ.
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk
-45
dB
VINA=2Vpp sinewave
f= 10MHz; RL = 75Ω.
-90
dB
VINA=2Vpp sinewave
f= 10kHz; RL = 600Ω.
-85
dB
VINA=2Vpp sinewave
f= 10kHz; RL = 1kΩ.
-80
dB
VINA=2Vpp sinewave
f= 1kHz; RL = 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.
ns
RL=1kΩ; CL=50pF
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
7
Propagation delay through
switch
tPS
30
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog
I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated.
Characteristics
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
2
Sym
Min
Typ‡
Max
Units
Test Conditions
CXtalk
30
mVpp
Digital Input Capacitance
CDI
10
pF
3
Switching Frequency
FO
4
Setup Time DATA to STROBE
tDS
10
ns
RL= 1kΩ,
CL=50pF
5
Hold Time DATA to STROBE
tDH
10
ns
RL= 1kΩ,
CL=50pF
6
Setup Time Address to STROBE
tAS
10
ns
RL= 1kΩ,
CL=50pF
7
Hold Time Address to STROBE
tAH
10
ns
RL= 1kΩ,
CL=50pF
8
STROBE Pulse Width
tSPW
20
ns
RL= 1kΩ,
CL=50pF
9
RESET Pulse Width
tRPW
40
ns
RL= 1kΩ,
CL=50pF
10
STROBE to Switch Status Delay
tS
40
100
ns
RL= 1kΩ,
CL=50pF
11
DATA to Switch Status Delay
tD
50
100
ns
RL= 1kΩ,
CL=50pF
12
RESET to Switch Status Delay
tR
35
100
ns
RL= 1kΩ,
CL=50pF
20
VIN=3V+VDC squarewave;
RIN=1kΩ, RL=10kΩ.
See Appendix, Fig. A.6
f=1MHz
MHz









† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Refer to Appendix, Fig. A.7 for test circuit.

3-31
MT8812
ISO-CMOS
tRPW
50%
RESET
50%
tSPW
STROBE
50%
50%
50%
tAS
ADDRESS
50%
50%
tAH
DATA
50%
50%
tDS
tDH
ON
SWITCH*
OFF
tR
tS
tD
tR
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
➀
AX0
AX1
AX2
AX3
AY0
AY1
AY2
Connection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
➀
No Connection
➀
No Connection
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
➀
No Connection
➀
No Connection
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
0
↓
X0-Y1
1
0
1
1
1
0
0
X11-Y1
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
X0-Y2
1
0
1
1
0
1
0
X11-Y2
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
0
↓
X0-Y3
1
0
1
1
1
1
0
X11-Y3
0
↓
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
X0-Y4
1
0
1
1
0
0
1
X11-Y4
0
↓
0
↓
0
↓
0
↓
1
↓
0
↓
1
↓
X0-Y5
1
0
1
1
1
0
1
X11-Y5
0
↓
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
X0-Y6
1
0
1
1
0
1
1
X11-Y6
0
↓
0
↓
0
↓
0
↓
1
↓
1
↓
1
↓
X0-Y7
1
0
1
1
1
1
1
X11-Y7
Table 1. Address Decode Truth Table
This address has no effect on device status.
3-32
↓↓
↓↓
↓↓
↓↓
↓↓
↓↓
↓↓