Zarlink MT9300B Multi-channel voice echo canceller Datasheet

MT9300B
Multi-Channel Voice Echo Canceller
Data Sheet
Not recommended for new designs. Use the
ZL38065, 32 channel VEC with enhanced
algorithm.
March 2005
Ordering Information
Features
•
Independent multiple channels of echo
cancellation; from 32 channels of 64 ms to 16
channels of 128 ms with the ability to mix
channels at 128 ms or 64 ms in any combination
•
Independent Power Down mode for each group of
2 channels for power management
•
MT9300BL
MT9300BV
160 Pin MQFP
208 Ball LBGA
-40°C to +85°C
•
Protection against narrow band signal divergence
•
Offset nulling of all PCM channels
ITU-T G.165 and G.168 compliant
•
10 MHz or 20 MHz master clock operation
•
Field proven, high quality performance
•
3.3 Volts operation with 5-Volt tolerant inputs
•
Compatible to ST-BUS and GCI interface at
2 Mb/s serial PCM
•
No external memory required
•
Non-multiplexed microprocessor interface
•
PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
•
IEEE-1149.1 (JTAG) Test Access Port
•
Per channel Fax/Modem G.164 2100 Hz or G.165
2100 Hz phase reversal Tone Disable
Applications
•
Per channel echo canceller parameters control
•
Transparent data transfer and mute
•
Fast reconvergence on echo path changes
•
Non-Linear Processor with high quality subjective
performance
•
Voice over IP network gateways
•
Voice over ATM, Frame Relay
•
T1/E1/J1 multichannel echo cancellation
•
Wireless base stations
•
Echo Canceller pools
•
DCME, satellite and multiplexer systems
VDD VSS
ODE
Echo Canceller Pool
Rin
Sin
Serial
to
Parallel
MCLK
Fsel
PLL
C4i
F0i
Timing
Unit
Group 0
Group 1
Group 2
Group 3
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 4
Group 5
Group 6
Group 7
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 8
Group 9
Group 10
Group 11
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Group 12
Group 13
Group 14
Group 15
ECA/ECB
ECA/ECB
ECA/ECB
ECA/ECB
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Rout
Sout
IC0
RESET
Microprocessor Interface
DS CS R/W A10-A0 DTA
Test Port
D7-D0
IRQ
TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT9300B
Data Sheet
Description
The MT9300B Voice Echo Canceller implements a cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.168 requirements. The MT9300B architecture contains 16 groups of two echo
cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of
128 milliseconds echo cancellation. This provides 32 channels of 64 milliseconds to 16 channels of 128
milliseconds echo cancellation or any combination of the two configurations. The MT9300B supports ITU-T G.165
and G.164 tone disable requirements.
2
Zarlink Semiconductor Inc.
MT9300B
1
2
3
4
5
VSS
ICO
VSS
c4i
VDD1
B
ICO
VSS
ICO
VDD1
C
ICO
ICO
VSS
D
NC
ICO
E
NC
F
G
1
A
H
J
K
L
M
6
7
8
9
ICO
VSS
Sout
F0i
VSS
Rin
VDD1
VSS
VDD2
VDD1
VSS
VDD1
VDD2
ICO
VSS
VSS
NC
NC
VDD1
VDD1
NC
MCLK
VSS
VSS
VSS
VSS
VSS
NC
Fsel
VDD1
VDD1
VSS
VSS
VDD2
VDD2
VSS
VSS
10
11
12
13
VDD1
ICO
VSS
ICO
VSS
VSS
Rout
VDD1
Sin
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD1
1
16
NC
VSS
VSS
ODE
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VDD1
NC
A10
VDD1
VSS
ICO
A9
VSS
VDD1
ICO
A8
VSS
VDD2
VDD2
NC
A7
VSS
VSS
VSS
VSS
NC
A6
VSS
VSS
VSS
VDD1
VDD1
NC
A5
VSS
VSS
VSS
VSS
VSS
NC
A4
ICO
NC
ICO PLLVSS PLLVDD
NC
NC
VSS
VSS
VDD1
VDD1
NC
A3
TDI
TMS
VDD1
VDD1
VSS
VSS
VSS
A2
TDO
TRST
VSS
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VDD1
VDD1
A1
TCK
VSS
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD1
VSS
VDD2
VSS
VSS
VDD1
A0
ICO
VSS
RESET
VDD1
R/W
VDD1
DTA
VDD1
IRQ
VDD1
DS
VDD1
CS
VSS
VSS
VSS
VSS
D0
D1
VDD1
D2
VSS
D3
D4
VSS
D5
VDD1
D6
VSS
D7
VSS
P
T
15
MT9300BV
14
NC
N
R
Data Sheet
VSS
- A1 corner is identified by metallized markings.
Figure 2 - 208 Ball LBGA
3
Zarlink Semiconductor Inc.
MT9300B
107
105
103
101
99
97
93
95
91
89
VSS
NC
NC
NC
NC
NC
VSS
109
NC
111
NC
NC
NC
NC
VDD1
113
NC
NC
NC
NC
VSS
115
NC
NC
NC
NC
VDD1
117
NC
ODE
Sout
Rout
VSS
Sin
Rin
F0i
C4i
VDD1
119
IC0
IC0
IC0
IC0
VSS
IC0
121
VSS
IC0
IC0
NC
VDD1
NC
NC
NC
NC
NC
NC
NC
NC
IC0
IC0
IC0
NC
NC
VSS
VSS
MCLK
VDD1
VDD1
Fsel
IC0
IC0
PLLVSS
PLLVDD
VSS
VSS
NC
NC
TMS
TDI
TDO
TCK
TRST
IC0
RESET
VDD1
NC
Data Sheet
87
85
83
81
123
79
125
77
127
75
129
73
131
71
133
69
135
67
137
65
63
139
61
MT9300BL
141
59
143
57
145
55
147
53
149
51
151
49
153
47
155
45
157
43
159
41
5
7
9
11
13
15
17
19
21
23
25
27
33
35
NC
NC
NC
NC
VDD1
Zarlink Semiconductor Inc.
31
NC
NC
NC
NC
VSS
D7
D6
D5
D4
VDD1
D3
D2
D1
D0
VSS
NC
NC
NC
DTA
R/W
CS
DS
IRQ
VDD1
NC
NC
NC
NC
NC
VSS
VSS
Figure 3 - 160 Pin MQFP
4
29
37
39
NC
NC
VSS
3
VSS
1
NC
VDD1
NC
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD1
NC
NC
NC
IC0
VSS
IC0
A10
A9
A8
VDD1
A7
A6
A5
A4
VSS
A3
A2
A1
A0
VDD1
NC
NC
MT9300B
Data Sheet
Pin Description
Pin #
208-Ball LBGA
A1,A3,A7,A11,A13,A15, A16, B2,
B6,B8,B12, B14, B15,
B16,C3,C5,C7, C9,C11,C12,
C13,C14, C16, D4,D8,D10,
D12,D13,E3, E4,E14,F13,G3,
G4,G7,G8,G9,G10,H7,H8,H9,
H10,H13, H14,J7,J8,J9, J10,
K7,K8, K9,K10,K13, K14,L3,
L4,M13, M14,,M15,N3,N4,N5,
N7,N9,N11,N13,P2,P3,P5,P7,P9.P
11,P13, P14,R2,R14, R15,R16,T1,
T3,T7,T10, T14,T16
160 Pin
MQFP
1, 2, 17, 27,
37, 38, 48,
58, 76, 77,
81, 87, 98,
108, 118,
119, 138,
139, 148,
149
A5,A9,B4,B10,C4,C8,C10,D3,D5, 8, 22, 32,
D7,D9,D11,D14,E13,
43, 53, 63,
F3,F4,F14,H3,H4,J13,J14,L13,L14 79, 93, 103,
,M3,M4,N6,N8, N10,N14,
113, 124,
N15,P4,P6,P8, P10,P15,
141, 142,
R4,R6,R8,R10, R12,T5,T12
159
Name
Description
VSS
Ground.
VDD1
Positive Power Supply. Nominally 3.3 volt.
E15,F15,A12,A10,A6,A2,
B1,B3,C1,C2,D2,E2,J2,K2,R1
57, 59, 114,
115,
116,117,
120,
121,122,
133, 134,
135, 144,
145, 157,
IC0
Internal Connection. These pins must be connected to
VSS for normal operation.
A14,C15,D1,D15,E1,F1, G1,
G15,H1,H15,J1,J15,K1,
K15,L1,L15,F2,L2
3 to 7, 14 to
16,
28 to 31, 33
to 36,
39 to 42, 60
to 62,
64 to 75, 78,
80,
82 to 86, 88
to 92, 94 to
97, 99
to102, 104,
123,
125 to 132,
136, 137,
150,151,160
NC
No connection. These pins must be left open for normal
operation.
R9
9
IRQ
Interrupt Request (Open Drain Output). This output
goes low when an interrupt occurs in any channel. IRQ
returns high when all the interrupts have been read from
the Interrupt FIFO Register. A pull-up resistor (1 K typical)
is required at this output.
5
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Pin Description (continued)
Pin #
Name
Description
208-Ball LBGA
160 Pin
MQFP
R11
10
DS
Data Strobe (Input). This active low input works in
conjunction with CS to enable the read and write
operations.
R13
11
CS
Chip Select (Input). This active low input is used by a
microprocessor to activate the microprocessor port.
R5
12
R/W
Read/Write (Input). This input controls the direction of the
data bus lines (D7-D0) during a microprocessor access.
R7
13
DTA
Data Transfer Acknowledgment (Open Drain Output).
This active low output indicates that a data bus transfer is
completed. A pull-up resistor (1 K typical) is required at
this output.
T2,T4,T6,T8,T9,T11,T13,T15
18, 19, 20, D0 - D3, Data Bus D0 - D7 (Bidirectional). These pins form the 821,
D4 - D7 bit bidirectional data bus of the microprocessor port.
23, 24, 25,
26
P16,N16,M16,L16,K16,
J16,H16,G16,F16,E16, D16
44, 45,46,
47,49, 50,
51,52,54,
55, 56
A0 A10
Address A0 to A10 (Input). These inputs provide the A10
- A0 address lines to the internal registers.
B13
105
ODE
Output Drive Enable (Input). This input pin is logically
AND’d with the ODE bit-6 of the Main Control Register.
When both ODE bit and ODE input pin are high, the Rout
and Sout ST-BUS outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the
Rout and Sout ST-BUS outputs are high impedance.
A8
106
Sout
Send PCM Signal Output (Output). Port 1 TDM data
output streams.
Sout pin outputs serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B9
107
Rout
Receive PCM Signal Output (Output). Port 2 TDM data
output streams. Rout pin outputs serial TDM data streams
at 2.048 Mb/s with 32 channels per stream.
B11
109
Sin
Send PCM Signal Input (Input). Port 2 TDM data input
streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B7
110
Rin
Receive PCM Signal Input (Input). Port 1 TDM data input
streams.
Rin pin receives serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
B5
111
F0i
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS or GCI interface specifications.
6
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Pin Description (continued)
Pin #
Name
Description
208-Ball LBGA
160 Pin
MQFP
A4
112
G2
140
H2
143
K3
146
PLLVSS PLL Ground. Must be connected to VSS.
K4
147
PLLVDD PLL Power Supply. Must be connected to VDD1.
M2
152
TMS
Test Mode Select (3.3 V Input). JTAG signal that controls
the state transitions of the TAP controller. This pin is pulled
high by an internal pull-up when not driven.
M1
153
TDI
Test Serial Data In (3.3 V Input). JTAG serial test
instructions and data are shifted in on this pin. This pin is
pulled high by an internal pull-up when not driven.
N1
154
TDO
Test Serial Data Out (Output). JTAG serial data is output
on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG scan is not enabled.
P1
155
TCK
Test Clock (3.3 V Input). Provides the clock to the JTAG
test logic.
N2
156
TRST Test Reset (3.3 V Input). Asynchronously initializes the
JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up or held
low, to ensure that the MT9300B is in the normal functional
mode. This pin is pulled by an internal pull-down when not
driven.
R3
158
RESET Device Reset (Schmitt Trigger Input). An active low
resets the device and puts the MT9300B into a low-power
stand-by mode.
When the RESET pin is returned to logic high and a
clock is applied to the MCLK pin, the device will
automatically execute initialization routines, which preset
all the Control and Status Registers to their default
power-up values.
C6,D6,J3,J4,N12,P12, G13,G14
C4i
Serial Clock (Input). 4.096 MHz serial clock for shifting
data in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK Master Clock (Input). Nominal 10 MHz or 20 MHz Master
Clock input. May be connected to an asynchronous
(relative to frame signal) clock source.
Fsel
VDD2
Frequency select (Input). This input selects the Master
Clock frequency operation. When Fsel pin is low, nominal
19.2 MHz Master Clock input must be applied. When Fsel
pin is high, nominal 9.6 MHz Master Clock input must be
applied.
These LBGA pins should be wired to VDD2= 1.8 V for
FUTURE USE. If the customer does not intend to use
future generation of the device, then these pins should
be NO CONNECTS
7
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Device Overview
The MT9300B architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo
cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or
Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms
echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of
echo cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-toBack configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both
directions in a single channel, providing full-duplex 64ms echo cancellation.
Each echo canceller contains the following main elements (see Figure 4).
•
Adaptive Filter for estimating the echo channel
•
Subtractor for cancelling the echo
•
Double-Talk detector for disabling the filter adaptation during periods of double-talk
•
Path Change detector for fast reconvergence on major echo path changes
•
Instability Detector to combat oscillation in very low ERL environments
•
Non-Linear Processor for suppression of residual echo
•
Disable Tone Detectors for detecting valid disable tones at send and receive path inputs
•
Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals
•
Offset Null filters for removing the DC component in PCM channels
•
12dB attenuator for signal attenuation
•
Parallel controller interface compatible with Motorola microcontrollers
•
PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding
Each echo canceller in the MT9300B has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
µ/A-Law/
Linear
Offset
Null
GCI
PORT2
Programmable
Bypass
Non-Linear
Processor
Linear/
µ/A-Law
Linear/
µ/A-Law
Microprocessor
Interface
Double-Talk
Detector
Narrow-Band
Detector
Instability
Detector
Rout
(channel N)
Adaptive
Filter
Disable Tone
Detector
+
Control
Sin
(channel N)
MuteR
12dB
Attenuator
Echo Canceller (N), where 0 ≤
Sout
(channel N)
MuteS
Path Change
Detector
Disable Tone
Detector
µ/A-Law/
Linear
Offset
Null
N ≤ 31
Figure 4 - Echo Canceller Functional Block Diagram
8
Zarlink Semiconductor Inc.
GCI
PORT1
Rin
(channel N)
MT9300B
Data Sheet
Adaptive Filter
The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then
subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is
divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal
configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay
configuration, both sections are cascaded to provide 128 ms of echo estimation in channel A. In Back-to Back
configuration, the first section is used in the receive direction and the second section is used in the transmit
direction for the same channel.
Double-Talk Detector
Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.
When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter
coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller
continues to cancel echo using the previous converged echo profile.
A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following
condition:
Lsin > Lrin + 20log10(DTDT)
where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0.
A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo
return. During these periods, the adaptation process is slowed down but it is not halted.
In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to get additional guardband, the DTDT
is set internally to 0.5625 (-5 dB).
In some applications the return loss can be higher or lower than 6 dB. The MT9300B allows the user to change the
detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value
into the DTDT register.
The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation:
DTDT(hex) = hex(DTDT(dec) * 32768)
where 0 < DTDT(dec) < 1
Example:
For DTDT = 0.5625 (-5dB), the
hexadecimal value becomes
hex(0.5625 * 32768) = 4800H
Path Change Detector
Integrated into the MT9300B is a Path Change Detector. This permits fast reconvergence when a major change
occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence
is achieved, but at a much slower speed.
The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional path
clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned
on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon
detection of a major path change.
9
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Non-Linear Processor (NLP)
After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT9300B
uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold
(TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the
programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the
following equation:
TSUP = Lrin + 20log10(NLPTHR)
where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed
in dBm0.
When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal
by an additional 36 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a
spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the
perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP.
The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2.
The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following
equation:
NLPTHR(hex) = hex(NLPTHR(dec) * 32768)
where 0 < NLPTHR(dec) < 1
The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register A1/B1. It should be
noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled.
If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar
spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A
neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values greater
than 80(hex) will increase the noise level. The scaling is done linearly.
Example:
To decrease the comfort noise level
by 3 dB, the register value would be
10 ^ (-3 / 20) * 128
= 0.71 * 128
= 91(dec)
= 5B(hex)
The default factory setting for the Noise Scaling register should be adequate for most operating environments. It is
unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance.
Disable Tone Detector
G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every 450 ms (±
25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone
Detector will trigger.
G.164 recommendation defines the disable tone as a 2100 Hz (±21 Hz) sine wave with a power level between 0 to
-31 dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone
Detector will trigger.
10
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
The MT9300B has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Rin
Tone
Detector
Sin
Tone
Detector
ECA
Status reg
TD bit
Echo Canceller
Rin
Tone
Detector
Sin
Tone
Detector
A
ECB
Status reg
TD bit
Echo Canceller
B
Figure 5 - Disable Tone Detection
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e,. IRQ pin low).
The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per
channel basis. When the PHDis bit is set to 1, G.164 tone disable requirements are selected.
In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the
Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors
internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by
setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the
interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a
given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state.
Instability Detector
In systems where the echo path return loss (ERL) is very low (<3 dB), a high loop gain may result. As a
consequence, an unstable condition may occur due to diverged echo canceller coefficients. This instability can
result in variable pitched ringing or oscillation. Should this ringing occur, the Instability Detector will activate and
suppress the oscillations.
The Instability Detector is activated by setting the RingClr bit in Control Register A3/B3 to "1".
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Zarlink Semiconductor Inc.
MT9300B
channel A
Sin
Data Sheet
Sout
+
channel A
Sin
+
echo
path A
Rout
Sout
echo
path A
Adaptive
Filter (64 ms)
Adaptive Filter
(128 ms)
channel A
PORT2
Optional -12dB pad
E.C.A
channel A
Rout
Rin
PORT1
PORT2
Rin
Optional -12dB pad
E.C.A
PORT1
b) Extended Delay Configuration (128ms)
channel B
+
-
echo
path B
-
Adaptive
Filter (64 ms)
echo
path
channel B
Sout
+
Sin
Optional -12dB pad
Adaptive
Filter (64 ms)
Adaptive
Filter (64 ms)
echo
path
E.C.B
Rout
Optional -12dB pad
PORT2
a) Normal Configuration (64 ms)
E.C.A
Optional -12dB pad
+
Rin
E.C.B
PORT1
c) Back-to-Back Configuration (64 ms)
Figure 6 - Device Configuration
Narrow Band Signal Detector (NBSD)
Single or dual frequency tones (i.e., DTMF tones) present in the receive input (Rin) of the echo canceller for a
prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is
designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When
narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo.
The NBSD can be disabled by setting the NBDis bit to “1” in Control Register 2.
Offset Null Filter
Adaptive filters in general do not operate properly when a DC offset is present at any inputs. To remove the DC
component, the MT9300B incorporates Offset Null filters in both Rin and Sin inputs.
The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2.
ITU-T G.168 Compliance
The MT9300B has been certified G.168 compliant in all 64 ms cancellation modes (i.e. Normal and Back-to-Back
configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.
It should be noted that G.168 compliance is not claimed for the 128 ms Extended Delay mode, although
subjectively no difference can be noticed.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Device Configuration
The MT9300B architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo
cancellers which can be individually controlled (Echo Canceller A and B). They can be set in three distinct
configurations: Normal, Back-to-Back, and Extended Delay. See Figure 6.
Normal Configuration
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously.
Back-to-Back Configuration
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional
echo cancellation is required.
Back-to-Back configuration is selected by writing “1” into the BBM bit of both Control Register A1 and Control
Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured
into Back-to-Back.
Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a
transmission device or between two codecs for echo control on analog trunks.
Extended Delay Configuration
In this configuration, the two echo cancellers from the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and
the second timeslot normally associated with ECB contains undefined data.
Extended Delay configuration is selected by writing “1” into the ExtDl bit in Echo Canceller A, Control Register A1.
For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must
always be set to zero.
Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
Echo Canceller Functional States
Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation.
Mute
In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which
is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with
quiet code.
+Zero
(quiet code)
LINEAR
16 bits
2’s
complement
SIGN/
MAGNITUDE
µ-Law
A-Law
0000h
80h
CCITT (G.711)
µ-Law
A-Law
FFh
D5h
Table 1 - Quiet PCM Code Assignment
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always
be “0”. Refer to Figure 4 and to Control Register 2 for bit description.
Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four control
bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details.
MT9300B Throughput Delay
The throughput delay of the MT9300B varies according to the device configuration. For all device configurations,
Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout
and Sin to Sout paths have a delay of two frames.
Serial PCM I/O channels
There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for
Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output
streams is for Rout pcm channels, and the other set is for Sout channels. See Figure 7 for channel allocation.
The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set
of PCM Send and Receive channels, as illustrated in Figure 4.
125 µsec
F0i
ST-Bus
F0i
GCI interface
Rin/Sin
Rout/Sout
Channel 0
Channel 1
Channel 30
Channel 31
Note: Refer to Figures 9 and 10 for timing details
Figure 7 - ST-BUS and GCI Interface Channel Assignment for 2 Mb/s Data Streams
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Serial Data Interface Timing
The MT9300B provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-Bus and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT9300B automatically detects the
presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling
edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of
the way into the bit cell (See Figure 10). In GCI format, every second rising edge of the C4i clock marks the bit
boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 11).
Base
Addr + Echo Canceller A
Base
Addr + Echo Canceller B
00h Control Reg A1
20h Control Reg B1
01h Control Reg A2
21h Control Reg B2
02h Status Reg
22h Status Reg
03h Reserved
23h Reserved
04h Flat Delay Reg
24h Flat Delay Reg
05h Reserved
25h Reserved
06h Decay Step Size Reg
26h Decay Step Size Reg
07h Decay Step Number
27h Decay Step Number
08h Control Reg A3
28h Control Reg B3
09h Reserved
29h Reserved
0Ah Reserved
2Ah Reserved
0Bh Reserved
2Bh Reserved
0Ch Rin Peak Detect Reg
2Ch Rin Peak Detect Reg
0Eh Sin Peak Detect Reg
2Eh Sin Peak Detect Reg
10h Error Peak Detect Reg
30h Error Peak Detect Reg
12h Reserved
32h Reserved
14h DTDT Reg
34h DTDT Reg
16h Reserved
36h Reserved
18h NLPTHR
38h NLPTHR
1Ah Step Size, MU
3Ah Step Size, MU
1Ch Reserved
3Ch Reserved
1Eh Reserved
3Eh Reserved
Figure 8 - Memory Mapping of per channel Control and Status Registers
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces to PCM
channel #5 on all serial PCM I/O streams.
As illustrated in Figure 8, the “per channel” registers provide independent control and status bits for each echo canceller.
Figure 9 shows the memory map of the control/status register blocks for all echo cancellers.
Group 0
Echo
Cancellers
Registers
Channel 0, EC A Ctrl/Stat Registers
0000H --> 001FH
Channel 1, EC B Ctrl/Stat Registers
0020H --> 003FH
Group 1
Echo
Cancellers
Registers
Channel 2, EC A Ctrl/Stat Registers
0040H --> 005FH
Channel 3, EC B Ctrl/Stat Registers
0060H --> 007FH
Groups 2 --> 14
Echo Cancellers
Registers
Group 15
Echo
Cancellers
Registers
Channel 30, EC A Ctrl/Stat Registers
03C0H --> 03DFH
Channel 31, EC B Ctrl/Stat Registers
03E0H --> 03FFH
Main Control Registers <15:0>
0400H --> 040FH
Interrupt FIFO Register
0410H
Test Register
0411H
Figure 9 - Memory Mapping
When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2
of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Group
Channel
Group
Channel
0
0, 1
8
16, 17
1
2, 3
9
18, 19
2
4, 5
10
20, 21
3
6, 7
11
22, 23
4
8, 9
12
24, 25
5
10, 11
13
26, 27
6
12, 13
14
28, 29
7
14, 15
15
30, 31
Table 2 - Group and Channel allocation
Extended Delay Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries don’t care data. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B
(Channel 5) will carry don’t care data.
Back-to-Back Configuration
For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries don’t care data. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B
(Channel 11) will carry don’t care data.
Power Up Sequence
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the MT9300B in
power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated.
The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500µs for PLL to lock.
C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups of
echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control
Register.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00H to Base Address+3FH, to
the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00H
to Base Address+3FH, for the specific application.
Power Management
Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their
respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are
bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section
for description.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
The typical power consumption can be calculated with the following equation:
PC = 60 * Nb_of_groups + 40, in mW
where 0 ≤ Nb_of_groups ≤ 16
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the
echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation.
Interrupts
The MT9300B provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the MT9300B may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate, application specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT9300B. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or
unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section.
JTAG Support
The MT9300B JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
Test Access Port (TAP)
The TAP provides access to many test functions of the MT9300B. It consists of three input pins and one output pin.
The following pins are found on the TAP.
•
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus
remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register
cells concurrent with the operation of the device and without interfering with the on-chip logic.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
•
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP Controller to control the test
operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally
pulled to V DD when it is not driven from an external source.
•
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register or into a test data register,
depending on the sequence previously applied to the TMS input. Both registers are described in a
subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V DDwhen it is not driven from an external source.
•
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on
the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO
driver is set to a high impedance state.
•
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
Instruction Register
In accordance with the IEEE 1149.1 standard, the MT9300B uses public instructions. The JTAG Interface contains
a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
Test Data Registers
As specified in IEEE 1149.1, the MT9300B JTAG Interface contains three test data registers:
•
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT9300B core logic.
•
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO.
•
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Register Descriptions
Echo Canceller A, Control Register A1
7
6
5
4
3
2
1
0
Reset
INJDis
BBM
PAD
Bypass
AdpDis
0
ExtDl
Echo Canceller B, Control Register B1
7
6
5
4
3
2
1
0
Reset
INJDis
BBM
PAD
Bypass
AdpDis
1
0
Read/Write Address:
00H + Base Address
Reset Value:
00H
Read/Write Address:
20H + Base Address
Reset Value:
02H
Bit
Name
Description
7
Reset
When high, the power-up initialization is executed which presets all register bits
including this bit and clears the Adaptive Filter coefficients.
6
INJDis
When high, the noise injection process is disabled. When low noise injection is
enabled.
5
BBM
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled.
Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register A1 and
Control Register B1) of the same group to the same logic value to avoid conflict.
4
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0 dB.
3
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped.
When low, output data on both Sout and Rout is a function of the echo canceller
algorithm.
2
AdpDis
When high, echo canceller adaptation is disabled. The MT9300B cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
1
0 or 1
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
0
ExtDl
or
0
When high, Echo Cancellers A and B of the same group are internally cascaded into
one 128 ms echo canceller.
When low, Echo Cancellers A and B of the same group operate independently.
Note: Do not enable both Extended-Delay and BBM configurations at the same time.
Control Register B1 bit-0 is a reserved bit and should be written “0”.
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Zarlink Semiconductor Inc.
MT9300B
Echo Canceller A, Control Register A2
Echo Canceller B, Control Register B2
7
6
5
TDis
PHDis
4
3
NLPDis AutoTD
2
NBDis HPFDis
1
0
MuteS
MuteR
Data Sheet
Read/Write Address:
Read/Write Address:
01H + Base Address
21H + Base Address
Reset Value:
00H
Bit
Name
Description
7
TDis
When high, tone detection is disabled. When low, tone detection is enabled.
When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are
disabled entirely and are put into power down mode.
6
PHDis
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone
regardless of the presence/absence of periodic phase reversals.
When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone
with periodic phase reversals.
5
NLPDis
When high, the non-linear processor is disabled.
When low, the non-linear processors function normally. Useful for G.165 conformance
testing.
4
AutoTD
When high, the echo canceller puts itself in Bypass mode when the tone detectors
detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state
of the 2100 Hz tone detectors.
3
NBDis
When high, the narrow-band detector is disabled. When low, the narrow-band
detector is enabled.
2
HPFDis
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
1
MuteS
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
0
MuteR
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
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Zarlink Semiconductor Inc.
MT9300B
Echo Canceller A, Status Register
Echo Canceller B, Status Register
7
6
5
4
3
2
1
0
res
TD
DTDet
res
res
res
TDG
NB
Data Sheet
Read Address:
Read Address:
02H + Base Address
22H + Base Address
Reset Value:
00H
Bit
Name
Description
7
res
Reserved bit.
6
TD
Logic high indicates the presence of a 2100 Hz tone.
5
DTDet
4
res
Reserved bit.
3
res
Reserved bit.
2
res
Reserved bit.
1
TDG
0
NB
Logic high indicates the presence of a double-talk condition.
Tone detection status bit gated with the AutoTD bit.
Logic high indicates that AutoTD has been enabled and the tone detector has
detected the presence of a 2100 Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
Echo Canceller A, Status Register
Echo Canceller B, Status Register
7
6
5
4
3
2
1
0
res
TD
DTDet
res
res
res
TDG
NB
Read Address:
Read Address:
02H + Base Address
22H + Base Address
Reset Value:
00H
Bit
Name
Description
7
res
Reserved bit.
6
TD
Logic high indicates the presence of a 2100 Hz tone.
5
DTDet
4
res
Reserved bit.
3
res
Reserved bit.
2
res
Reserved bit.
1
TDG
0
NB
Logic high indicates the presence of a double-talk condition.
Tone detection status bit gated with the AutoTD bit.
Logic high indicates that AutoTD has been enabled and the tone detector has
detected the presence of a 2100 Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Echo Canceller A, Flat Delay Register (FD)
Echo Canceller B, Flat Delay Register (FD)
Read/Write Address: 04H+ Base Address
Read/Write Address: 24H + Base Address
7
6
5
4
3
2
1
0
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Echo Canceller A, Decay Step Number Register (NS)
Echo Canceller B, Decay Step Number Register (NS)
7
6
5
NS7
NS6
NS5
4
NS4
3
2
NS3
NS2
Read/Write Address: 07H + Base Address
Read/Write Address: 27H + Base Address
1
NS1
0
6
0
0
5
0
4
0
3
2
0
SSC2
1
SSC1
Power Reset Value
00H
NS0
Echo Canceller A, Decay Step Size Control Register (SSC)
Echo Canceller B, Decay Step Size Control Register (SSC)
7
Power Reset Value
00H
Read/Write Address: 06H + Base Address
Read/Write Address: 26H + Base Address
0
SSC0
Power Reset Value
04H
Note: Bits marked with “0” are reserved bits and should be written “0”.
Amplitude of MU
FIR Filter Length (512 or 1024 taps)
1.0
Step Size (SS)
Flat Delay (FD7-0)
2-16
Time
Number of Steps (NS7-0)
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation stepsize (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo
canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat
delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be
programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive
Filter. Note that in the following register descriptions, one tap is equivalent to 125 µs (64 ms/512 taps).
FD7-0
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The delay is defined as
FD7-0 x 8 taps. For example; if FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo canceller FIR filter. The valid range
of FD7-0 is: 0 £ FD7-0 £ 64 in normal mode and 0 £ FD7-0 £ 128 in extended-delay mode. The default value of FD7-0 is zero.
SSC2-0
Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The
decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For
example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is
04h.
NS7-0
Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period
of SS taps (see SSC2-0). The start of the exponential decay is defined as:
Filter Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0.
For example, if NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] = 512 - [4 x (4x24)] = 256
taps for a filter length of 512 taps.
23
Zarlink Semiconductor Inc.
MT9300B
Echo Canceller A, Control Register A3
Echo Canceller B, Control Register B3
7
6
5
4
res
res
res
res
3
2
RingClr PathClr
1
0
PathDet
res
Data Sheet
Read/Write Address:
Read/Write Address:
08H + Base Address
28H + Base Address
Reset Value:
0AH
Bit
Name
Description
7-4
res
3
RingClr
When high, the instability detector is activated.
When low, the instability detector is disabled.
2
PathClr
When high, the current echo channel estimate will be cleared and the echo canceller
will enter fast convergence mode upon detection of a path change. When low, the
echo canceller will keep the current path estimate but revert to fast convergence
mode upon detection of a path change. Note: this bit is ignored if PathDet is low.
1
PathDet
When high, the path change detector is activated. When low, the path change
detector is disabled.
0
res
Reserved bits. Must always be set to zero for normal operation.
Reserved bit. Must always be set to zero for normal operation.
24
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Echo Canceller A, Rin Peak Detect Register 2 (RP)
Echo Canceller B, Rin Peak Detect Register 2 (RP)
7
6
5
RP15
RP14
RP13
4
RP12
3
RP11
2
RP10
Echo Canceller A, Rin Peak Detect Register 1 (RP)
Echo Canceller B, Rin Peak Detect Register 1 (RP)
7
6
5
4
3
2
RP7
RP6
RP5
RP4
RP3
RP2
Read Address: 0DH + Base Address
Read Address: 2DH + Base Address
1
0
RP9
RP8
Power Reset Value
N/A
Read Address: 0CH + Base Address
Read Address: 2CH + Base Address
1
0
RP1
RP0
Power Reset Value
N/A
These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in
Register 1.
Echo Canceller A, Sin Peak Detect Register 2 (SP)
Echo Canceller B, Sin Peak Detect Register 2 (SP)
7
SP15
6
SP14
5
SP13
4
SP12
3
SP11
2
SP10
Read Address: 0FH + Base Address
Read Address: 2FH + Base Address
1
0
SP9
SP8
Echo Canceller A, Sin Peak Detect Register 1 (SP)
Echo Canceller B, Sin Peak Detect Register 1 (SP)
7
SP7
6
SP6
5
SP5
Power Reset Value
N/A
Read Address: 0EH + Base Address
Read Address: 2EH + Base Address
4
3
2
1
0
SP4
SP3
SP2
SP1
SP0
Power Reset Value
N/A
These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s complement
linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Echo Canceller A, Error Peak Detect Register 2 (EP)
Echo Canceller B, Error Peak Detect Register 2 (EP)
7
6
5
4
EP15
EP14
EP13
EP12
3
Read Address: 11H + Base Address
Read Address: 31H + Base Address
2
EP11
EP10
1
0
EP9
EP8
Echo Canceller A, Error Peak Detect Register 1 (EP)
Echo Canceller B, Error Peak Detect Register 1 (EP)
7
6
EP7
EP6
Power Reset Value
N/A
Read Address: 10H + Base Address
Read Address: 30H + Base Address
5
4
3
2
1
0
EP5
EP4
EP3
EP2
EP1
EP0
Power Reset Value
N/A
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement linear coded
format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1.
Echo Canceller A, Double-Talk Detection Threshold Register 2
Echo Canceller B, Double-Talk Detection Threshold Register 2
7
DTDT15
6
DTDT14
5
DTDT13
4
DTDT12
3
2
1
0
DTDT11
DTDT10
DTDT9
DTDT8
Echo Canceller A, Double-Talk Detection Threshold Register 1
Echo Canceller B, Double-Talk Detection Threshold Register 1
7
6
5
4
3
2
1
DTDT7
DTDT6
DTDT5
DTDT4
Read/Write Address: 15H + Base Address
Read/Write Address: 35H + Base Address
DTDT3
DTDT2
DTDT1
Power Reset Value
48H
(DTDT)
Read/Write Address: 14h + Base Address
Read/Write Address: 34h + Base Address
0
Power Reset Value
DTDT0
(DTDT)
00H
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value
defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in
Register 1.
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Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Echo Canceller A, Non-Linear Processor Threshold Register 2
Echo Canceller B, Non-Linear Processor Threshold Register 2
Read/Write Address: 19H + Base Address
Read/Write Address: 39H + Base Address
7
6
5
4
3
2
1
0
NLP15
NLP14
NLP13
NLP12
NLP11
NLP10
NLP9
NLP8
Echo Canceller A, Non-Linear Processor Threshold Register 1
Echo Canceller B, Non-Linear Processor Threshold Register 1
7
6
5
4
3
2
1
NLP7
NLP6
NLP5
NLP4
NLP3
NLP2
NLP1
Power Reset Value
0CH
(NLPTHR)
Read/Write Address: 18H + Base Address
Read/Write Address: 38H + Base Address
0
NLP0
(NLPTHR)
Power Reset Value
E0H
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s complement linear
value defaults to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low
byte is in Register 1.
Echo Canceller A, Adaptation Step Size (MU) Register 2
Echo Canceller B, Adaptation Step Size (MU) Register 2
7
MU15
6
MU14
5
MU13
4
3
2
MU12
MU11
MU10
Read/Write Address: 1BH + Base Address
Read/Write Address: 3BH + Base Address
1
MU9
Echo Canceller A, Adaptation Step Size (MU) Register 1
Echo Canceller B, Adaptation Step Size (MU) Register 1
7
6
5
4
3
2
1
MU7
MU6
MU5
MU4
MU3
MU2
MU1
Power Reset Value
40H
0
MU8
(MU)
Read/Write Address: 1AH + Base Address
Read/Write Address: 3AH + Base Address
0
MU0
(MU)
Power Reset Value
00H
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0
The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1.
27
Zarlink Semiconductor Inc.
MT9300B
Main Control Register 0
7
6
5
WR_all
ODE
MIRQ
4
(EC group 0)
3
2
MTDBI MTDAI Format
1
0
LAW
PWUP
Data Sheet
Read/Write Address:
400H
Reset Value:
00H
Bit
Name
Description
7
WR_all
Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped
into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16
Groups of Echo Cancellers as per Group 0.
When low, address mapping is per Figure 8.
Note: Only the Main Control Register 0 has the WR_all bit.
6
ODE
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When
both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are
high impedance.
Note: Only the Main Control Register 0 has the ODE bit.
5
MIRQ
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are
masked. The Tone Detectors operate as specified in their Echo Canceller B, Control
Register 2.
When low, the Tone Detectors Interrupts are active.
Note: Only the Main Control Register 0 has the MIRQ bit.
4
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
3
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
2
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, accept sign-magnitude
PCM code.
1
LAW
A/m Law: When high, both Echo Cancellers A and B for a given group, accept A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, accept m-Law companded
PCM code.
28
Zarlink Semiconductor Inc.
MT9300B
Main Control Register 0
7
6
5
WR_all
ODE
MIRQ
4
(EC group 0)
3
2
MTDBI MTDAI Format
1
0
LAW
PWUP
Data Sheet
Read/Write Address:
400H
Reset Value:
00H
Bit
Name
Description
0
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given
group, are active.
When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed
from Rin to Rout and from Sin to Sout with two frames delay.
When the PWUP bit toggles from zero to one, the echo canceller A and B execute their
initialization routine which presets their registers, Base Address+00H to Base
Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients.
Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for
their specific application.
29
Zarlink Semiconductor Inc.
MT9300B
7
unused
6
5
unused
unused
4
3
2
MTDBI MTDAI Format
Main Control Register 1
Main Control Register 2
Main Control Register 3
Main Control Register 4
Main Control Register 5
Main Control Register 6
Main Control Register 7
Main Control Register 8
Main Control Register 9
Main Control Register 10
Main Control Register 11
Main Control Register 12
Main Control Register 13
Main Control Register 14
Main Control Register 15
1
0
LAW
PWUP
Data Sheet
Reset Value:
(EC group 1)
(EC group 2)
(EC group 3)
(EC group 4)
(EC group 5)
(EC group 6)
(EC group 7)
(EC group 8)
(EC group 9)
(EC group 10)
(EC group 11)
(EC group 12)
(EC group 13)
(EC group 14)
(EC group 15)
00H
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
401H
402H
403H
404H
405H
406H
407H
408H
409H
40AH
40BH
40CH
40DH
40EH
40FH
Bit
Name
Description
7-5
unused
Unused Bits.
4
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
3
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
2
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, select sign-magnitude
PCM code.
1
LAW
A/m Law: When high, both Echo Cancellers A and B for a given group, select A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, select m-Law companded
PCM code.
30
Zarlink Semiconductor Inc.
MT9300B
7
unused
6
5
unused
unused
4
3
2
MTDBI MTDAI Format
Main Control Register 1
Main Control Register 2
Main Control Register 3
Main Control Register 4
Main Control Register 5
Main Control Register 6
Main Control Register 7
Main Control Register 8
Main Control Register 9
Main Control Register 10
Main Control Register 11
Main Control Register 12
Main Control Register 13
Main Control Register 14
Main Control Register 15
1
0
LAW
PWUP
Data Sheet
Reset Value:
(EC group 1)
(EC group 2)
(EC group 3)
(EC group 4)
(EC group 5)
(EC group 6)
(EC group 7)
(EC group 8)
(EC group 9)
(EC group 10)
(EC group 11)
(EC group 12)
(EC group 13)
(EC group 14)
(EC group 15)
00H
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
401H
402H
403H
404H
405H
406H
407H
408H
409H
40AH
40BH
40CH
40DH
40EH
40FH
Bit
Name
Description
0
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given
group, are active.
When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed
from Rin to Rout and from Sin to Sout with two frames delay.
When the PWUP bit toggles from zero to one, the echo cancellers A and B execute
their initialization routine which presets their registers, Base Address+00H to Base
Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients.
Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for
their specific application.
31
Zarlink Semiconductor Inc.
MT9300B
Interrupt FIFO Register
7
6
5
4
3
2
1
0
IRQ
0
0
I4
I3
I2
I1
I0
Bit
Name
7
IRQ
6:5
0
4:0
I<4:0>
Data Sheet
Read Address:
410H (Read only)
Reset Value:
00H
Description
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt
FIFO register is read.
Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bits. Always zero
I<4:0> binary code indicates the channel number at which a Tone Detector state
change has occurred.
Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Test Register
7
6
5
4
3
2
1
0
res
res
res
res
res
res
res
Tirq
Read/Write Address:
411H
Reset Value:
00H
Bit
Name
Description
7:1
res
Reserved bits. Must always be set to zero for normal operation.
0
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine.
When high, any change to MTDBI and MTDAI bits of the Main Control Register will
cause an interrupt and its corresponding channel number will be available from the
Interrupt FIFO Register.
When low, normal operation is selected.
32
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD1
-0.3
5.0
V
1
Supply Voltage
2
Voltage on any 3.3 V I/O pins (other than supply
pins)
VI3
VSS - 0.3
VDD1+0.5
V
3
Voltage on any 5 V Tolerant I/O pins (other than
supply pins)
VI5
VSS - 0.3
5.5
V
4
Continuous Current at digital outputs
IO
20
mA
5
Package power dissipation
PD
2.0
W
6
Storage temperature
TS
150
°C
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
1
Sym.
Min.
Operating Temperature
TOP
-40
Typ.‡
Max.
Units
+85
°C
2
Positive Supply
VDD1
3.0
3.6
V
3
Input High Voltage on 3.3 V
tolerant
VIH3
0.7VDD1
VDD1
V
4
Input High Voltage on 5 V tolerant
VIH5
0.7VDD1
5.5
V
5
Input Low Voltage
VIL
0.3VDD1
V
3.3
Test Conditions
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
1
Supply Current
2
3
4
5
I
N
P
U
T
S
6
7
8
9
10
Min.
Typ.‡
ICC
Max.
Units
Test Conditions
250
µA
RESET = 0
IDD
308
375
mA
All channels active
Power Consumption
PC
1.0
1.35
W
All channels active
Input High Voltage
VIH
Input Low Voltage
VIL
Input Leakage
Input Leakage on Pullup
Input Leakage on Pulldown
Input Pin Capacitance
O
U
T
P
U
T
S
Sym.
0.7VDD1
IIH/IIL
ILU
ILD
V
-30
30
CI
Output High Voltage
VOH
Output Low Voltage
VOL
High Impedance Leakage
Output Pin Capacitance
0.3VDD1
V
10
-55
65
µA
µA
µA
10
pF
0.8VDD1
VIN=VSS to VDD1 or 5.5V
VIN=VSS
VIN=VDD1
See Note 1
V
IOH = 12 mA
0.4
V
IOL = 12 mA
IOZ
10
µA
VIN=VSS to 5.5V
CO
10
pF
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1=3.3 V and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
33
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
- Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym.
Level
Units
1
CMOS Threshold
VTT
0.5VDD1
V
2
CMOS Rise/Fall Threshold Voltage High
VHM
0.7VDD1
V
3
CMOS Rise/Fall Threshold Voltage Low
VLM
0.3VDD1
V
Conditions
† Characteristics are over recommended operating conditions unless otherwise stated
i
AC Electrical Characteristics† - Frame Pulse and C4i
Characteristic
1 Frame pulse width (ST-BUS, GCI)
Sym.
Min.
tFPW
20
Typ.‡
Max.
Units
2*
ns
Notes
tCP-20
2 Frame Pulse Setup time before
C4i falling (ST-BUS or GCI)
tFPS
10
122
150
ns
3 Frame Pulse Hold Time from C4i
falling (ST-BUS or GCI)
tFPH
10
122
150
ns
4 C4i Period
tCP
190
244.1
300
ns
5 C4i Pulse Width High
tCH
85
150
ns
6 C4i Pulse Width Low
tCL
85
150
ns
7 C4i Rise/Fall Time
tr, tf
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
Rin/Sin Set-up Time
tSIS
10
ns
2
Rin/Sin Hold Time
tSIH
10
ns
3
Rout/Sout Delay
- Active to Active
tSOD
60
ns
CL=150pF
4
Output Data Enable (ODE)
Delay
tODE
30
ns
CL=150pF, RL=1K
See Note 1
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing
* Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
34
Zarlink Semiconductor Inc.
MT9300B
Data Sheet
tFPW
F0i
VTT
tFPS
tCP
tFPH
tCH
tCL
tr
VHM
VTT
VLM
C4i
tSOD
Rout/Sout
Bit 0, Channel 31
tf
Bit 7, Channel 0
tSIS
Rin/Sin
Bit 6, Channel 0
tSIH
Bit 7, Channel 0
Bit 0, Channel 31
VTT
Bit 5, Channel 0
Bit 6, Channel 0
VTT
Bit 5, Channel 0
Figure 10 - ST-BUS Timing at 2.048 Mb/s
tFPW
F0i
VTT
tFPS
tCP
tFPH
tCH
tCL
tr
VHM
VTT
VLM
C4i
tSOD
Sout/Rout
Bit 7, Channel 31)
tf
Bit 0, Channel 0
tSIS
Sin/Rin
Bit 1, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
Figure 11 - GCI Interface Timing at 2.048 Mb/s
VTT
ODE
tODE
tODE
Sout/Rout
VTT
tSIH
Bit 0, Channel 0
Bit 7, Channel 31)
Bit 2, Channel 0
HiZ
Valid Data
HiZ
VTT
Figure 12 - Output Driver Enable (ODE)
35
Zarlink Semiconductor Inc.
VTT
MT9300B
Data Sheet
AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated.
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
1 Master Clock Frequency,
- Fsel = 0
- Fsel = 1
fMCF0
fMCF1
19.0
9.5
20.0
10.0
21.0
10.5
MHz
MHz
2 Master Clock Low
tMCL
20
ns
3 Master Clock High
tMCH
20
ns
Notes
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing
tMCH
VTT
MCLK
tMCL
Figure 13 - Master Clock
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
0
ns
3
Address setup from DS falling
tADS
0
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
0
ns
6
Address hold after DS rising
tADH
0
ns
7
Data delay on read
tDDR
8
Data hold on read
tDHR
3
9
Data setup on write
tDSW
0
ns
10 Data hold on write
tDHW
0
ns
Test Conditions
79
ns
CL=150pF, RL=1K
15
ns
CL=150pF, RL=1K
See Note 1
11 Acknowledgment delay
tAKD
80
ns
CL=150pF, RL=1K
12 Acknowledgment hold time
tAKH
0
8
ns
CL=150pF, RL=1K,
See Note 1
13 IRQ delay
tIRD
20
65
ns
CL=150pF, RL=1K,
See Note 1
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing
* Note 1:High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
36
Zarlink Semiconductor Inc.
MT9300B
DS
Data Sheet
tCSS
tCSH
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A10
tDDR
D0-D7
READ
VTT
tDHR
VTT
VALID READ DATA
tDSW
tDHW
D0-D7
WRITE
VTT
VALID WRITE DATA
tAKD
tAKH
VTT
DTA
tIRD
VTT
IRQ
Figure 14 - Motorola Non-Multiplexed Bus Timing
37
Zarlink Semiconductor Inc.
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