MT93L04 128-Channel Voice Echo Canceller Data Sheet Features • January 2006 MT93L04 is a Multi-chip Module (MCM) consisting of 4 MT93L00 devices thus providing 128 channels of 64 msec Echo Cancellation • Each device (MT93L00) is independent of the each other • Each device has the capability of cancelling echo over 32 channels • The MCM module provides more than 40% board space savings • Each device (MT93L00) can be programmed independently in any mode e.g back to back or extended delay to provide capability of cancelling different echo tails • Ordering Information MT93L04AG 365 Ball BGA Trays MT93L04AG2 365 Ball BGA** Trays **Pb Free Tin/Silver/Copper -40°C to +85°C • Voice over ATM, Frame Relay • T1/E1/J1 multichannel echo cancellation • Wireless base stations • DCME, satellite and multiplexer systems The MT93L04 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The MT93L04 architecture contains 64 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 128 channels of 64 milliseconds to 64 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT93L04 supports ITU-T G.165 and G.164 tone disable requirements. Applications Voice over IP network gateways Echo Canceller pools Description Each device has the same Jtag identification code • • MT93L00 MT93L00 1 4 MT93L00 MT93L00 3 2 Figure 1 - MT93L04 is MULTI-CHIP Module Consisting of 4 MT93L00 Devices 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT93L04 VDD1 (3.3V) Data Sheet VDD2 (1.8V) VSS ODE Echo Canceller Pool Rin Sin Serial to Parallel MCLK Fsel PLL C4i F0i Group 0 Group 1 Group 2 Group 3 ECA/ECB ECA/ECB ECA/ECB ECA/ECB Group 4 Group 5 Group 6 Group 7 ECA/ECB ECA/ECB ECA/ECB ECA/ECB Group 8 Group 9 Group 10 Group 11 ECA/ECB ECA/ECB ECA/ECB ECA/ECB Group 12 Group 13 Group 14 Group 15 ECA/ECB ECA/ECB ECA/ECB ECA/ECB Parallel to Serial Note: Refer to Figure 4 for Echo Canceller block diagram Rout Sout IC0 RESET Timing Unit Microprocessor Interface DS CS R/W A10-A0 DTA D7-D0 Test Port IRQ TMS TDI TDO TCK TRST Figure 2 - Functional Block Diagram for Single MT93L00 (32 channels) Features of Single MT93L00 • Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination • Independent Power Down mode for each group of 2 channels for power management • ITU-T G.165 and G.168 compliant • Field proven, high quality performance • Compatible to ST-BUS and GCI interface at 2 Mb/s serial PCM • PCM coding, µ/A-Law ITU-T G.711 or sign magnitude • Per channel Fax/Modem G.164 2100 Hz or G.165 2100 Hz phase reversal Tone Disable • Per channel echo canceller parameters control • Transparent data transfer and mute • Fast reconvergence on echo path changes • Non-Linear Processor with high quality subjective performance • Protection against narrow band signal divergence • Offset nulling of all PCM channels • 10 MHz or 20 MHz master clock operation • 3.3 V pads and 1.8 V Logic core operation with 5-Volt tolerant inputs • No external memory required • Non-multiplexed microprocessor interface • IEEE-1149.1 (JTAG) Test Access Port 2 Zarlink Semiconductor Inc. MT93L04 1 2 3 4 5 6 7 8 9 10 11 Data Sheet 12 14 13 15 16 17 18 19 20 1 A Tsig(12)_d1 SC_Fclk_d1 B Tsig(15)_d1 D Halt_d1 F G PLLVSS1_d1 Sin_d2 Vss Vss Vss Vss Vss Vss Vdd2 Vss Vss Vss Vss Vdd1 Vss Vss Vss Vss Vdd2 Vss Vss Vdd2 Vss Vss Vdd1 Vss Vdd1 Vdd1 Vdd2 Vss Vss Vss Vss Vss Vss Step_d2 TD0_d2 Vss Vss Vss Vdd2 Vdd2 Vdd2 Tck_d2 TDI_d2 D(4)_d2 4 5 6 DT1_d3 Tsig(3)_d3 A_ICI_d3 SG1_d3 TM1_d3 A(3)_d2 8 A(10)_d2 9 TCK_d3 Halt_d3 PLLVSS1_d3 10 11 12 13 Figure 3 - 365 Ball BGA Zarlink Semiconductor Inc. 14 15 D(0)_d3 A(3)_d3 D(5)_d3 A(2)_d3 D(3)_d3 U V W D(1)_d3 D(4)_d3 DTAB_d3 17 T A(1)_d3 DSB_d3 16 A(6)_d3 D(7)_d3 IRQB_d3 TDO_d3 - A1 corner is identified by metallized markings. 3 D(6)_d3 Trstb_d3 A(9)_d3 A(0)_d3 CSB_d3 R A(5)_d3 Tsig(8)_d3 RESETB_d3 TMS_d3 PLLVDD_d3 P A(7)_d3 A(4)_d3 D(2)_d3 N Tsig(0)_d3 A(8)_d3 SC_fclk_d3 R/WB_d3 Test_en_d3 Tsig(2)_d3 A_IC2_d3 Tsig(9)_d3 TDI_d3 Rout_d3 Tsig(1)_d3 Tsig(10)_d3 Tsig(14)_d3 PLLVSS2_d3 A(8)_d2 D(5)_d2 7 Tm2_d3 L ODE_d3 Tsig(4)_d3 A(10)_d3 Tsig(12)_d3 K M SC_set_d3 Tsig(11)_d3 Tsig(13)_d3 AT1_d3 A(7)_d2 D(6)_d2 D(1)_d2 Mclk_d3 A(2)_d2 D(3)_d2 Csb_d2 Fsel_d3 A(1)_d2 D(7)_d2 D(0)_d2 RESETB_d2 3 Rin_d3 FOIB_d3 Sout_d3 Tsig(7)_d3 Tsig(6)_d3 Vdd1 Vdd1 D(3)_d4 D(0)_d4 Tsig(5)_d3 Vdd1 Tsig(15)_d3 Step_d3 A(4)_d2 A(9)_d2 D(2)_d2 DSB_d2 D(2)_d4 C4IB_d3 Vdd2 Vss D(4)_d4 DTAB_d4 Vdd2 Vss Vss A(5)_d2 A(0)_d2 Tsig(0)_d2 R/WB_d2 Trstb_d2 PLLVDD_d2 A_IC1_d2 DTAB_d2 Test_en_d2 A(2)_d4 D(6)_d4 Vdd2 Vss Vss Vss Vss A(6)_d2 A_IC2_d2 Tsig(1)_d2 Tms_d2 G H SC_en_d3 Irqb_d2 AT1_d2 F J Tsig(3)_d2 Tsig(2)_d2 E D(5)_d4 SC_reset_d3 PLLVSS2_d2 D A(1)_d4 D(7)_d4 Vdd1 Tsig(4)_d2 C A(3)_d4 A(0)_d4 Vdd2 SG1_d2 Mclk_d2 A(4)_d4 SC_in_d3 Tsig(5)_d2 A(6)_d4 R/WB_d4 ST_mclk_d3 Tsig(6)_d2 Halt_d2 A(7)_d4 A(5)_d4 Sin_d3 Ode_d2 A(9)_d4 A(8)_d4 SM_mclk_d3 ST_mclk_d2 TM2_d2 2 TCK_d4 Tsig(7)_d2 TM1_d2 1 Vss Vdd1 Vdd2 SC_en_d2 Tsig(13)_d2 Tsig(14)_d2 Y Vdd1 Vdd1 Tsig(8)_d2 Tsig(12)_d2 PLLVSS1_d2 Vdd2 Rout_d2 Tsig(11)_d2 Fsel_d2 Vdd2 Csb_d4 Rin_d2 FOIB_d2 Tsig(9)_d2 T W Vdd2 D(1)_d4 D(1)_d1 SC_Fclk_d2 DT1_d2 RESETB_d4 Vdd2 SM_mclk_d2 SC_set_d2 V Tsig(15)_d4 A(10)_d4 A_IC2_d4 Dsb_d4 C4IB_d2 Sout_d2 U Trstb_d4 TMS_d4 IRQB_d4 IRQB_d1 RESETB_d1 Tsig(15)_d2 AT1_d4 PLLVSS1_d4 DTAB_d1 Tsig(10)_d2 R Vdd1 D(2)_d1 CSB_d1 P Vdd1 Halt_d4 A_IC1_d4 Tsig(4)_d4 PLLVSS2_d4 TMS_d1 SC_reset_d2 N A(5)_d1 A(6)_d1 Tsig(1)_d4 Tsig(0)_d4 TDI_d4 Test_en_d4 TDI_d1 TRSTB_D1 M Tsig(13)_d4 A_IC1_d1 Step_d4 D(0)_d1 TD0_d1 SC_in_d2 A(3)_d1 Tsig(3)_d4 TD0_d4 PLLVDD_d4 B Tsig(2)_d4 ODE_d4 Rout_d4 Mclk_d4 Tsig(7)_d4 Tsig(6)_d4 Tsig(5)_d4 SC_en_d4 Tsig(9)_d4 A(8)_d1 A(7)_d1 C4IB Tsig(8)_d4 Tsig(12)_d4 Tm1_d4 Sin_d4 D(4)_d1 R/WB_d1 TCK_D1 K SG1_d4 Rin_d4 FOIB_d4 SC_reset_d4 D(3)_d1 Dsb_d1 Sout_d4 SM_mclk_d4 ST_mclk_d4 TM2_d4 Tsig(11)_d4 A(9)_d1 Tsig(4)_d1 A(1)_d1 D(5)_d1 Test_En_d1 SC_set_d4 D(6)_d1 DT1_d1 H L D(7)_d1 Step_d1 AT1_d1 A(4)_d1 SC_fclk_d4 DT1_d4 Tsig(3)_d1 Tsig(5)_d1 Rin_d1 SG1(d1) PLLVSS2_d1 J A(2)_d1 Tsig(14)_d1 PLLVDD_d1 SC_in_d4 Tsig(14)_d4 Tsig(10)_d4 A(10)_d1 Tsig(6)_d1 C4IB A(0)_d1 Mclk_d1 Tsig(2)_d1 Sout_d1 SC_en_d1 Tsig(10)_d1 Tm1_d1 E Sin_d1 Tsig(8)_d1 Tsig(0)_d1 A_IC2_d1 ODE_d1 SC_set_d1 Tsig(9)_d1 Fsel_d1 Rout_d1 ST_mclk_d1 Tsig(13)_d1 Fsel_d4 A SC_reset_d1 TM2_d1 Tsig(1)_d1 Tsig(7)_d1 SM_mclk_d1 Tsig(11)_d1 C FOIB_d1 SC_in_d1 18 19 20 Y MT93L04 Data Sheet Pin Description Signal Name Signal Type VDD1 = 3.3V Power VDD2 = 1.8V Power VSS Power BGA Ball # Signal Description R6, R8, R13, R15, N15,H15, Positive Power Supply. Nominally 3.3 volt. F15,F13,F8,F6,H6,N6, P6, VDD1 = I/O Voltage R9,R10,R11,R12,M15, L15,K15,J15,F12,F11, F10,F9,J6, K6, L6,M6, Positive Power Supply. Nominally 1.8 volt. VDD2 = Core Voltage H8,H9,H10,H11,H12, H13, Ground J8, J9,J10,J11, J12,J13,K8,K9,K10,K11,K1 2,K13 L8,L9,L10, L11,L12,L13,M8,M9,M10,M 11,M12, M13, N8, N9,N10,N11,N12,N13 DEVICE 1 TMS_d1 User Signal J4 Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. TDI_d1 User Signal J3 Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. TDO_d1 User Signal J2 Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. TCK_d1 User Signal J1 Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. TRSTB_d1 User Signal K1 Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Test_En_d1 ICO H1 Internal Connection. Connected to VSS for normal operation RESETB_d1 User Signal K2 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. 4 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description IRQB_d1 User Signal J5 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. DSB_d1 User Signal H2 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. CSB_d1 User Signal K3 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/WB_d1 User Signal H3 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. DTAB_d1 User Signal K4 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. D(0)_d1 User Signal H4 D(1)_d1 User Signal K5 D(2)_d1 User Signal H5 D(3)_d1 User Signal G4 D(4)_d1 User Signal G5 D(5)_d1 User Signal F4 D(6)_d1 User Signal F5 D(7)_d1 User Signal E5 A(0)_d1 User Signal D4 A(1)_d1 User Signal E6 A(2)_d1 User Signal D5 A(3)_d1 User Signal E7 A(4)_d1 User Signal D7 A(5)_d1 User Signal E8 A(6)_d1 User Signal E10 A(7)_d1 User Signal D8 A(8)_d1 User Signal D10 A(9)_d1 User Signal C10 A(10)_d1 User Signal B10 Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. 5 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description A_IC1_d1 ICO E9 Internal Connection. Connected to VSS for normal operation A_IC2_d1 ICO A8 Internal Connection. Connected to VSS for normal operation Tsig(0)_d1 NC A10 No connection. The pin must be left open for normal operation. Tsig(1)_d1 NC A9 No connection. The pin must be left open for normal operation. Tsig(2)_d1 NC B9 No connection. The pin must be left open for normal operation. Tsig(3)_d1 NC C9 No connection. The pin must be left open for normal operation. Tsig(4)_d1 NC D9 No connection. The pin must be left open for normal operation. Tsig(5)_d1 NC C8 No connection. The pin must be left open for normal operation. Tsig(6)_d1 NC B8 No connection. The pin must be left open for normal operation. Tsig(7)_d1 NC A7 No connection. The pin must be left open for normal operation. ODE_d1 User Signal B7 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Sout_d1 User Signal C7 Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rout_d1 User Signal A6 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Sin_d1 User Signal B6 Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rin_d1 User Signal D6 Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. 6 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description FOIb_d1 User Signal A5 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C4IB_d1 User Signal C6 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). SC_set_d1 ICO B5 Internal Connection. Connected to VSS for normal operation SM_mclk_d1 ICO A4 Internal Connection. Connected to VSS for normal operation ST_mclk_d1 ICO B4 Internal Connection. Connected to VSS for normal operation SC_en_d1 ICO C5 Internal Connection. Connected to VSS for normal operation SC_In_d1 ICO A3 Internal Connection. Connected to VSS for normal operation SC_Reset:_d1 ICO B3 Internal Connection. Connected to VSS for normal operation SC_Fclk_d1 ICO A2 Internal Connection. Connected to VSS for normal operation Tsig(8)_d1 NC C4 Internal Connection. The pin must be left open for normal operation. Tsig(9)_d1 NC C3 Internal Connection. The pin must be left open for normal operation. Tsig(10)_d1 NC D3 Internal Connection. The pin must be left open for normal operation. Tsig(11)_d1 NC B2 Internal Connection. The pin must be left open for normal operation. Tsig(12)_d1 NC A1 Internal Connection. The pin must be left open for normal operation. Tsig(13)_d1 NC C2 Internal Connection. The pin must be left open for normal operation. Tsig(14)_d1 NC E3 Internal Connection. The pin must be left open for normal operation. Tsig(15)_d1 NC B1 Internal Connection. The pin must be left open for normal operation. Tm1_d1 ICO D2 Internal Connection. Connected to VSS for normal operation Tm2_d1 ICO C1 Internal Connection. Connected to VSS for normal operation 7 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Sg1_d1 ICO E4 Internal Connection. Connected to VSS for normal operation DT1_d1 NC F3 No connection. The pin must be left open for normal operation. MCLK_d1 User Signal E2 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Fsel_d1 User Signal D1 Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Halt_d1 ICO E1 Internal Connection. Connected to VSS for normal operation Step_d1 ICO F2 Internal Connection. Connected to VSS for normal operation PLLVSS1_d1 Power G3 PLL Ground. Must be connected to VSS PLLVDD_d1 Power F1 PLL Power Supply. Must be connected to VDD2 PLLVSS2_d1 Power G2 PLL Ground. Must be connected to VSS AT1_d1 NC G1 No connection. The pin must be left open for normal operation. TMS_d2 Signal V4 Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. TDI_d2 Signal Y2 Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. TDO_d2 Signal W3 Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. TCK_d2 Signal Y3 Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. TRSTB_d2 Signal W4 Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. DEVICE 2 8 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Test_En_d2 ICO V5 Internal Connection. Connected to VSS for normal operation RESETB_d2 Signal Y4 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. IRQB_d2 Signal U5 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. DSB_d2 Signal W5 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. CSB_d2 Signal Y5 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/WB_d2 Signal V6 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. DTAB_d2 Signal U6 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. D(0)_d2 Signal W6 D(1)_d2 Signal Y6 D(2)_d2 Signal V7 D(3)_d2 Signal W7 D(4)_d2 Signal Y7 D(5)_d2 Signal Y8 D(6)_d2 Signal W8 D(7)_d2 Signal V8 Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. 9 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description A(0)_d2 Signal U9 A(1)_d2 Signal V9 A(2)_d2 Signal W9 A(3)_d2 Signal Y9 A(4)_d2 Signal U10 A(5)_d2 Signal T10 A(6)_d2 Signal T9 A(7)_d2 Signal V10 A(8)_d2 Signal W10 A(9)_d2 Signal U8 A(10)_d2 Signal Y10 A_IC1_d2 ICO T8 Internal Connection. Connected to VSS for normal operation A_IC2_d2 ICO T7 Internal Connection. Connected to VSS for normal operation Tsig(0)_d2 NC U7 No connection. The pin must be left open for normal operation. Tsig(1)_d2 NC T6 No connection. The pin must be left open for normal operation. Tsig(2)_d2 NC U4 No connection. The pin must be left open for normal operation. Tsig(3)_d2 NC T5 No connection. The pin must be left open for normal operation. Tsig(4)_d2 NC R5 No connection. The pin must be left open for normal operation. Tsig(5)_d2 NC T4 No connection. The pin must be left open for normal operation. Tsig(6)_d2 NC P5 No connection. The pin must be left open for normal operation. Tsig(7)_d2 NC P4 No connection. The pin must be left open for normal operation. ODE_d2 Signal N5 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. 10 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Sout_d2 Signal L1 Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rout_d2 Signal N4 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Sin_d2 Signal L2 Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rin_d2 Signal N3 Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. FOIb_d2 Signal N2 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C4IB_d2 Signal L3 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). SC_set_d2 ICO N1 Internal Connection. Connected to VSS for normal operation SM_mclk_d2 ICO L4 Internal Connection. Connected to VSS for normal operation ST_mclk_d2 ICO M5 Internal Connection. Connected to VSS for normal operation SC_en_d2 ICO L5 Internal Connection. Connected to VSS for normal operation SC_In_d2 ICO M1 Internal Connection. Connected to VSS for normal operation SC_Reset:_d2 ICO M2 Internal Connection. Connected to VSS for normal operation SC_Fclk_d2 ICO M3 Internal Connection. Connected to VSS for normal operation Tsig(8)_d2 NC M4 No connection. The pin must be left open for normal operation. Tsig(9)_d2 NC P1 No connection. The pin must be left open for normal operation. Tsig(10)_d2 NC P2 No connection. The pin must be left open for normal operation. 11 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Tsig(11)_d2 NC R1 No connection. The pin must be left open for normal operation. Tsig(12)_d2 NC R2 No connection. The pin must be left open for normal operation. Tsig(13)_d2 NC P3 No connection. The pin must be left open for normal operation. Tsig(14)_d2 NC T1 No connection. The pin must be left open for normal operation. Tsig(15)_d2 NC U1 No connection. The pin must be left open for normal operation. Tm1_d2 ICO T2 Internal Connection. Connected to VSS for normal operation Tm2_d2 ICO R3 Internal Connection. Connected to VSS for normal operation Sg1_d2 ICO R4 Internal Connection. Connected to VSS for normal operation DT1_d2 NC V1 No connection. The pin must be left open for normal operation. MCLK_d2 Signal U2 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Fsel_d2 Signal W1 Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Halt_d2 ICO T3 Internal Connection. Connected to VSS for normal operation Step_d2 ICO V2 Internal Connection. Connected to VSS for normal operation PLLVSS1_d2 Power Y1 PLL Ground. Must be connected to VSS PLLVDD_d2 Power W2 PLL Power Supply. Must be connected to VDD2 PLLVSS2_d2 Power U3 PLL Ground. Must be connected to VSS AT1_d2 NC V3 No connection. The pin must be left open for normal operation. DEVICE 3 TMS_d3 Signal W13 Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. 12 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description TDI_d3 Signal V13 Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. TDO_d3 Signal Y14 Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. TCK_d3 Signal W14 Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. TRSTB_d3 Signal Y15 Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Test_En_d3 ICO V14 Internal Connection. Connected to VSS for normal operation RESETB_d3 Signal W15 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. IRQB_d3 Signal Y16 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. DSB_d3 Signal Y17 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. CSB_d3 Signal W16 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/WB_d3 Signal V15 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. B_d3 Signal Y18 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. 13 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description D(0)_d3 Signal W17 D(1) _d3 Signal Y19 D(2)_d3 Signal V16 D(3)_d3 Signal W18 D(4)_d3 Signal Y20 D(5)_d3 Signal W19 D(6)_d3 Signal V17 D(7)_d3 Signal V18 A(0)_d3 Signal U18 A(1)_d3 Signal V19 A(2)_d3 Signal W20 A(3)_d3 Signal V20 A(4)_d3 Signal T18 A(5)_d3 Signal U19 A(6)_d3 Signal U20 A(7)_d3 Signal T19 A(8)_d3 Signal R18 A(9)_d3 Signal T20 A(10)_d3 Signal R17 A_IC1_d3 ICO R19 Internal Connection. Connected to VSS for normal operation A_IC2_d3 ICO P18 Internal Connection. Connected to VSS for normal operation Tsig(0)_d3 NC R20 No connection. The pin must be left open for normal operation. Tsig(1)_d3 NC P19 No connection. The pin must be left open for normal operation. Tsig(2)_d3 NC P20 No connection. The pin must be left open for normal operation. Tsig(3)_d3 NC N19 No connection. The pin must be left open for normal operation. Tsig(4)_d3 NC N18 No connection. The pin must be left open for normal operation. Tsig(5)_d3 NC M17 No connection. The pin must be left open for normal operation. Tsig(6)_d3 NC M18 No connection. The pin must be left open for normal operation. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. 14 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Tsig(7)_d3 NC M19 No connection. The pin must be left open for normal operation. ODE_d3 Signal M20 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Sout_d3 Signal L20 Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rout_d3 Signal N20 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Sin_d3 Signal M16 Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rin_d3 Signal L19 Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. FOIb_d3 Signal L18 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C4IB_d3 Signal L17 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). SC_set_d3 ICO N17 Internal Connection. Connected to VSS for normal operation SM_mclk_d3 ICO L16 Internal Connection. Connected to VSS for normal operation ST_mclk_d3 ICO N16 Internal Connection. Connected to VSS for normal operation SC_en_d3 ICO P17 Internal Connection. Connected to VSS for normal operation SC_In_d3 ICO P16 Internal Connection. Connected to VSS for normal operation SC_Reset:_d3 ICO R16 Internal Connection. Connected to VSS for normal operation 15 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description SC_Fclk_d3 ICO T17 Internal Connection. Connected to VSS for normal operation Tsig(8)_d3 NC U17 No connection. The pin must be left open for normal operation. Tsig(9)_d3 NC U16 No connection. The pin must be left open for normal operation. Tsig(10)_d3 NC T16 No connection. The pin must be left open for normal operation. Tsig(11)_d3 NC T15 No connection. The pin must be left open for normal operation. Tsig(12)_d3 NC U15 No connection. The pin must be left open for normal operation. Tsig(13)_d3 NC T14 No connection. The pin must be left open for normal operation. Tsig(14)_d3 NC U14 No connection. The pin must be left open for normal operation. Tsig(15)_d3 NC T13 No connection. The pin must be left open for normal operation. Tm1_d3 ICO Y11 Internal Connection. Connected to VSS for normal operation Tm2_d3 ICO U13 Internal Connection. Connected to VSS for normal operation Sg1_d3 ICO W11 Internal Connection. Connected to VSS for normal operation DT1_d3 NC V11 No connection. The pin must be left open for normal operation. MCLK_d3 Signal U11 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. Fsel_d3 Signal T12 Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Halt_d3 ICO Y13 Internal Connection. Connected to VSS for normal operation Step_d3 ICO T11 Internal Connection. Connected to VSS for normal operation PLLVSS1_d3 Power Y12 PLL Ground. Must be connected to VSS PLLVDD_d3 Power W12 PLL Power Supply. Must be connected to VDD2 16 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description PLLVSS2_d3 Power V12 PLL Ground. Must be connected to VSS AT1_d3 NC U12 No connection. The pin must be left open for normal operation. TMS_d4 Signal E16 Test Mode Select (3.3 V Input). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven. TDI_d4 Signal D17 Test Serial Data In (3.3 V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. TDO_d4 Signal C18 Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. TCK_d4 Signal F16 Test Clock (3.3 V Input). Provides the clock to the JTAG test logic. TRSTB_d4 Signal E17 Test Reset (3.3 V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT93L00 is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. Test_En_d4 ICO G16 Internal Connection. Connected to VSS for normal operation RESETB_d4 Signal F17 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. IRQB_d4 Signal G17 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. DSB_d4 Signal H16 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. DEVICE 4 17 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description CSB_d4 Signal K16 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/WB_d4 Signal H17 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. DTAB_d4 Signal K17 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. D(0)_d4 Signal K18 D(1)_d4 Signal J16 D(2)_d4 Signal K19 D(3)_d4 Signal K20 D(4)_d4 Signal J20 D(5)_d4 Signal J19 D(6)_d4 Signal J18 D(7)_d4 Signal J17 A(0)_d4 Signal H18 A(1)_d4 Signal H19 A(2)_d4 Signal H20 A(3)_d4 Signal G20 A(4)_d4 Signal G19 A(5)_d4 Signal G18 A(6)_d4 Signal F20 A(7)_d4 Signal F19 A(8)_d4 Signal F18 A(9)_d4 Signal E20 A(10)_d4 Signal E19 A_IC1_d4 ICO D20 Internal Connection. Connected to VSS for normal operation A_IC2_d4 ICO E18 Internal Connection. Connected to VSS for normal operation Tsig(0)_d4 NC D19 No connection. The pin must be left open for normal operation. Tsig(1)_d4 NC C20 No connection. The pin must be left open for normal operation. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. 18 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Tsig(2)_d4 NC B20 No connection. The pin must be left open for normal operation. Tsig(3)_d4 NC C19 No connection. The pin must be left open for normal operation. Tsig(4)_d4 NC D18 No connection. The pin must be left open for normal operation. Tsig(5)_d4 NC C17 No connection. The pin must be left open for normal operation. Tsig(6)_d4 NC B19 No connection. The pin must be left open for normal operation. Tsig(7)_d4 NC A20 No connection. The pin must be left open for normal operation. ODE_d4 Signal B18 Output Drive Enable (Input). This input pin is logically AND’d with the ODE bit-6 of the Main Control Register. When both ODE bit and ODE input pin are high, the Rout and Sout ST-BUS outputs are enabled.When the ODE bit is low or the ODE input pin is low, the Rout and Sout STBUS outputs are high impedance. Sout_d4 Signal A19 Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rout_d4 Signal C16 Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Sin_d4 Signal B17 Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Rin_d4 Signal A18 Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. FOIb_d4 Signal B16 Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. C4IB_d4 Signal C15 Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). SC_set_d4 ICO A17 Internal Connection. Connected to VSS for normal operation 19 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description SM_mclk_d4 ICO A16 Internal Connection. Connected to VSS for normal operation ST_mclk_d4 ICO B15 Internal Connection. Connected to VSS for normal operation SC_en_d4 ICO C14 Internal Connection. Connected to VSS for normal operation SC_In_d4 ICO A15 Internal Connection. Connected to VSS for normal operation SC_Reset:_d4 ICO B14 Internal Connection. Connected to VSS for normal operation SC_Fclk_d4 ICO A14 Internal Connection. Connected to VSS for normal operation Tsig(8)_d4 NC C13 No connection. The pin must be left open for normal operation. Tsig(9)_d4 NC D12 No connection. The pin must be left open for normal operation. Tsig(10)_d4 NC A12 No connection. The pin must be left open for normal operation. Tsig(11)_d4 NC B12 No connection. The pin must be left open for normal operation. Tsig(12)_d4 NC C12 No connection. The pin must be left open for normal operation. Tsig(13)_d4 NC E11 No connection. The pin must be left open for normal operation. Tsig(14)_d4 NC A13 No connection. The pin must be left open for normal operation. Tsig(15)_d4 NC E12 No connection. The pin must be left open for normal operation. Tm1_d4 ICO D11 Internal Connection. Connected to VSS for normal operation Tm2_d4 ICO B13 Internal Connection. Connected to VSS for normal operation Sg1_d4 ICO C11 Internal Connection. Connected to VSS for normal operation DT1_d4 NC B11 No connection. The pin must be left open for normal operation. MCLK_d4 Signal D13 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock input. May be connected to an asynchronous (relative to frame signal) clock source. 20 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description Fsel_d4 Signal A11 Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. Halt_d4 ICO E13 Internal Connection. Connected to VSS for normal operation Step_d4 ICO D14 Internal Connection. Connected to VSS for normal operation PLLVSS1_d4 Power E14 PLL Ground. Must be connected to VSS PLLVDD_d4 Power D15 PLL Power Supply. Must be connected to VDD2 PLLVSS2_d4 Power D16 PLL Ground. Must be connected to VSS AT1_d4 NC E15 No connection. The pin must be left open for normal operation. 21 Zarlink Semiconductor Inc. MT93L04 Data Sheet Description of the Single MT93L00 Device Overview The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers, Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation. Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • Path Change detector for fast reconvergence on major echo path changes • Instability Detector to combat oscillation in very low ERL environments • Non-Linear Processor for suppression of residual echo • Disable Tone Detectors for detecting valid disable tones at send and receive path inputs • Narrow-Band Detector for preventing Adaptive Filter divergence from narrow-band signals • Offset Null filters for removing the DC component in PCM channels • 12 dB attenuator for signal attenuation • Parallel controller interface compatible with Motorola microcontrollers • PCM encoder/decoder compatible with µ/A-Law ITU-T G.711 or Sign-Magnitude coding Each echo canceller in the MT93L00 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. 22 Zarlink Semiconductor Inc. MT93L04 Sin (channel N) Offset Null m/A-Law/ Linear + Data Sheet Non-Linear Processor Linear/ m/A-Law - Sout (channel N) MuteS Programmable Bypass Double-Talk Detector Narrow-Band Detector Instability Detector Rout (channel N) Microprocessor Interface Control ST-BUS PORT2 Adaptive Filter Disable Tone Detector Linear/ m/A-Law MuteR 12dB Attenuator Offset Null Path Change Detector ST-BUS PORT1 Disable Tone Detector m/A-Law/ Linear Rin (channel N) Echo Canceller (N), where 0 ≤ N ≤ 31 Figure 4 - Echo Canceller Functional Block Diagram Adaptive Filter The adaptive filter adapts to the echo path and generates an estimate of the echo signal. This echo estimate is then subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is divided into two sections. Each section contains 512 taps providing 64 ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and the second section to channel B. In Extended Delay configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back configuration, the first section is used in the receive direction and the second section is used in the transmit direction for the same channel. Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the relative signal levels of Rin (Lrin) and Sin (Lsin) meet the following condition: Lsin > Lrin + 20log10(DTDT) where DTDT is the Double-Talk Detection Threshold. Lsin and Lrin are signal levels expressed in dBm0. A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo return. During these periods, the adaptation process is slowed down but it is not halted. 23 Zarlink Semiconductor Inc. MT93L04 Data Sheet In G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to get additional guardband, the DTDT is set internally to 0.5625 (-5 dB). In some applications the return loss can be higher or lower than 6 dB. The MT93L00 allows the user to change the detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value into the DTDT register. The DTDT register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: DTDT(hex) = hex(DTDT(dec) * 32768) where 0 < DTDT(dec) < 1 Example: For DTDT = 0.5625 (-5dB), the hexadecimal value becomes hex(0.5625 * 32768) = 4800h Path Change Detector Integrated into the MT93L00A is a Path Change Detector. This permits fast reconvergence when a major change occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. The Path Change Detector is activated by setting the PathDet bit in Control Register A3/B3 to "1". An optional path clearing feature can be enabled by setting the PathClr bit in Control Register A3/B3 to "1". With path clearing turned on, the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change. Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT93L00 uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR). TSUP can be calculated by the following equation: TSUP = Lrin + 20log10(NLPTHR) where NLPTHR is the Non-Linear Processor Threshold register value and Lrin is the relative power level expressed in dBm0. When the level of residual error signal falls below TSUP, the NLP is activated further attenuating the residual signal by an additional 36 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the perceived noise level constant. Consequently, the user does not hear the activation and de-activation of the NLP. The NLP processor can be disabled by setting the NLPDis bit to “1” in Control Register 2. 24 Zarlink Semiconductor Inc. MT93L04 Data Sheet The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the following equation: NLPTHR(hex) = hex(NLPTHR(dec) * 32768) where 0 < NLPTHR(dec) < 1 The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register A1/B1. It should be noted that the NLPTHR is valid and the comfort noise injection is active only when the NLP is enabled. If the comfort noise injector is unable to correctly match the level of the background noise (because of peculiar spectral characteristics, for example), the injected level can be fine-tuned using the Noise Scaling register. A neutral value of 80(hex) will prevent any scaling. Values less than 80(hex) will reduce the noise level, values greater than 80(hex) will increase the noise level. The scaling is done linearly. Example: To decrease the comfort noise level by 3 dB, the register value would be 10 ^ (-3 / 20) • 128 = 0.71 • 128 = 91(dec) = 5B(hex) The default factory setting for the Noise Scaling register should be adequate for most operating environments. It is unlikely that it will need to be changed. It has also been set to a value which will ensure G.168 compliance. Disable Tone Detector G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every 450 ms (± 25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will trigger. G.164 recommendation defines the disable tone as a 2100 Hz (±21 Hz) sine wave with a power level between 0 to -31 dBm0. If the disable tone is present for a minimum of 400 milliseconds, with or without phase reversal, the Tone Detector will trigger. The MT93L00 has two Tone Detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 5 and to the Interrupts section. Rin Tone Detector Sin Tone Detector ECA Status reg TD bit Echo Canceller A Rin Tone Detector Sin Tone Detector ECB Status reg TD bit Echo Canceller B Figure 5 - Disable Tone Detection Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the 25 Zarlink Semiconductor Inc. MT93L04 Data Sheet frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is generated (i.e., IRQ pin low). The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per channel basis. When the PHDis bit is set to 1, G.164 tone disable requirements are selected. In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by setting the AutoTD bit in Control Register 2 to high. In external mode, an external controller is needed to service the interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a given channel, the external controller must switch the echo canceller from Enable Adaptation to Bypass state. Instability Detector In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause stability problems in the adaptive filter. This instability can result in variable pitched ringing or oscillation. Should this ringing occur, the Instability Detector will activate and suppress the oscillations. The Instability Detector is activated by setting the RingClr bit in Control Register A3/B3 to "1". Narrow Band Signal Detector (NBSD) Single or dual frequency tones (i.e., DTMF tones) present in the receive input (Rin) of the echo canceller for a prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, adaptation is halted but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NBDis bit to “1” in Control Register 2. Offset Null Filter Adaptive filters in general do not operate properly when a DC offset is present at any inputs. To remove the DC component, the MT93L00 incorporates Offset Null filters in both Rin and Sin inputs. The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2. ITU-T G.168 Compliance The MT93L00 has been certified G.168 compliant in all 64 ms cancellation modes (i.e., Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. It should be noted that G.168 compliance is not claimed for the 128 ms Extended Delay mode, although subjectively no difference can be noticed. Device Configuration The MT93L00 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figure 6. Normal Configuration In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in Figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously. 26 Zarlink Semiconductor Inc. MT93L04 Data Sheet Back-to-Back Configuration In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing full-duplex 64 ms echo cancellation. See Figure 6c. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. Back-to-Back configuration is selected by writing “1” into the BBM bit of both Control Register A1 and Control Register B1 of a given group of echo cancellers. Table 2 shows the 16 groups of 2 cancellers that can be configured into Back-to-Back. Examples of Back-to-Back configuration include positioning one group of echo cancellers between a CODEC and a transmission device or between two codecs for echo control on analog trunks. Extended Delay configuration In this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. See Figure 6b. This configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB contains undefined data. Extended Delay configuration is selected by writing “1” into the ExtDl bit in Echo Canceller A, Control Register A1. For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must always be set to zero. Table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity. Echo Canceller Functional States Each echo canceller has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. Mute In Normal and in Extended Delay configurations, writing a “1” into the MuteR bit replaces Rin with quiet code which is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with quiet code. 27 Zarlink Semiconductor Inc. MT93L04 Sin channel A Data Sheet Sout + channel A Sin echo path A Rout Adaptive Filter (128 ms) channel A Optional -12dB pad channel A Rout Rin E.C.A Sout echo path A Adaptive Filter (64ms) PORT2 + PORT1 PORT2 E.C.A Rin Optional -12dB pad PORT1 b) Extended Delay Configuration (128ms) channel B + - echo path B Sout + Sin - Adaptive Filter (64ms) echo path channel B Optional -12dB pad Adaptive Filter (64ms) Adaptive Filter (64ms) echo path E.C.B Rout Optional -12dB pad PORT2 a) Normal Configuration (64ms) E.C.A Optional -12dB pad + Rin E.C.B PORT1 c) Back-to-Back Configuration (64ms) Figure 6 - Device Configuration +Zero (quiet code) LINEAR 16 bits 2’s complement SIGN/ MAGNITUDE µ-Law A-Law CCITT (G.711) µ-Law A-Law 0000h 80h FFh D5h Table 1 - Quiet PCM Code Assignment In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Sout. In Extended Delay and in Back -to -Back configurations, MuteR and MuteS bits of Echo Canceller B must always be “0”. Refer to Figure 4 and to Control Register 2 for bit description. Bypass The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame (125 µs) in order to properly clear the filter. Disable Adaptation When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The adaptation process is halted, however, the echo canceller continues to cancel echo. 28 Zarlink Semiconductor Inc. MT93L04 Data Sheet Enable Adaptation In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller to model the echo return path characteristics in order to cancel echo. This is the normal operating state. The echo canceller functions are selected in Control Register A1/B1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. Refer to the Registers Description for details. MT93L00 Throughput Delay The throughput delay of the MT93L00 varies according to the device configuration. For all device configurations, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames. Serial PCM I/O Channels There are two sets of TDM I/O streams, each with channels numbered from 0 to 31. One set of input streams is for Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output streams is for Rout pcm channels, and the other set is for Sout channels. See Figure 7 for channel allocation. The arrangement and connection of PCM channels to each echo canceller is a 2 port I/O configuration for each set of PCM Send and Receive channels, as illustrated in Figure 4. Serial Data Interface Timing The MT93L00 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz. The input and output data rate of the ST-Bus and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT93L00 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way into the bit cell (See Figure 9). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 10). 29 Zarlink Semiconductor Inc. MT93L04 Base Addr + Echo Canceller A Data Sheet Base Addr + Echo Canceller B 00h Control Reg A1 20h Control Reg B1 01h Control Reg 2 21h Control Reg 2 02h Status Reg 22h Status Reg 03h Reserved 23h Reserved 04h Flat Delay Reg 24h Flat Delay Reg 05h Reserved 25h Reserved 06h Decay Step Size Reg 26h Decay Step Size Reg 07h Decay Step Number 27h Decay Step Number 08h Control Reg A3 28h Control Reg B3 09h Control Reg A4 29h Control Reg B4 0Ah Noise Scaling 2Ah Noise Scaling 0Bh Injection Rate 2Bh Injection Rate 0Ch Rin Peak Detect Reg 2Ch Rin Peak Detect Reg 0Eh Sin Peak Detect Reg 2Eh Sin Peak Detect Reg 10h Error Peak Detect Reg 30h Error Peak Detect Reg 12h Reserved 32h Reserved 14h DTDT Reg 34h DTDT Reg 16h Reserved 36h Reserved 18h NLPTHR 38h NLPTHR 1Ah Step Size, MU 3Ah Step Size, MU 1Ch Reserved 3Ch Reserved 1Eh Reserved 3Eh Reserved Figure 7 - Memory Mapping of per channel Control and Status Registers Memory Mapped Control and Status registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces to PCM channel #5 on all serial PCM I/O streams. As illustrated in Figure 7, the “per channel” registers provide independent control and status bits for each echo canceller. Figure 8 shows the memory map of the control/status register blocks for all echo cancellers. When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section. 30 Zarlink Semiconductor Inc. MT93L04 Data Sheet Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended Delay or Back-to-Back Normal Configuration For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B, channels 2 and 3 are active. Group Channel Group Channel 0 0, 1 8 16, 17 1 2, 3 9 18, 19 2 4, 5 10 20, 21 3 6, 7 11 22, 23 4 8, 9 12 24, 25 5 10, 11 13 26, 27 6 12, 13 14 28, 29 7 14, 15 15 30, 31 Table 2 - Group and Channel Allocation Extended Delay Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don’t care data. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B (Channel 5) will carry don’t care data. Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries don’t care data. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B (Channel 11) will carry don’t care data. 31 Zarlink Semiconductor Inc. MT93L04 Data Sheet Group 0 Echo Cancellers Registers Channel 0, EC A Ctrl/Stat Registers 0000h --> 001Fh Channel 1, EC B Ctrl/Stat Registers 0020h --> 003Fh Group 1 Echo Cancellers Registers Channel 2, EC A Ctrl/Stat Registers 0040h --> 005Fh Channel 3, EC B Ctrl/Stat Registers 0060h --> 007Fh Groups 2 --> 14 Echo Cancellers Registers Group 15 Echo Cancellers Registers Channel 30, EC A Ctrl/Stat Registers 03C0h --> 03DFh Channel 31, EC B Ctrl/Stat Registers 03E0h --> 03FFh Main Control Registers <15:0> 0400h --> 040Fh Interrupt FIFO Register 0410h Test Register 0411h Figure 8 - Memory Mapping Power Up Sequence On power up, the RESET pin must be held low for 100µs. Forcing the RESET pin low will put the MT93L00 in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero. When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500µs for PLL to lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 16 groups of echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control Register. For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute their initialization routine. The initialization routine sets their registers, Base Address+00H to Base Address+3FH, to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00H to Base Address+3FH, for the specific application. Power Management Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section for description. 32 Zarlink Semiconductor Inc. MT93L04 Data Sheet The typical power consumption can be calculated with the following equation: PC =9* Nb_of_groups + 3.6, in mW where 0 < Nb_of_groups < 16 Call Initialization To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the echo canceller in bypass mode for at least one frame (125 µs) and then enabling adaptation. Interrupts The MT93L00 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is detected and released. Although the MT93L00 may be configured to react automatically to tone disable status on any input PCM voice channels, the user may want for the external HOST processor to respond to Tone Disable information in an appropriate, application specific manner. Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt when a Tone Disable releases. Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory containing the channel number of the echo canceller that has generated the interrupt. All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will toggle low for each pending interrupt. After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address mapping of Status register). The TD bit indicates the presence of a Tone Disable. The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT93L00. To provide more flexibility, the MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section. JTAG Support The MT93L00 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only. Test Access Port (TAP) The TAP provides access to many test functions of the MT93L00. It consists of three input pins and one output pin. The following pins are found on the TAP. • Test Clock Input (TCK) The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. 33 Zarlink Semiconductor Inc. MT93L04 • Data Sheet Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD1 when it is not driven from an external source. • Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VDD1 when it is not driven from an external source • Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data from the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the Boundary Scan cells, the TDO driver is set to a high impedance state. • Test Reset (TRST) This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS. Instruction Register In accordance with the IEEE 1149.1 standard, the MT93L00 uses public instructions. The JTAG Interface contains a 3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. Test Data Registers As specified in IEEE 1149.1, the MT93L00 JTAG Interface contains three test data registers: • Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT93L00 core logic. • Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. 34 Zarlink Semiconductor Inc. MT93L04 Data Sheet Register Descriptions Echo Canceller A, Control Register A1 7 6 5 4 Reset INJDis BBM PAD 3 2 Bypass AdpDis Read/Write Address: 00H + Base Address 1 0 0 ExtDl Reset Value: Echo Canceller B, Control Register B1 7 6 5 4 Reset INJDis BBM PAD 3 2 Bypass AdpDis 00H. Read/Write Address: 20H + Base Address 1 0 1 0 Reset Value: 02H. Bit Name Description 7 Reset When high, the power-up initialization is executed which presets all register bits including this bit and clears the Adaptive Filter coefficients. 6 INJDis When high, the noise injection process is disabled. When low noise injection is enabled. 5 BBM When high the Back to Back configuration is enabled. When low the Normal configuration is enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always set both BBM bits of the two echo cancellers (Control Register A1 and Control Register B1) of the same group to the same logic value to avoid conflict. 4 PAD When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low the Rin to Rout path gain is 0 dB. 3 Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter coefficients are set to zero and the filter adaptation is stopped. When low, output data on both Sout and Rout is a function of the echo canceller algorithm. 2 AdpDis When high, echo canceller adaptation is disabled. The MT93L00 cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics. 1 0 or 1 Bits marked as “1” or “0” are reserved bits and should be written as indicated. 0 ExtDl or 0 When high, Echo Cancellers A and B of the same group are internally cascaded into one 128 ms echo canceller. When low, Echo Cancellers A and B of the same group operate independently. Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit-0 is a reserved bit and should be written “0”. 35 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Control Register A2 Echo Canceller B, Control Register B2 7 TDis 6 5 4 3 2 1 Data Sheet Read/Write Address: 01H + Base Address Read/Write Address: 21H + Base Address 0 PHDis NLPDis AutoTD NBDis HPFDis MuteS Reset Value: MuteR 00H. Bit Name Description 7 TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put into power down mode. 6 PHDis When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon the presence of a 2100 Hz tone with periodic phase reversals. 5 NLPDis When high, the non-linear processor is disabled. When low, the non-linear processors function normally. Useful for G.165 conformance testing. 4 AutoTD When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones. When low, the echo canceller algorithm will remain operational regardless of the state of the 2100 Hz tone detectors. 3 NBDis When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled. 2 HPFDis When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low, the offset nulling filters are active and will remove DC offsets on PCM input signals. 1 MuteS When high, data on Sout is muted to quiet code. When low, Sout carries active code. 0 MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code. Echo Canceller A, Status Register Echo Canceller B, Status Register 7 6 5 4 3 2 1 0 res TD DTDet res res res TDG NB Read Address: Read Address: 02H + Base Address 22H + Base Address Reset Value: 00H. Bit Name Description 7 res Reserved bit. 6 TD Logic high indicates the presence of a 2100 Hz tone. 36 Zarlink Semiconductor Inc. MT93L04 Echo Canceller A, Status Register Echo Canceller B, Status Register 7 6 5 4 3 2 1 0 res TD DTDet res res res TDG NB Bit Name 5 DTDet 4 res Reserved bit. 3 res Reserved bit. 2 res Reserved bit. 1 TDG 0 NB Data Sheet Read Address: Read Address: 02H + Base Address 22H + Base Address Reset Value: 00H. Description Logic high indicates the presence of a double-talk condition. Tone detection status bit gated with the AutoTD bit. Logic high indicates that AutoTD has been enabled and the tone detector has detected the presence of a 2100 Hz tone. Logic high indicates the presence of a narrow-band signal on Rin. 37 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Flat Delay Register (FD) Echo Canceller B, Flat Delay Register (FD) 7 6 5 4 FD7 FD6 FD5 FD4 3 FD3 Read/Write Address: 04h + Base Address Read/Write Address: 24h + Base Address 2 1 0 FD2 FD1 FD0 Echo Canceller A, Decay Step Number Register (NS) Echo Canceller B, Decay Step Number Register (NS) 7 NS7 6 NS6 5 NS5 4 NS4 3 2 NS3 NS2 1 NS1 Read/Write Address: 07h + Base Address Read/Write Address: 27h + Base Address 0 0 6 0 5 0 4 3 0 0 2 SSC2 1 SSC1 Power Reset Value 00h NS0 Echo Canceller A, Decay Step Size Control Register (SSC) Echo Canceller B, Decay Step Size Control Register (SSC) 7 Power Reset Value 00h Read/Write Address: 06h + Base Address Read/Write Address: 26h + Base Address 0 SSC0 Power Reset Value 04h Note: Bits marked with “0” are reserved bits and should be written “0”. Amplitude of MU FIR Filter Length (512 or 1024 taps) 1.0 Step Size (SS) Flat Delay (FD7-0) 2-16 Time Number of Steps (NS7-0) The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one tap is equivalent to 125 µs (64 ms/512 taps). 38 Zarlink Semiconductor Inc. MT93L04 Data Sheet FD7-0 Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2-16). The delay is defined as FD7-0 x 8 taps. For example; if FD7-0 = 5, then MU=2-16 for the first 40 taps of the echo canceller FIR filter. The valid range of FD7-0 is: 0 ≤ FD7-0 ≤ 64 in normal mode and 0 ≤ FD7-0 ≤ 128 in extended-delay mode. The default value of FD7-0 is zero. SSC2-0 Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2SSC2-0. For example; If SSC2-0 = 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC2-0 is 04h.NS7-0Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a period of SS taps (see SSC2-0). The start of the exponential decay is defined as: Filter Length (512 or 1024) - [Decay Step Number (NS7-0) x Step Size (SS)] where SS = 4 x2SSC2-0. For example, if NS7-0=4 and SSC2-0=4, then the exponential decay start value is 512 - [NS7-0 x SS] = 512 - [4 x (4x24)] = 256 taps for a filter length of 512 taps. Echo Canceller A, Control Register A3 Echo Canceller B, Control Register B3 7 6 5 4 res res res res 3 2 1 Read/Write Address: 08H + Base Address Read/Write Address: 28H + Base Address 0 RingClr PathClr PathDet Reset Value: res 0AH. Bit Name Description 7-4 res 3 RingClr When high, the instability detector is activated. When low, the instability detector is disabled 2 PathClr When high, the current echo channel estimate will be cleared and the echo canceller will enter fast convergence mode upon detection of a path change. When low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. Note: this bit is ignored if PathDet is low. 1 PathDet When high, the path change detector is activated. When low, the path change detector is disabled. 0 res Reserved bits. Must always be set to zero for normal operation. Reserved bit. Must always be set to zero for normal operation. Echo Canceller A, Control Register A4 Echo Canceller B, Control Register B4 Read/Write Address: 09H + Base Address Read/Write Address: 29H + Base Address 7 6 5 4 3 2 1 0 0 SD2 SD1 SD0 res res res res Bit Name 7 0 Reset Value: Description Must be set to zero. 39 Zarlink Semiconductor Inc. 50H. MT93L04 Echo Canceller A, Control Register A4 Echo Canceller B, Control Register B4 Read/Write Address: 09H + Base Address Read/Write Address: 29H + Base Address 7 6 5 4 3 2 1 0 0 SD2 SD1 SD0 res res res res Bit Name 6-4 SupDec 3-0 res Data Sheet Reset Value: 50H. Description These three bits control how long the echo canceller remains in a fast convergence state following a path change, Reset or Bypass operation. A value of zero will keep the echo canceller in fast convergence indefinitely. Reserved bits. Must always be set to zero for normal operation. Echo Canceller A, Noise Scaling (NS) Echo Canceller B, Noise Scaling (NS) Read/Write Address: 0Ah + Base Address Read/Write Address: 2Ah + Base Address 7 6 5 4 3 2 1 0 NS7 NS6 NS5 NS4 NS3 NS2 NS1 NS0 Power Reset Value 74h If the comfort noise level estimator is unable to correctly match the background noise level, this register can be used to scale the comfort noise up or down. A neutral value of 80h will prevent any scaling. Values less than 80h will scale the comfort noise level down. Values greater than 80h will scale the comfort noise level up. Scaling is done linearly, so to scale the comfort noise down by 1 dB, a value of 72h would be used (-1 dB = 89% of original level, 0.89(dec) • 80h = 72h). Similarly, to scale up by 1 dB, use a value of 8Fh (1 dB = 112% of original level, 1.12(dec) • 80h = 8Fh). Echo Canceller A, Injection Rate (IR) Echo Canceller B, Injection Rate (IR) Read/Write Address: 0Bh + Base Address Read/Write Address: 2Bh + Base Address 7 6 5 4 3 2 1 0 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 Power Reset Value 0Ch The NLP ramps-in comfort noise during the initial background noise estimation stage. This register provides control over the ramp-in speed. Higher values will increase the ramp-in speed. 40 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Rin Peak Detect Register 2 (RP) Echo Canceller B, Rin Peak Detect Register 2 (RP) 7 RP15 6 RP14 5 RP13 Read Address: 0Dh + Base Address Read Address: 2Dh + Base Address 4 3 2 1 0 RP12 RP11 RP10 RP9 RP8 Echo Canceller A, Rin Peak Detect Register 1 (RP) Echo Canceller B, Rin Peak Detect Register 1 (RP) 7 6 RP7 RP6 5 4 3 RP5 RP4 RP3 2 RP2 Power Reset Value N/A Read Address: 0Ch + Base Address Read Address: 2Ch + Base Address 1 0 RP1 RP0 Power Reset Value N/A These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. 41 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Sin Peak Detect Register 2 (SP) Echo Canceller B, Sin Peak Detect Register 2 (SP) Read Address: 0Fh + Base Address Read Address: 2Fh + Base Address 7 6 5 4 3 2 1 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 Echo Canceller A, Sin Peak Detect Register 1 (SP) Echo Canceller B, Sin Peak Detect Register 1 (SP) 7 6 SP7 SP6 5 SP5 4 SP4 3 SP3 2 SP2 Power Reset Value N/A Read Address: 0Eh + Base Address Read Address: 2Eh + Base Address 1 0 SP1 SP0 Power Reset Value N/A These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 Main Control Register 12 Main Control Register 13 Main Control Register 14 Main Control Register 15 (EC group 1) (EC group 2) (EC group 3) (EC group 4) (EC group 5) (EC group 6) (EC group 7) (EC group 8) (EC group 9) (EC group 10) (EC group 11) (EC group 12) (EC group 13) (EC group 14) (EC group 15) Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: Read/Write Address: 42 Zarlink Semiconductor Inc. 401H 402H 403H 404H 405H 406H 407H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH MT93L04 Data Sheet Echo Canceller A, Error Peak Detect Register 2 (EP) Echo Canceller B, Error Peak Detect Register 2 (EP) 7 6 EP15 5 EP14 EP13 Read Address: 11h + Base Address Read Address: 31h + Base Address 4 3 2 1 0 EP12 EP11 EP10 EP9 EP8 Echo Canceller A, Error Peak Detect Register 1 (EP) Echo Canceller B, Error Peak Detect Register 1 (EP) 7 6 EP7 EP6 5 4 EP5 3 2 EP3 EP4 EP2 Power Reset Value N/A Read Address: 10h + Base Address Read Address: 30h + Base Address 1 0 EP1 EP0 Power Reset Value N/A These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in Register 1. Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address: 35h + Base Address 7 DTDT15 6 5 DTDT14 DTDT13 4 3 2 DTDT12 DTDT11 1 DTDT10 DTDT9 Power Reset Value 48h 0 DTDT8 (DTDT) Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address 7 DTDT7 6 DTDT6 5 DTDT5 4 DTDT4 3 2 DTDT3 1 DTDT2 DTDT1 0 DTDT0 (DTDT) Power Reset Value 00h This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s complement linear value defaults to 4800h= 0.5625 or -5 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. 43 Zarlink Semiconductor Inc. MT93L04 Data Sheet Echo Canceller A, Non-Linear Processor Threshold Register 2 Read/Write Address: 19h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 2 Read/Write Address: 39h + Base Address Power Reset Value 0Bh 7 6 5 4 3 2 1 0 NLP15 NLP14 NLP13 NLP12 NLP11 NLP10 NLP9 NLP8 (NLPTHR) Echo Canceller A, Non-Linear Processor Threshold Register 1 Read/Write Address: 18h + Base Address Echo Canceller B, Non-Linear Processor Threshold Register 1 Read/Write Address: 38h + Base Address 7 6 5 4 3 2 1 0 NLP7 NLP6 NLP5 NLP4 NLP3 NLP2 NLP1 NLP0 (NLPTHR) Power Reset Value 60h This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s complement linear value defaults to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low byte is in Register 1. Echo Canceller A, Adaptation Step Size (MU) Register 2 Echo Canceller B, Adaptation Step Size (MU) Register 2 Read/Write Address: 1Bh + Base Address Read/Write Address: 3Bh + Base Address 7 6 5 4 3 2 1 0 MU15 MU14 MU13 MU12 MU11 MU10 MU9 MU8 Echo Canceller A, Adaptation Step Size (MU) Register 1 Echo Canceller B, Adaptation Step Size (MU) Register 1 7 6 MU7 MU6 5 4 3 2 MU5 MU4 MU3 MU2 Power Reset Value 40h (MU) Read/Write Address: 1Ah + Base Address Read/Write Address: 3Ah + Base Address 1 0 MU1 MU0 Power Reset Value 00h (MU) This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0 The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1. Main Control Register 0 7 6 5 4 WR_all ODE MIRQ MTDBI Bit Name 7 WR_all 3 (EC group 0) 2 MTDAI Format Read/Write Address: 400H 1 0 LAW PWUP Reset Value: 00H. Description Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000h to 0003Fh which is Group 0 address mapping. Useful to initialize the 16 Groups of Echo Cancellers as per Group 0. When low, address mapping is per Figure 8. Note: Only the Main Control Register 0 has the WR_all bit. 44 Zarlink Semiconductor Inc. MT93L04 Main Control Register 0 7 6 5 4 WR_all ODE MIRQ MTDBI 3 (EC group 0) 2 MTDAI Format Data Sheet Read/Write Address: 400H 1 0 LAW PWUP Reset Value: 00H. Bit Name Description 6 ODE Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE bit and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main Control Register 0 has the ODE bit. 5 MIRQ Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone Detectors operate as specified in their Echo Canceller B, Control Register 2. When low, the Tone Detectors Interrupts are active. Note: Only the Main Control Register 0 has the MIRQ bit. 4 MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. 3 MTDAI Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. 2 Format ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-magnitude PCM code. 1 LAW A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-Law companded PCM code. 0 PWUP Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo canceller A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. 45 Zarlink Semiconductor Inc. MT93L04 Data Sheet Bit Name Description 7-5 unused Unused Bits. 4 MTDBI Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2. When low, the Tone Detector B Interrupt is active. 3 MTDAI Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2. When low, the Tone Detector A Interrupt is active. 2 Format ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711) PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM code. 1 LAW A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, select m-Law companded PCM code. 0 PWUP Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the echo cancellers A and B execute their initialization routine which presets their registers, Base Address+00H to Base Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. Interrupt FIFO Register 7 6 5 4 3 2 1 0 IRQ 0 0 I4 I3 I2 I1 I0 Bit Name 7 IRQ 6:5 0 Read Address: 410H (Read only) Reset Value: 00H. Description Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that no interrupt is pending and the FIFO is empty. Unused bits. Always zero 46 Zarlink Semiconductor Inc. MT93L04 Interrupt FIFO Register 7 6 5 4 3 2 1 0 IRQ 0 0 I4 I3 I2 I1 I0 Bit Name 4:0 I<4:0> Data Sheet Read Address: 410H (Read only) Reset Value: 00H. Description I<4:0> binary code indicates the channel number at which a Tone Detector state change has occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated. Test Register Read/Write Address: 411H 7 6 5 4 3 2 1 0 res res res res res res res Tirq Reset Value: 00H. Bit Name Description 7:1 res Reserved bits. Must always be set to zero for normal operation. 0 Tirq Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high, any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its corresponding channel number will be available from the Interrupt FIFO Register. When low, normal operation is selected. Absolute Maximum Ratings* Parameter Symbol Min. Max. Units 1 I/O Supply Voltage (VDD1) VDD1 -0.3 5.0 V 2 Core Supply Voltage (VDD2) VDD2 -0.3 2.5 V 3 Input on any I/O pins (other than supply pins) VI3 VSS - 0.3 VDD1+0.5 V 4 Input on any 5 V Tolerant I/O pins VI5 VSS - 0.3 5.5 V 5 Continuous Current at digital outputs Io 20 mA 6 Package power dissipation PD 2.0 W 7 Storage temperature TS 150 °C -55 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. 47 Zarlink Semiconductor Inc. MT93L04 Data Sheet Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units +85 °C Test Conditions 1 Operating Temperature TOP -40 2 I/O Supply Voltage VDD1 3.0 3.3 3.6 V Device I/O voltage 3 Core Supply Voltage VDD2 1.6 1.8 1.9 V Device core voltage 4 Input High Voltage on 3.3 V tolerant I/O VIH3 0.7VDD1 VDD1 V 5 Input High Voltage on 5 V tolerant I/O VIH5 0.7VDD1 5.5 V 6 Input Low Voltage VIL 0.3VDD1 V ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 4 5 7 8 9 10 Test Conditions 250 µA RESET = 0 32 channels of single device are active IDD_CORE 65 mA 32 channels of single device are active Total Power Consumption for all 4 devices PC 600 mW All devices and all 128 channels are active Input High Voltage VIH Input Low Voltage VIL Input Pin Capacitance O U T P U T S Units mA Input Leakage Input Leakage on Pullup Input Leakage on Pulldown 6 I Max. 10 IDD_CORE (single device) (VDD2 =1.8V)*** 3 Ty.p‡ DD_IO IDD_IO (VDD1=3.3V)*** (single device) I N P U T S Min. I CC Static Supply Current*** 1 2 Sym. 0.7VDD1 V 0.3VDD1 IIH/IIL ILU ILD -30 30 CI 3 Output High Voltage VOH Output Low Voltage VOL High Impedance Leakage IOZ Output Pin Capacitance CO µA µA µA 10 0.8VDD1 5 V VIN=VSS to VDD1 or 5.5V VIN=VSS VIN=VDD1 See Note 1 pF V IOH = 10 mA 0.4 V IOL = 10 mA 10 µA VIN=VSS to 5.5V 10 pF † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD1=3.3 V and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN). The *** specifications are for 1 MT93L00 device of the Multi-chip module. 48 Zarlink Semiconductor Inc. MT93L04 Data Sheet AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics Sym. Level Units 1 CMOS Threshold VTT 0.5VDD1 V 2 CMOS Rise/Fall Threshold Voltage High VHM 0.7VDD1 V 3 CMOS Rise/Fall Threshold Voltage Low VLM 0.3VDD1 V Conditions † Characteristics are over recommended operating conditions unless otherwise stated i AC Electrical Characteristics† - Frame Pulse and C4i Characteristic Sym. Min. Typ.‡ Max. Units 2* tcP-20 ns 1 Frame pulse width (ST-BUS, GCI) tFPW 20 2 Frame Pulse Setup time before C4i falling (ST-BUS or GCI) tFPS 10 122 150 ns 3 Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) tFPH 10 122 150 ns 4 C4i Period tCP 190 244.1 300 ns 5 C4i Pulse Width High tCH 85 150 ns 6 C4i Pulse Width Low tCL 85 150 ns 7 C4i Rise/Fall Time tr, tf 10 ns Notes † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD1=3.3V and for design aid only: not guaranteed and not subject to production testing AC Electrical Characteristics† - Serial Streams for ST-BUS and GCI Backplanes Characteristic Sym. Min. Typ.‡ Max. Units Test Conditions 1 Rin/Sin Set-up Time tSIS 10 ns 2 Rin/Sin Hold Time tSIH 10 ns 3 Rout/Sout Delay - Active to Active tSOD 60 ns CL=150pF 4 Output Data Enable (ODE) Delay tODE 30 ns CL=150pF, RL=1K See Note 1 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing * Note1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 49 Zarlink Semiconductor Inc. MT93L04 Data Sheet tFPW F0i VTT tFPS tCP tFPH tCH tCL tr VHM VTT VLM C4i tSOD Rout/Sout Bit 0, Channel 31 tf Bit 7, Channel 0 tSIS Rin/Sin Bit 6, Channel 0 tSIH Bit 7, Channel 0 Bit 0, Channel 31 VTT Bit 5, Channel 0 Bit 6, Channel 0 VTT Bit 5, Channel 0 Figure 9 - ST-BUS Timing at 2.048 Mb/s tFPW F0i VTT tFPS tCP tFPH tCH tCL tr VHM VTT VLM C4i tSOD Sout/Rout Bit 7, Channel 31) tf Bit 0, Channel 0 tSIS Sin/Rin Bit 1, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0 Figure 10 - GCI Interface Timing at 2.048 Mb/s VTT ODE tODE Sout/Rout VTT tSIH Bit 0, Channel 0 Bit 7, Channel 31) Bit 2, Channel 0 HiZ tODE Valid Data HiZ VTT Figure 11 - Output Driver Enable (ODE) 50 Zarlink Semiconductor Inc. VTT MT93L04 Data Sheet AC Electrical Characteristics† - Master Clock - Voltages are with respect to ground (VSS). unless otherwise stated. Sym. Min. Typ.‡ Max. Units Master Clock Frequency, - Fsel = 0 - Fsel = 1 fMCF0 fMCF1 19.0 9.5 20.0 10.0 21.0 10.5 MHz MHz 2 Master Clock Low tMCL 20 ns 3 Master Clock High tMCH 20 ns Characteristic 1 Notes † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD1=3.3V and for design aid only: not guaranteed and not subject to production testing tMCH VTT MCLK tMCL Figure 12 - Master Clock 51 Zarlink Semiconductor Inc. MT93L04 Data Sheet AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode Characteristics Sym. Min. Typ.‡ Max. Units 1 CS setup from DS falling tCSS 0 ns 2 R/W setup from DS falling tRWS 0 ns 3 Address setup from DS falling tADS 0 ns 4 CS hold after DS rising tCSH 0 ns 5 R/W hold after DS rising tRWH 0 ns 6 Address hold after DS rising tADH 0 ns 7 Data delay on read tDDR 8 Data hold on read tDHR 3 9 Data setup on write tDSW 0 ns 10 Data hold on write tDHW 0 ns 11 Acknowledgment delay tAKD 12 Acknowledgment hold time tAKH 13 IRQ delay tIRD Test Conditions 79 ns CL=150pF, RL=1K 15 ns CL=150pF, RL=1K See Note 1 80 ns CL=150pF, RL=1K 0 8 ns CL=150pF, RL=1K, See Note 1 20 65 ns CL=150pF, RL=1K, See Note 1 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD1=3.3 V and for design aid only: not guaranteed and not subject to production testing *Note 1:High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 52 Zarlink Semiconductor Inc. MT93L04 DS Data Sheet tCSS tCSH VTT CS tRWH tRWS VTT R/W tADS tADH VTT VALID ADDRESS A0-A10 tDDR D0-D7 READ VTT tDHR VTT VALID READ DATA tDSW tDHW D0-D7 WRITE VTT VALID WRITE DATA tAKD tAKH VTT DTA tIRD VTT IRQ Figure 13 - Motorola Non-Multiplexed Bus Timing 53 Zarlink Semiconductor Inc. MT93L04 Data Sheet Pin #1 Corner 1 D F H K M P T V 3 4 5 6 8 7 9 14 16 10 12 18 20 15 11 13 17 19 Ø 1.00 (3X) REF. A C E G 24.00 B 2 J L N R U W Y 4.00" 45’ (4X) 24.00 REF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.27 A B C D E F G H J K L M N P R T U V W Y 24.13 27.00 ± 0.20 0.60 ~ 0.90 (365X) B 1.27 24.13 A 1.17 27.00 ± 0.20 30 ° 0.15 (0.56) C Seating Plane 0.50 ~ 0.70 MT93L04AG 365 -Ball BGA 54 Zarlink Semiconductor Inc. 2.33 ± 0.13 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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