ETC MX10C8050 Single-chip 8-bit microcontroller Datasheet

ADVANCED INFORMATION
MX10C805X
SINGLE-CHIP 8-BIT MICROCONTROLLER
FEATURE
•
•
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•
•
•
•
•
•
High performance CMOS ROM CPU
Operation Voltage 5V
Up to 40MHz operation (3.5MHz to 40MHz)
Three 16-bit timer/counters
256 Bytes of on-chip data RAM
4/8/16/32/64 Kbytes on-chip Program memory
32 Programmable I/O lines
On-chip Watch-Dog-Timer (WDT)
6 interrupt Sources
•
•
•
•
•
•
•
•
ROM Code protection
Two priority levels
Power saving Idle and power down modes
64 K external program memory space
64 K external data memory space
Available in PLCC, PQFP, and PDIP package
Four 8-bit I/O ports
Full-duplex enhanced UART compatible with the standard 80C51 and the 80C52
• Extended Temperature Range (-40°C to +85° C)
GENERAL DESCRIPTION
The single-chip 8-bit microcontroller is manufactured in
MXIC's advanced CMOS process. This device uses the
same powerful instruction set, has the same architecture, and is pin-to-pin compatible with the existing 80C51.
The added features make it an even more powerful
microcontroller for applications that require clock output, and up/down counting capabilities such as motor
control. It also has a more versatile serial channel that
facilitates multi-processor communications.
40
39
40 PDIP
P0.4
P1.6
P0.5
P1.7
P0.6
RST
P0.7
EA
P3.0
N.C.
MX10C805X
12
34
N.C.
P3.1
ALE
P3.2
PSEN
P3.3
P2.7
P2.6
P3.4
29
28
P2.3
P2.2
P2.1
P2.0
N.C.
VSS
XTAL1
XTAL2
P3.7
23
P2.5
P2.4
17
18
P3.6
P3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA
ALE
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P1.4
P1.3
P1.2
P1.1
P1.0
N.C.
VCC
P0.0
P0.1
P0.2
P0.3
44 PQFP
(T2) P1.0
(T2EX) P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
(RXD) P3.0
(TXD)P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
VSS
MX10C805X
P0.3
P0.2
44
P0.1
1
P0.0
P1.0
P1.1
6
VCC
7
N.C.
P1.5
P1.2
44 PLCC
P1.3
P1.4
PIN CONFIGURATIONS
34
33
44
1
MX10C805X
11
12
23
22
P0.4
P0.5
P0.6
P0.7
EA
N.C.
ALE
PSEN
P2.7
P2.6
P2.5
P3.6
P3.7
XTAL2
XTAL1
VSS
N.C.
P2.0
P2.1
P2.2
P2.3
P2.4
P1.5
P1.6
P1.7
RST
P3.0
N.C.
P3.1
P3.2
P3.3
P3.4
P3.5
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REV. 0.3, APR. 09, 1999
1
MX10C805X
BLOCK DIAGRAM
P0.0-P0.7
P2.0-P2.7
PORT 0
PORT 2
DRIVERS
Vcc
Vss
RAM ADDR.
REGISTER
DRIVERS
PORT 0
LATCH
RAM
PORT 2
LATCH
STACK
POINTER
ACC
TMP2
ROM
T3
WATCHDOG
TIMER
TMP1
BUFFER
B
REGISTER
ALU
PC
INCREMENTER
T0/T1/T2
SFRs
TIMERS
ALE
EA
RST
TIMING
AND
CONTROL
DPTR
PORT 1
LATCH
OSC.
XTAL1
PROGRAM
COUNTER
INSTRUCTION
REGISTER
PSW
PSEN
PROGRAM
ADDR.
REGISTER
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0-P1.7
P3.0-P3.7
XTAL2
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REV. 0.3, APR. 09, 1999
2
MX10C805X
In additional, Port 1 serves the functions of the following
special features of the MX10C805X :
PROCESS INFORMATION
This device is manufactured on a MXIC CMOS process.
Port Pin
P1.0
PACKAGES
MX10C805
1
P
C
P1.1
Temperature
C=0°C to 70°C
I=-40°C to 85°C
Alternate Function
T2 (External Count Input to Timer/
Counter 2), Clock-Out
T2EX (Timer/Counter 2 Capture/Reload
Trigger and Direction Control)
Port 2 : Port 2 is an 8-bit bidirectional I/O port with internal pullups. The port 2 output buffers can drive LS TTL
inputs. Port 2 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
Package
P=PDIP
Q=PLCC
F=PQFP
ROM Size
0=64K Bytes
1=4K Bytes
2=8K Bytes
4=16K Bytes
8=32K Bytes
Port 2 emits the high-order address byte during fetches
from external Program Memory and during accesses to
external Data Memory that use 16-bit addresses (MOVX
@DPTR). In this application it uses strong internal
pullups when emitting 1's. During accesses to external
Data Memory that use 8-bit addresses (MOVX @Ri),
Port 2 emits the contents of the P2 Special Function
Register.
PIN DESCRIPTIONS
VCC : Supply voltage.
Port 3 : Port 3 is an 8-bit bidirectional I/O port with internal pullups. The port 3 output buffers can drive LS TTL
inputs. Port 3 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
VSS : Circuit ground.
Port 0 : Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance
inputs.
Port 3 also serves the function of various special features of the 8051 Family, as listed below :
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1's, and can source and sink serveral LS
TTL inputs.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pullups. The port 1 output buffers can drive LS TTL
inputs. Port 1 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, on the data sheet)
because of the internal pullups.
P/N:PM0591
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write sttobe)
RD (external data memory read strobe)
REV. 0.3, APR. 09, 1999
3
MX10C805X
OSCILLATOR CHARACTERISTICS
RST : Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
The port pins will be driven to their reset condition when
a minimum VIHI voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a capacitor connected
to VCC.
XTAL1 and XTAL2 are the input and output, respectively,
of a inverting amplifier which can be configured for use
as an on-chip oscillator, as shown in Figure 3. Either a
quartz crystal or ceramic resonator may be used.
C2
ALE : Address Latch Enable output pulse for latching
the low byte of the address during accesses to external
memory.
XTAL2
C1
XTAL1
In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that
one ALE pulse is skipped during each access to external Data Memory.
VSS
C1, C2 = 30 pF is equal to or less than 10 pF for Crystal
For Ceramic Resonators,contact resonator manufacture.
Figure 3. Oscillator Connections
If desired, ALE operation can be disabled by setting bit
5 of SFR location 87H (PCON). With this bit set, the pin
is weakly pulled high. However, the ALE disable feature
will be suspended during a MOVX or MOVC instruction,
idle mode, power down mode. The ALE disable feature
will be terminated by reset. When the ALE disable feature is suspended or terminated, the ALE pin will no
longer be pulled up weakly. Setting the ALE-disable bit
has no affect if the micrcontroller is in external execution mode.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 floats, as shown in Figure 4. There are no requirememts on the duty cycle of
the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified
on the data sheet must be observed.
Throughout the remainder of this data sheet, ALE will
refer to the signal coming out of the ALE pin, and the pin
will be referred to as the ALE pin.
An external oscillator may encounter as much as a 100
pF load at XTAL1 when it starts up. This is due to interaction between the amplifer and its feedback capacitance. Once the external signal meets the VIL and VIH
specifications the capacitance will not exceed 20 pF.
PSEN : Program Store Enable is the read strobe to external Program Memory.
When the MX10C805X is executing code from external
Program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data memory.
EA/VPP : Extrernal Access enable. EA must be strapped
to VSS in order to enable the twiceto fetch code from
external Program Memory locations 0000H to 0FFFFH.
EA will be internally latched on reset.
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
VSS
EA should be strapped to VCC for internal program executions.
Figure 4. External Clock Drive Configuration
XTAL1 : Input to the inverting oscillator amplifier.
XTAL2 : Output from the inverting oscillator amplifier.
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4
MX10C805X
IDLE MODE
ABSOLUTE MAXIMUM RATING*
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption
is reduced. The Special Function Registers and the
onboard RAM retain their values during Idle, but the processor stops executing instructions. Idle Mode will be
exited if the chip is reset or if an enabled interrupt occurs.
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Other Pin to VSS
IOL Per I/O Pin
Power Dissipation
-40°C to +85°C
-65°C to +150°C
-0.5V to +6.5V
15mA
1.5W
(Based on PACKAGE heat transfer limitations, not device consumption)
Table 2. Status of the External Pins during Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
POWER DOWN MODE
To save even more power, a Power Down mode can be
invoked by software. If this mode, the oscillator is stopped
and the instruction that invoked Power Down is the last
instruction executed. The on-chip RAM and Special
Function Registers retain their values until the Power
Down mode is terminated.
To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level, and must be held
active long enough for the oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin
low restarts the oscillator but bringing the pin back high
completes the exit. Once the interrupt is serviced, the
next instruction to be executed after RETI will be the
one following the instruction that put the device into Power
Down.
On the MX10C805X either a hardware reset or an external interrupt can cause an exit from Power Down. Reset redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the SFRs
and on-chip RAM to retain their values.
OPERATING CONDITIONS
Symbol
TA
VCC
fOSC
Description
Ambient Temperature Under Bias
Commerical
Industrial
Oscillator Frequency
P/N:PM0591
Min
Max
Units
0
-40
4.5
3.5
+70
+85
5.5
40
°C
°C
V
MHz
REV. 0.3, APR. 09, 1999
5
MX10C805X
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
(Note 4)
VIL
Input Low Voltage
-0.5
0.2 VCC-0.1
V
VIL1
Input Low Voltage EA
0
0.2 VCC-0.3
V
Input High Voltage
0.2 VCC+0.9
VCC+0.5
V
0.7 VCC
VCC+0.5
V
0.4
V
IOL=1.6 mA (Note 1)
0.4
V
IOL=3.2 mA (Note 1)
VIH
(Except XTAL1, RST)
VIH1
Input High Voltage
(XTAL1, RST)
VOL
Output Low Voltage (Note 5)
(Ports 1, 2, and 3)
VOL1
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
VOH
VOH1
Output High Voltage
0.9 VDD
V
IOH=-10 uA
(Port 1, 2 and 3, ALE, PSEN)
0.75 VDD
V
IOH=-30 uA
0.5 VDD
V
IOH=-60uA
Output High Voltage
0.9 VDD
V
IOH=-80 uA
(Port 0 in External Bus Mode)
IIL
0.75 VDD
V
IOH=-300 uA
0.5 VDD
V
IOH=-800 uA
-50
uA
VIN=0.4V
Logical 0 Input Current
(Ports 1, 2 and 3)
ILI
Input leakage Current (Port 0)
±10
uA
VIN=VIL or VIH
ITL
Logical 1 to 0 Transition Current
-750
uA
VIN=2V
150
K ohm
(Ports 1, 2 and 3)
Industrial
PRST
RST Pulldown Resistor
CIO
Pin Capacitance
ICC
Power Supply Current:
15
10
pF
@1 MHz, 25°C
(Note 3)
Active Mode at 40 MHz
Idle Mode at 40 MHz(70°C 5.5V)
Power Down Mode
2
60
mA
28
mA
10
uA
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and Ports 1, 2 and 3. The
noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications
where capacitive loading exceeds 100 pF, the noise pulses on these signlas may exceed 0.8V. It may be desirable to qualify ALE or other
signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are
stabilizing.
3. Minimum VCC for Power Down is 2V.
4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
Maximum IOL per 8-bit port:
Port 0:
26mA
Ports 1, 2 and 3:
15mA
Maximum total IOL for all output pins:
71mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
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6
MX10C805X
60.0
MAX
ACTIVE MODE
50.0
40.0
ICC (mA)
TYP
ACTIVE MODE
30.0
20.0
MAX
IDLE MODE
MAX
IDLE MODE
10.0
0.0
0.0
8.0
4.0
12.0
16.0
20.0
24.0
28.0
32.0
36.0
Freq at XTAL1 (MHz)
NOTE:
ICC Max at 33 MHz is at 5V is + 10% VCC, while
ICC Max at 24 MHz and below is at 5V + 20% VCC
Figure 5. 80C52/54/58 ICC vs Frequwncy
VCC
VCC
VCC
ICC
VCC
VCC
VCC
VCC
P0
P0
EA
EA
RST
RST
MX10C805X
(NC)
CLOCK
SIGNAL
ICC
MX10C805X
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
XTAL2
XTAL1
VSS
All other pins disconnected
TCLCH = TCHCL = 5ns
All other pins disconnected
TCLCH = TCHCL = 5ns
Figure 7. ICC Test Condition Idle Mode
Figure 6. ICC Test Condition, Active Mode
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7
MX10C805X
VCC
ICC
VCC
VCC
P0
EA
RST
MX10C805X
(NC)
XTAL2
XTAL1
VSS
All other pins disconnected
Figure 8. ICC Test Condition, Power Down Mode
VCC=2.0V to 6.0V
VCC-0.5
0.45V
0.7 VCC
0.2 VCC-0.1
TCHCL
TCLCX
TCHCX
TCLCH
TCLCL
Figure 9. Clock Signal Waveform for ICC Tests in Active and Idle Modes.
TCLCH = TCHCL = 5 ns
EXPLANATION OF THE AC SYMBOLS
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of
a signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
L: Logic level LOW, or ALE
P: PSEN
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to PSEN Low
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8
MX10C805X
AC CHARACTERISTICS
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All
Other Outputs = 80 pF)
tCK min. = 1/f max. (maximum operating frequency); tCK=clock period
SYMBOL
PARAMETER
EXTERNAL PROGRAM MEMORY
TLHLL
ALE PULSE DURATION
TAVLL
ADDRESS SET-UP TIME TO ALE
TLLAX
ADDRESS HOLD TIME AFTER ALE
TLLIV
TIME FROM ALE TO VALID INSTRUCTION INPUT
TLLPL
TIME FROM ALE TO CONTROL PULSE PSEN
TPLPH
CONTROL PULSE DURATION PSEN
TPLIV
TIME FROM PSEN TO VALID INSTRUCTION INPUT
TPXIX
INPUT INSTRUCTION HOLD TIME AFTER PSEN
TPXIZ
INPUT INSTRUCTION FLOAT DELAY AFTER PSEN
TAVIV
ADDRESS TO VALID INSTRUCTION INPUT
TPLAZ
TO PSEN ADDRESS FLOAT TIME
EXTERNAL DATA MEMORY
TLHLL
ALE PULSE DURATION
TAVLL
ADDRESS SET-UP TIME TO ALE
TLLAX
ADDRESS HOLD TIME AFTER ALE
TRLRH
RD PULSE DURATION
TWLWH
WR PULSE DURATION
TRLDV
RD TO VALID DATA INPUT
TRHDX
DATA HOLD TIME AFTER RD
TRHDZ
DATA FLOAT DELAY AFTER RD
TLLDV
TIME FROM ALE TO VALID DATA INPUT
TAVDV
ADDRESS TO VALID INPUT
TLLWL
TIME FROM ALE TO RD OR WR
TAVWL
TIME FROM ADDRESS TO RD OR WR
TWHLH
TIME FROM RD OR WR HIGH TO ALE HIGH
TQVWX
DATA VALID TO WR TRANSITION
TQVWH
DATA SET-UP TIME BEFORE WR
TWHQX
DATA HOLD TIME AFTER WR
TRLAZ
ADDRESS FLOAT DELAY AFTER RD
33 MHz
MIN
MAX
UNIT
20
17
10
17
70
0
-
55
12
20
95
10
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
20
17
10
80
80
0
32
40
45
10
10
125
10
-
60
90
105
140
55
0
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NS
NOTE:
1. The maximun operating frequency is limited to 40 MHz and the minimum to 3.5 MHz.
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9
MX10C805X
External clock drive XTAL
SYMBOL
PARAMETER
fCLK
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
tCY
clock frequency
clock period
HIGH time
LOW time
RISE time
FALL time
cycle time (tCY = 12 tCK)
VARIABLE CLOCK
MIN
MAX
1.2
16 (tbf.)
63
833
20
tCK-tCLCX
20
tCK-tCHCX
20
20
0.75
10
UNIT
MHz
ns
ns
ns
ns
ns
ms
SERIAL PORT CHARACTERISTICS
Serial Port Timing : Shift Register Mode
VDD = 5V±10%; VSS = 0V; Tamb=0°C; Load Capacitance = 80 pF
SYMBOL
PARAMETER
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
33 MHz OSCILLATOR
MIN
MAX
360
167
5
0
167
UNIT
ns
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
VCC-0.5
0.45V
0.7 VCC
0.2 VCC-0.1
TCHCX
TCLCX
TCHCL
TCLCH
TCLCL
AC TESTING INPUT, OUTPUT WAVEFORMS
VCC-0.5
0.45V
FLOAT WAVEFORM
VLOAD+0.1V
VLOAD
VLOAD-0.1V
0.2 VCC+0.9
0.2 VCC-0.1
AC Inputs during testing are driven at VCC-0.5V for a
Logic "1" 0.45V for a Logic "0". Timing measurements
are made at VIH min for a Logic "1" and VIL max for a
Logic "0".
VOH-0.1V
TIMING REFERENCE
POINTS
VOL+0.1V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100mV
change form the loaded VOH/VOL level occurs. IOL/IOH = + 20 mA
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MX10C805X
EXTERNAL PROGRAM MEMORY READ CYCLE
TLHLL
ALE
TLLPL
TPLIP
TLHIV
TAVLL
TPLIV
PSEN
TPXIZ
TPLAZ
TPXIX
TLLAX
PORT 0
A0 - A7
INSTR IN
A0 - A7
TAVIV
A8 - A15
PORT 2
A8 - A15
EXTERNAL DATA MEMORY READ CYCLE
ALE
TLHLL
TWHLH
TLLDL
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVLL
TLLAX
TRLDV
TRHDX
TRLIZ
PORT 0
A0-A7 FROM RI OR DPL
DATA IN
A0-A7 FROM
PCL
INSTR. IN
TAVWL
TAVDV
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
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A8-A15 FROM PCH
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11
MX10C805X
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
TLHLL
TWHLH
PSEN
TLLWL
TWLWH
WR
TAVLL
TWHQX
TQVWX
TLLAX
TQVWH
PORT 0
A0-A7 FROM
PCL
DATA OUT
A0-A7 FROM RI OR DPL
INSTR. IN
TAVWL
PORT 2
A8-A15 FROM PCH
P2.0-P2.7 OR A8-A15 FROM DPH
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
2
1
0
5
4
3
8
7
6
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
1
0
3
2
4
5
6
7
VALID
VALID
WRITE TO SBUF
TXHDV
INPUT DATA
VALID
TXHDX
VALID
VALID
VALID
VALID
VALID
CLEAR RI
P/N:PM0591
REV. 0.3, APR. 09, 1999
12
MX10C805X
REVISION HISTORY
REVISION
0.3
DESCRIPTION
Modify Block Diagram
PAGE
P2
P/N:PM0591
DATE
APR/09/1999
REV. 0.3, APR. 09, 1999
13
MX10C805X
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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TEL:+32-2-456-8020
FAX:+32-2-456-8021
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FAX:+65-348-8096
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TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
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TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
14
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