PHILIPS N74F573N Octal transparent latch 3-state Datasheet

INTEGRATED CIRCUITS
74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification
IC15 Data Handbook
1989 Oct 16
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
FEATURES
• 74F573 is broadside pinout version of 74F373
• 74F574 is broadside pinout version of 74F374
• Inputs and Outputs on opposite side of package allow easy
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
interface to Microprocessors
• Useful as an Input or Output port for Microprocessors
• 3-State Outputs for Bus interfacing
• Common Output Enable
• 74F563 and 74F564 are inverting version of 74F573 and 74F574
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
respectively
• 3-State Outputs glitch free during power-up and power-down
• These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F573
5.0ns
35mA
TYPE
TYPICAL fMAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F574
180MHz
50mA
ORDERING INFORMATION
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
20-Pin Plastic DIP
N74F573N, N74F574N
SOT146-1
20-Pin Plastic SOL
N74F573D, N74F574D
SOT163-1
N74F573DB
SOT339-1
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
20-Pin Plastic SSOP
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0 - D7
Data inputs
1.0/1.0
20µA/0.6mA
E (74F573)
Latch Enable input (active falling edge)
1.0/1.0
20µA/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20µA/0.6mA
CP (74F574)
Clock Pulse input (active rising edge)
1.0/1.0
20µA/0.6mA
150/40
3.0mA/24mA
Q0 - Q7
3-State outputs
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Oct 16
2
853-0083 97897
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
PIN CONFIGURATION – 74F573
PIN CONFIGURATION – 74F574
OE 1
20
VCC
OE 1
20
VCC
D0
2
19
Q0
D0
2
19
Q0
D1
3
18
Q1
D1
3
18
Q1
D2
4
17
Q2
D2
4
17
Q2
D3
5
16
Q3
D3
5
16
Q3
D4
6
15
Q4
D4
6
15
Q4
D5
7
14
Q5
D5
7
14
Q5
D6
8
13
Q6
D6
8
13
Q6
D7
9
12
Q7
D7
9
12
Q7
11
E
11
CP
GND 10
GND 10
SF01073
SF01074
LOGIC SYMBOL – 74F573
11
1
LOGIC SYMBOL – 74F574
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
E
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC) – 74F573
11
1
OE
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
SF01076
LOGIC SYMBOL (IEEE/IEC) – 74F574
1
EN1
11
EN2
EN1
C2
19
2
3
18
3
18
4
17
4
17
5
16
5
16
6
15
6
15
7
14
7
14
8
13
8
13
9
12
9
12
2
2D
1
SF01077
1989 Oct 16
CP
3
VCC=Pin 20
GND=Pin 10
SF01075
1
11
2
2D
1
19
SF01078
3
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
LOGIC DIAGRAM – 74F573
D0
D1
2
D2
3
D
E
E
OE
E
D4
5
D
D
Q
D3
4
Q
E
D
Q
D5
6
E
D
Q
D6
7
E
D
Q
D7
8
E
9
D
Q
E
D
Q
E
Q
11
1
19
VCC=Pin 20
GND=Pin 10
18
Q0
17
Q1
16
Q2
15
Q3
14
Q4
13
Q5
12
Q6
Q7
SF01079
FUNCTION TABLE – 74F573
INPUTS
H =
h =
L =
l =
NC=
X =
Z =
↓ =
E
Dn
INTERNAL
REGISTER
OUTPUTS
OE
L
L
H
H
L
H
L
H
L
H
Load and read register
L
L
↓
↓
l
h
L
H
L
H
Latch and read register
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
OPERATING MODES
Q0 – Q7
Hold
Disable outputs
High voltage level
High voltage level one setup time prior to the High-to-Low E transition
Low voltage level
Low voltage level one setup time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off” state
High-to-Low E transition
LOGIC DIAGRAM – 74F574
D0
D1
2
D
CP
CP
OE
D2
3
CP
Q
D4
5
D
D
Q
D3
4
CP
D
Q
D5
6
CP
D
Q
D6
7
CP
D
Q
D7
8
CP
9
D
Q
CP
D
Q
CP
Q
11
1
19
VCC=Pin 20
GND=Pin 10
Q0
18
Q1
17
16
Q2
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SF01080
1989 Oct 16
4
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
FUNCTION TABLE – 74F574
CP
Dn
INTERNAL
REGISTER
OUTPUTS
OE
INPUTS
L
L
↑
↑
l
h
L
H
L
H
L
↑
X
NC
NC
H =
h =
L =
l =
NC=
X =
Z =
↑ =
↑ =
OPERATING MODES
Q0 – Q7
H
↑
Dn
Dn
High voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
Not a Low-to-High clock transition
Z
Load and read register
Hold
Disable outputs
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
VCC
Supply voltage
–0.5 to +7.0
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5.0
mA
VOUT
Voltage applied to output in High output state
–0.5 to +VCC
V
IOUT
Current applied to output in Low output state
48
mA
Tamb
Operating free-air temperature range
0 to +70
°C
Tstg
Storage temperature
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
LIMITS
PARAMETER
MIN
NOM
MAX
5.0
5.5
UNIT
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–3
mA
IOL
Low-level output current
24
mA
Tamb
Operating free-air temperature range
70
°C
1989 Oct 16
0
5
V
V
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
TEST CONDITIONSNO TAG
PARAMETER
MIN
TYP
MAX
UNIT
NO TAG
VOH
O
VCC = MIN, VIL = MAX,
VIH = MIN, IOH = MAX
High level output voltage
High-level
VCC = MIN, VIL = MAX,
VIH = MIN, IOL = MAX
±10%VCC
2.4
±5%VCC
2.7
±10%VCC
V
3.4
V
0.35
0.50
V
0.35
0.50
V
–0.73
–1.2
V
100
µA
VOL
O
Low level output voltage
Low-level
VIK
Input clamp voltage
II
Input current at
maximum input voltage
VCC = MAX, VI = 7.0V
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
µA
IIL
Low-level input current
VCC = MAX, VI = 0.5V
–0.6
mA
IOZH
Off-state output current,
High-level voltage applied
VCC = MAX, VO = 2.7V
50
µA
IOZL
Off-state output current,
Low-level voltage applied
VCC = MAX, VO = 0.5V
–50
µA
IOS
Short-circuit output currentNO TAG
–150
mA
30
40
mA
35
50
mA
40
60
mA
45
65
mA
50
70
mA
VCC = MAX
ICCH
ICCL
ICC
Supply
current
((total))
74F573
VCC = MAX
ICCZ
ICCH
ICCL
±5%VCC
VCC = MIN, II = IIK
74F574
VCC = MAX
–60
ICCZ
55
85
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
1989 Oct 16
6
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
TEST
CONDITIONS
PARAMETER
Tamb= +25°C
VCC = +5V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5V ± 10%
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
Waveform
NO TAG
3.0
1.0
5.5
3.5
8.0
6.0
2.5
1.0
9.0
7.0
ns
tPLH
tPHL
Propagation delay
E to Qn
Waveform
NO TAG
4.5
3.0
8.5
5.0
11.5
7.0
4.0
2.5
12.5
8.0
ns
tPZH
tPZL
Output Enable time
to High or Low level
Waveform
NO TAG
Waveform
NO TAG
2.5
2.5
5.5
5.5
9.5
8.0
2.0
2.0
10.5
8.5
ns
tPHZ
tPLZ
Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
1.0
1.0
3.0
2.5
6.0
5.5
1.0
1.0
6.5
5.5
ns
fMAX
Maximum Clock frequency
Waveform
NO TAG
160
180
tPLH
tPHL
Propagation delay
CP to Qn
Waveform
NO TAG
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.0
8.0
ns
tPZH
tPZL
Output Enable time
to High or Low level
Waveform
NO TAG
Waveform
NO TAG
2.5
3.0
4.5
5.0
7.5
8.0
2.0
3.0
7.5
8.5
ns
tPHZ
tPLZ
Output Disable time
from High or Low level
Waveform
NO TAG
Waveform
NO TAG
1.0
1.0
3.0
2.5
5.5
5.5
1.0
1.0
6.0
6.0
ns
74F573
74F574
150
MHz
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
Tamb= +25°C
VCC = +5V
CL = 50pF, RL = 500Ω
TEST
CONDITIONS
PARAMETER
MIN
ts(H)
ts(L)
Setup time,
Dn to E
th(H)
th(L)
Hold time,
Dn to E
tw(H)
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
0.0
1.5
0.0
2.0
ns
Waveform 4
2.5
4.0
2.5
4.0
ns
E pulse width,
High
Waveform NO TAG
3.0
3.5
ns
ts(H)
ts(L)
Setup time,
Dn to CP
Waveform NO TAG
2.5
2.5
3.0
3.0
ns
th(H)
th(L)
Hold time,
Dn to CP
Waveform NO TAG
0
0
0
0
ns
tw(H)
tw(L)
CP Pulse width,
High or Low
Waveform NO TAG
3.0
3.5
3.0
4.0
ns
1989 Oct 16
74F573
74F574
7
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
AC WAVEFORMS
For all waveforms, VM = 1.5V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
E, CP
VM
VM
tW(H)
Dn
VM
VM
tW(L)
tPHL
VM
tPLH
tPHL
tPLH
Qn
VM
Qn
VM
VM
VM
SF01081
SF01082
Waveform 1. Propagation Delay, Clock and Enable Inputs
to Output, Enable, Clock Pulse Widths,
and Maximum Clock Frequency
Dn
VM
VM
VM
VM
ts(H)
th(H)
ts(L)
th(L)
CP
VM
Waveform 2. Propagation Delay for Data to Outputs
Dn
VM
VM
VM
ts(H)
ts(L)
th(H)
E
VM
VM
th(L)
VM
VM
SF00992
SF00191
Waveform 4. Data Setup and Hold Times
Waveform 3. Data Setup and Hold Times
OE
VM
tPZH
Qn
OE
VM
tPHZ
VM
tPZL
VOH -0.3V
Qn
VM
0V
tPLZ
VM
VOL +0.3V
SF00343
SF00344
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
1989 Oct 16
VM
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
8
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00777
1989 Oct 16
9
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
DIP20: plastic dual in-line package; 20 leads (300 mil)
1989 Oct 16
10
SOT146-1
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SO20: plastic small outline package; 20 leads; body width 7.5 mm
1989 Oct 16
11
SOT163-1
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
1989 Oct 16
12
SOT339-1
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
NOTES
1989 Oct 16
13
Philips Semiconductors
Product specification
Latch/flip-flop
74F573, 74F574
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
yyyy mmm dd
14
Date of release: 10-98
9397-750-05141
Similar pages