PHILIPS N74F842N Bus interface latch Datasheet

INTEGRATED CIRCUITS
74F841/842/843/845/846
Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
IC15 Data Handbook
1999 Jun 23
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State)
74F843 9-bit bus interface latch, non-inverting (3-State)
74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
DESCRIPTION
• High speed parallel latches
• Extra data width for wide address/data paths or buses carrying
The 74F841–74F846 bus interface latch series are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
parity
The 74F841–74F846 series are funcitonally an pin compatible to the
AMD AM29841–AM29846 series.
• High impedance NPN base input structure minimizes bus loading
• IIL is 20µA vs 1000A for AM29841 series
• Buffered control inputs to reduce AC effects
• Ideal where high speed, light loading, or increased fan-in are
The 74F841 consists of ten D-type latches with 3-State outputs. The
flip-flops appear transparent to the data when Latch Enable (LE) is
High. This allows asynchronous operation, as the output transition
follows the data in transition. On the LE High-to-Low transition, the
data that meets the setup and hold time is latched.
required as with MOS microprocessors
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• 48mA sink current
• Slim dual in-line 300 mil package
• Broadside pinout
• Pin-for-pin and function compatible with AMD AM29841-846
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
The 74F842 is the inverted output version of the 74F841.
The 74F843 consists of nine D-type latches with 3-State outputs. In
addition to the LE and OE pins, the 74F843 has a Master Reset
(MR) pin and Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When MR is Low, the
outputs are Low if OE is Low. When MR is High, data can be
entered into the latch. When PRE is Low, the outputs are High, if OE
is Low, PRE overrides MR.
series
The 74F845 consists of eight D-type latches with 3-State outputs. In
addition to the LE, OE, MR and PRE pins, the 74F845 has two
addtitional OE pins making a total of three Output Enables (OE0,
OE1, OE2) pins.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F841, 74F842
5.5ns
60mA
74F843, 74F845
5.5ns
75mA
The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user
control of the interface, e.g., CS, DMA, and RD/WR.
74F846
6.2ns
60mA
The 74F846 is the inverted output version of the 74F845.
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
PACKAGE DRAWING
NUMBER
24-pin plastic Slim DIP (300 mil)
N74F841N, N74F842N, N74F843N, N74F845N, N74F846N
SOT222-1
24-pin plastic SOL
N74F841D, N74F842D, N74F843D, N74F845D, N74F846D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Dn
Data inputs
1.0/0.033
20µA/20µA
LE
Latch Enable input
1.0/0.033
20µA/20µA
OE, OEn
Output Enable input (active Low)
1.0/0.033
20µA/20µA
MR
Master Reset input (active Low)
1.0/0.033
20µA/20µA
PRE
Preset input (active Low)
1.0/0.033
20µA/20µA
Qn
Data outputs
1200/80
24mA/48mA
Qn
Data outputs
1200/80
24mA/48mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1999 Jun 23
2
853–1208 21851
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F841
OE 1
PIN CONFIGURATION for 74F842
24 VCC
OE 1
24 VCC
D0
2
23 Q0
D0
2
23 Q0
D1
3
22 Q1
D1
3
22 Q1
D2
4
21 Q2
D2
4
21 Q2
D3
5
20 Q3
D3
5
20 Q3
D4
6
19 Q4
D4
6
19 Q4
D5
7
18 Q5
D5
7
18 Q5
D6
8
17 Q6
D6
8
17 Q6
D7
9
16 Q7
D7
9
16 Q7
D8 10
15 Q8
D8 10
15 Q8
D9 11
14 Q9
D9 11
14 Q9
GND 12
13 LE
GND 12
13 LE
SF01279
SF01282
LOGIC SYMBOL for 74F841
LOGIC SYMBOL for 74F842
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23
22
21
20
19
18
17
16
15
14
13
LE
13
LE
1
OE
1
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23
22
21
20
19
18
17
16
15
14
VCC = Pin 24
GND = Pin 12
VCC = Pin 24
GND = Pin 12
SF01280
LOGIC SYMBOL (IEEE/IEC) for 74F841
1
13
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
EN
13
C1
EN
C1
23
2
3
22
3
22
4
21
4
21
5
20
5
20
6
19
6
19
7
18
7
18
8
17
8
17
9
16
9
16
10
15
10
15
11
14
11
14
2
1D
SF01281
1999 Jun 23
SF01283
1D
23
SF01284
3
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F843
OE 1
24 VCC
D0
2
23 Q0
D1
3
22 Q1
D2
4
21 Q2
D3
5
20 Q3
D4
6
19 Q4
D5
7
18 Q5
D6
8
17 Q6
D7
9
16 Q7
D8 10
15 Q8
MR 11
14 PRE
GND 12
13 LE
SF01285
LOGIC SYMBOL for 74F843
13
LE
14
PRE
11
MR
1
OE
2
3
4
5
6
7
8
9
10
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
23
22
21
20
19
18
17
16
15
VCC = Pin 24
GND = Pin 12
SF01286
LOGIC SYMBOL (IEEE/IEC) for 74F843
1
11
EN
R
14
S2
13
2
C1
1D
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
SF01287
1999 Jun 23
4
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
PIN CONFIGURATION for 74F845
OE0
1
PIN CONFIGURATION for 74F846
OE0
1
24 VCC
OE1
2
23 OE2
24 VCC
OE1
2
23 OE2
D0
3
22 Q0
D0
3
22 Q0
D1
4
21 Q1
D1
4
21 Q1
D2
5
20 Q2
D2
5
20 Q2
19 Q3
D3
6
19 Q3
D3
6
D4
7
18 Q4
D4
7
18 Q4
D5
8
17 Q5
D5
8
17 Q5
D6
9
16 Q6
D6
9
16 Q6
D7 10
15 Q7
D7 10
15 Q7
MR 11
14 PRE
MR 11
14 PRE
GND 12
GND 12
13 LE
13 LE
SF01291
SF01294
LOGIC SYMBOL for 74F845
LOGIC SYMBOL for 74F846
3
4
5
6
7
8
9
10
D0
D1
D2
D3
D4
D5
D6
D7
13
LE
13
LE
14
PRE
14
PRE
11
MR
11
MR
1
OE0
1
OE0
2
OE1
2
OE1
23
OE2
23
OE2
VCC = Pin 24
GND = Pin 12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
22
21
20
19
18
17
16
15
VCC = Pin 24
GND = Pin 12
3
4
5
6
7
8
9
10
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
22
21
20
19
18
17
16
15
SF01292
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F845
1
2
LOGIC SYMBOL (IEEE/IEC) for 74F846
1
&
2
EN
23
14
11
13
3
EN
23
14
S2
11
R
13
C1
1D
22
3
S2
R
C1
1D
22
4
21
4
21
5
20
5
20
6
19
6
19
7
18
7
18
8
17
8
17
9
16
9
16
10
15
10
15
SF01293A
1999 Jun 23
&
SF01296A
5
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F841
D0
D1
2
D2
3
D
L
LE
OE
D3
4
D
Q
L
D4
5
D
Q
L
D5
6
D
Q
D6
7
D
L
Q
D7
8
D
L
Q
L
D
Q
D8
10
9
L
D
C
Q
L
D9
11
D
Q
L
D
Q
L
Q
13
1
23
Q0
VCC = Pin 24
GND = Pin 12
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF01297
LOGIC DIAGRAM for 74F842
D0
D1
2
D2
3
D
L
LE
OE
D3
4
D
Q
L
D4
5
D
Q
L
D5
6
D
Q
D6
7
D
L
Q
D7
8
D
L
Q
L
D
Q
D8
10
9
L
D
C
Q
L
D9
11
D
Q
L
D
Q
Q
13
1
23
Q0
VCC = Pin 24
GND = Pin 12
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
OUTPUTS
INPUTS
74F841
74F842
OE
LE
Dn
Qn
Qn
L
H
L
L
H
L
H
H
H
L
L
↓
l
L
H
L
↓
h
H
L
H
X
X
Z
Z
L
L
X
NC
NC
OPERATING MODE
Transparent
Latched
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
1999 Jun 23
15
Q8
14
Q9
SF01298
FUNCTION TABLE for 74F841 and 74F842
H =
L =
h =
l =
↓ =
X =
NC=
Z =
L
6
High Impedance
Hold
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F843
D0
PRE
LE
OE
D2
D3
D4
D5
D6
D7
D8
10
3
4
5
6
7
8
9
D P
D P
D P
D P
D P
D P
D P
D P
14
L
MR
D1
2
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
D P
Q
L
C
11
13
1
23
Q0
VCC = Pin 24
GND = Pin 12
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
OUTPUTS
INPUTS
74F843
OPERATING MODE
OE
PRE
MR
LE
Dn
Qn
L
L
X
X
X
H
Preset
L
H
L
X
X
L
Clear
L
H
H
H
L
L
L
H
H
H
H
H
L
H
H
↓
l
L
L
H
H
↓
h
H
H
X
X
X
X
Z
L
H
H
L
X
NC
Transparent
Latched
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
1999 Jun 23
15
Q8
SF01299
FUNCTION TABLE for 74F843
H =
L =
h =
l =
↓ =
X =
NC=
Z =
Q
7
High Impedance
Hold
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
LOGIC DIAGRAM for 74F845
D0
PRE
D1
LE
OE0
OE1
OE2
D3
D4
D5
D6
D7
10
4
5
6
7
8
9
D P
D P
D P
D P
D P
D P
D P
14
L
MR
D2
3
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
D P
Q
L
C
Q
11
13
1
2
23
22
Q0
VCC = Pin 24
GND = Pin 12
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF01301
LOGIC DIAGRAM for 74F846
D1
D0
PRE
LE
OE0
OE1
OE2
D3
D4
D5
D6
D7
10
4
5
6
7
8
9
D P
D P
D P
D P
D P
D P
D P
14
L
MR
D2
3
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
Q
L
C
D P
Q
L
C
Q
11
13
1
2
23
22
Q0
VCC = Pin 24
GND = Pin 12
21
Q1
20
Q2
19
Q3
18
Q4
17
Q5
16
Q6
15
Q7
SF01302
FUNCTION TABLE for 74F845 and 74F846
OUTPUTS
INPUTS
74F845
74F846
OPERATING MODE
OE
PRE
MR
LE
Dn
Qn
Qn
L
L
X
X
X
H
H
Preset
L
H
L
X
X
L
L
Clear
L
H
H
H
L
L
H
L
H
H
H
H
H
L
L
H
H
↓
l
L
H
L
H
H
↓
h
H
L
H
X
X
X
X
Z
Z
L
H
H
L
X
NC
NC
Transparent
H =
L =
h =
l =
↓ =
X =
NC=
Z =
Latched
High voltage level
Low voltage level
High state one setup time before the High-to-Low LE transition
Low state one setup time before the High-to-Low LE transition
High-to-Low transition
Don’t care
No change
High impedance “off” state
1999 Jun 23
8
High Impedance
Hold
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
VCC
Supply voltage
–0.5 to +7.0
V
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in High output state
–0.5 to VCC
V
IOUT
Current applied to output in Low output state
Tamb
Operating free-air temperature range
Tstg
Storage temperature range
84
mA
0 to +70
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIK
Input clamp current
–18
mA
IOH
High-level output current
–24
mA
IOL
Low-level output current
48
mA
Tamb
Operating free-air temperature range
+70
°C
1999 Jun 23
0
9
V
V
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
LIMITS
TEST CONDITIONS1
PARAMETER
MIN
IOH
15mA
O = –15mA
VOH
O
VCC = MIN,,
VIL = MAX, VIH = MIN
High level output voltage
High-level
IOH
24mA
O = –24mA
TYP2
UNIT
MAX
±10%VCC
2.2
±5%VCC
2.2
±10%VCC
2.0
V
±5%VCC
2.0
V
V
3.3
V
IOL = 32mA
±10%VCC
0.38
0.55
V
IOL = 48mA
±5%VCC
0.38
0.55
V
–0.73
–1.2
V
VCC = 0.0V, VI = 7.0V
100
µA
VCC = MAX, VI = 2.7V
20
µA
VCC = MAX, VI = 0.5V
–20
µA
Off-state output current,
High-level voltage applied
VCC = MAX, VO = 2.7V
50
µA
IOZL
Off-state output current,
Low-level voltage applied
VCC = MAX, VO = 0.5V
–50
µA
IOS
Short-circuit output current3
–225
mA
50
65
mA
60
80
mA
ICCZ
70
92
mA
ICCH
40
60
mA
65
90
mA
ICCZ
60
90
mA
ICCH
65
90
mA
75
100
mA
ICCZ
85
115
mA
ICCH
50
70
mA
70
95
mA
70
95
mA
VCC = MIN,,
VIL = MAX, VIH = MIN
VOL
O
Low level output voltage
Low-level
VIK
Input clamp voltage
II
Input current at maximum input voltage
IIH
High-level input current
IIL
Low-level input current
IOZH
VCC = MIN, II = IIK
VCC = MAX
ICCH
74F841
74F842
ICC
Supply
y current
(total)
74F843
74F845
74F846
ICCL
VCC = MAX
ICCL
VCC = MAX
ICCL
VCC = MAX
ICCL
VCC = MAX
ICCZ
–100
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, IOS tests should be performed last.
1999 Jun 23
10
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
Waveform 1, 2
2.0
2.5
4.0
4.5
7.5
7.5
2.0
2.5
8.0
8.0
ns
tPLH
tPHL
Propagation delay
Dn to Qn
tPLH
tPHL
Propagation delay
LE to Qn
Waveform 1, 2
4.5
4.0
6.5
6.0
9.5
9.0
4.0
3.5
10.0
9.5
ns
tPLH
tPHL
Propagation delay
Dn to Qn
Waveform 1, 2
3.5
3.0
5.5
5.0
8.5
8.0
4.5
4.0
9.0
8.5
ns
tPLH
tPHL
Propagation delay
LE to Qn
Waveform 1, 2
5.0
4.5
7.0
6.5
10.0
9.0
3.0
3.0
10.5
9.5
ns
tPZH
tPZL
Output enable time
High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
2.5
4.0
4.5
6.0
8.0
9.5
2.0
3.0
8.5
10.5
ns
tPHZ
tPLZ
Output disable time
High or Low-level OEn to Qn or Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
ns
74F841
74F842
AC SETUP REQUIREMENTS for 74F841/74F842
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
ts(H)
ts(L)
Setup time, High or Low
Dn to LE
th(H)
th(L)
Hold time, High or Low
Dn to LE
tw(H)
LE pulse width, High
th(H)
th(L)
Hold time, High or Low
Dn to LE
tw(H)
LE pulse width, High
1999 Jun 23
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
0.0
0.0
1.0
1.0
ns
Waveform 4
2.5
3.0
3.0
4.0
ns
Waveform 4
3.5
4.0
ns
Waveform 4
3.0
3.5
3.5
4.5
ns
Waveform 4
3.0
3.0
ns
74F841
74F842
11
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F843/74F845
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
Waveform 1, 2
2.0
2.5
4.5
4.5
7.5
8.0
2.0
2.5
8.5
8.5
ns
tPLH
tPHL
Propagation delay
LE to Qn
Waveform 1, 2
4.5
4.0
6.5
6.0
9.5
8.5
4.5
4.0
10.0
8.5
ns
tPLH
Propagation delay
PRE to Qn
Waveform 3
3.5
5.5
8.5
3.0
9.0
ns
tPHL
Propagation delay
MR to Qn
Waveform 3
2.0
4.5
7.5
2.0
8.0
ns
tPZH
tPZL
Output enable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
2.5
4.0
4.5
6.0
7.5
9.5
2.0
3.0
8.0
10.5
ns
tPHZ
tPLZ
Output disable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
ns
AC SETUP REQUIREMENTS for 74F843/74F845
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
ts(H)
ts(L)
Setup time, High or Low
Dn to LE
Waveform 4
1.0
1.0
0.0
0.0
ns
th(H)
th(L)
Hold time, High or Low
Dn to LE
Waveform 4
3.0
4.0
3.0
4.0
ns
tw(H)
LE pulse width, High
Waveform 4
3.0
3.0
ns
tw(L)
PRE pulse width, Low
Waveform 3
4.0
5.0
ns
tw(H)
MR pulse width, Low
Waveform 3
4.0
5.0
ns
tREC
PRE recovery time
Waveform 3
0.0
0.0
ns
tREC
MR recovery time
Waveform 3
3.5
4.5
ns
1999 Jun 23
12
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC ELECTRICAL CHARACTERISTICS for 74F846
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
Waveform 1, 2
3.5
3.0
5.5
5.0
8.5
8.0
3.0
3.0
9.5
8.5
ns
tPLH
tPHL
Propagation delay
LE to Qn
Waveform 1, 2
5.0
4.5
7.0
6.5
10.0
9.0
5.0
4.5
10.5
9.5
ns
tPLH
Propagation delay
PRE to Qn
Waveform 3
3.5
5.5
8.5
3.0
9.5
ns
tPHL
Propagation delay
MR to Qn
Waveform 3
5.0
7.0
10.0
4.5
10.5
ns
tPZH
tPZL
Output enable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
2.5
4.0
5.0
6.0
7.5
9.5
2.0
3.0
8.0
10.5
ns
tPHZ
tPLZ
Output disable time
High or Low-level OEn to Qn
Waveform 5
Waveform 6
1.0
1.0
4.5
5.0
8.0
8.0
1.0
1.0
8.5
8.5
ns
AC SETUP REQUIREMENTS for 74F846
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
ts(H)
ts(L)
Setup time, High or Low
Dn to LE
Waveform 4
0.0
0.0
0.0
0.0
ns
th(H)
th(L)
Hold time, High or Low
Dn to LE
Waveform 4
3.0
4.0
3.0
4.0
ns
tw(H)
LE pulse width, High
Waveform 4
3.0
3.0
ns
tw(L)
PRE pulse width, Low
Waveform 3
4.0
5.0
ns
tw(H)
MR pulse width, Low
Waveform 3
4.0
5.0
ns
tREC
PRE recovery time
Waveform 3
0.0
0.0
ns
tREC
MR recovery time
Waveform 3
3.5
4.5
ns
1999 Jun 23
13
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn, LE
VM
VM
tPLH
tPHL
Qn
VM
Dn, LE
VM
VM
VM
tPHL
tPLH
VM
Qn
VM
SF01303
Waveform 1.
PRE,
MR
VM
SF01304
Propagation Delay, Non-Inverting Path
tw(L)
Waveform 2.
Dn
VM
tREC
LE
VM
LE
Propagation Delay, Inverting Path
VM
VM
VM
VM
ts(H)
th(H)
ts(L)
th(L)
VM
VM
VM
tw(H)
SF01306
tPLH
Qn, Qn
Waveform 4.
VM
Data Setup and Hold Times
tPHL
Qn, Qn
VM
SF01305
Waveform 3. Master Reset and Preset Pulse Width,
Master Reset and Preset to Output Delay,
and Master Reset and Preset to Latch Enable Recovery Time
OEn
Qn, Qn
VM
VM
tPZH
tPHZ
OEn
VOH -0.3V
VM
VM
tPZL
VM
Qn, Qn
tPLZ
3.5V
VM
0V
VOL +0.3V
SF00509
SF00510
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable time from Low Level
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
1999 Jun 23
14
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for 3-State Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00777
1999 Jun 23
15
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
DIP24: plastic dual in-line package; 24 leads (300 mil)
1999 Jun 23
16
SOT222-1
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
SO24: plastic small outline package; 24 leads; body width 7.5 mm
1999 Jun 23
17
SOT137-1
Philips Semiconductors
Product specification
74F841/74F842/74F843/
74F845/74F846
Bus interface latches
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-99
Document order number:
1999 Jun 23
18
9397 750 06143
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